X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Fflash%2Fnor%2Ffm3.c;h=15a08f701adc779b631e0ae3bbf9cf74abadb05d;hb=3d135a5c70db67ed13cc93eeab0b700f6ef8a412;hp=d3d143f60b35dc24d2af126ea439b9cc4086b58f;hpb=36bc83b174e4ac9741f325fc20fa01885e10f85e;p=openocd.git diff --git a/src/flash/nor/fm3.c b/src/flash/nor/fm3.c index d3d143f60b..15a08f701a 100644 --- a/src/flash/nor/fm3.c +++ b/src/flash/nor/fm3.c @@ -17,9 +17,7 @@ * GNU General Public License for more details. * * * * You should have received a copy of the GNU General Public License * - * along with this program; if not, write to the * - * Free Software Foundation, Inc., * - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * + * along with this program. If not, see . * ***************************************************************************/ #ifdef HAVE_CONFIG_H @@ -63,7 +61,7 @@ enum fm3_flash_type { struct fm3_flash_bank { enum fm3_variant variant; enum fm3_flash_type flashtype; - int probed; + bool probed; }; FLASH_BANK_COMMAND_HANDLER(fm3_flash_bank_command) @@ -134,7 +132,7 @@ FLASH_BANK_COMMAND_HANDLER(fm3_flash_bank_command) return ERROR_FLASH_BANK_INVALID; } - fm3_info->probed = 0; + fm3_info->probed = false; return ERROR_OK; } @@ -203,29 +201,30 @@ static int fm3_busy_wait(struct target *target, uint32_t offset, int timeout_ms) return retval; } -static int fm3_erase(struct flash_bank *bank, int first, int last) +static int fm3_erase(struct flash_bank *bank, unsigned int first, + unsigned int last) { struct fm3_flash_bank *fm3_info = bank->driver_priv; struct target *target = bank->target; int retval = ERROR_OK; - uint32_t u32DummyRead; - int sector, odd; - uint32_t u32FlashType; - uint32_t u32FlashSeqAddress1; - uint32_t u32FlashSeqAddress2; + uint32_t u32_dummy_read; + int odd; + uint32_t u32_flash_type; + uint32_t u32_flash_seq_address1; + uint32_t u32_flash_seq_address2; struct working_area *write_algorithm; struct reg_param reg_params[3]; struct armv7m_algorithm armv7m_info; - u32FlashType = (uint32_t) fm3_info->flashtype; + u32_flash_type = (uint32_t) fm3_info->flashtype; - if (u32FlashType == fm3_flash_type1) { - u32FlashSeqAddress1 = 0x00001550; - u32FlashSeqAddress2 = 0x00000AA8; - } else if (u32FlashType == fm3_flash_type2) { - u32FlashSeqAddress1 = 0x00000AA8; - u32FlashSeqAddress2 = 0x00000554; + if (u32_flash_type == fm3_flash_type1) { + u32_flash_seq_address1 = 0x00001550; + u32_flash_seq_address2 = 0x00000AA8; + } else if (u32_flash_type == fm3_flash_type2) { + u32_flash_seq_address1 = 0x00000AA8; + u32_flash_seq_address2 = 0x00000554; } else { LOG_ERROR("Flash/Device type unknown!"); return ERROR_FLASH_OPERATION_FAILED; @@ -262,7 +261,7 @@ static int fm3_erase(struct flash_bank *bank, int first, int last) 0x00, 0xBE, /* BKPT #0 */ }; - LOG_INFO("Fujitsu MB9[A/B]FXXX: Sector Erase ... (%d to %d)", first, last); + LOG_INFO("Fujitsu MB9[A/B]FXXX: Sector Erase ... (%u to %u)", first, last); /* disable HW watchdog */ retval = target_write_u32(target, 0x40011C00, 0x1ACCE551); @@ -277,13 +276,13 @@ static int fm3_erase(struct flash_bank *bank, int first, int last) if (retval != ERROR_OK) return retval; - /* FASZR = 0x01, Enables CPU Programming Mode (16-bit Flash acccess) */ + /* FASZR = 0x01, Enables CPU Programming Mode (16-bit Flash access) */ retval = target_write_u32(target, 0x40000000, 0x0001); if (retval != ERROR_OK) return retval; /* dummy read of FASZR */ - retval = target_read_u32(target, 0x40000000, &u32DummyRead); + retval = target_read_u32(target, 0x40000000, &u32_dummy_read); if (retval != ERROR_OK) return retval; @@ -301,20 +300,20 @@ static int fm3_erase(struct flash_bank *bank, int first, int last) armv7m_info.common_magic = ARMV7M_COMMON_MAGIC; armv7m_info.core_mode = ARM_MODE_THREAD; - init_reg_param(®_params[0], "r0", 32, PARAM_OUT); /* u32FlashSeqAddress1 */ - init_reg_param(®_params[1], "r1", 32, PARAM_OUT); /* u32FlashSeqAddress2 */ + init_reg_param(®_params[0], "r0", 32, PARAM_OUT); /* u32_flash_seq_address1 */ + init_reg_param(®_params[1], "r1", 32, PARAM_OUT); /* u32_flash_seq_address2 */ init_reg_param(®_params[2], "r2", 32, PARAM_OUT); /* offset */ /* write code buffer and use Flash sector erase code within fm3 */ - for (sector = first ; sector <= last ; sector++) { + for (unsigned int sector = first ; sector <= last ; sector++) { uint32_t offset = bank->sectors[sector].offset; for (odd = 0; odd < 2 ; odd++) { if (odd) offset += 4; - buf_set_u32(reg_params[0].value, 0, 32, u32FlashSeqAddress1); - buf_set_u32(reg_params[1].value, 0, 32, u32FlashSeqAddress2); + buf_set_u32(reg_params[0].value, 0, 32, u32_flash_seq_address1); + buf_set_u32(reg_params[1].value, 0, 32, u32_flash_seq_address2); buf_set_u32(reg_params[2].value, 0, 32, offset); retval = target_run_algorithm(target, 0, NULL, 3, reg_params, @@ -337,12 +336,12 @@ static int fm3_erase(struct flash_bank *bank, int first, int last) destroy_reg_param(®_params[1]); destroy_reg_param(®_params[2]); - /* FASZR = 0x02, Enables CPU Run Mode (32-bit Flash acccess) */ + /* FASZR = 0x02, Enables CPU Run Mode (32-bit Flash access) */ retval = target_write_u32(target, 0x40000000, 0x0002); if (retval != ERROR_OK) return retval; - retval = target_read_u32(target, 0x40000000, &u32DummyRead); /* dummy read of FASZR */ + retval = target_read_u32(target, 0x40000000, &u32_dummy_read); /* dummy read of FASZR */ return retval; } @@ -359,22 +358,22 @@ static int fm3_write_block(struct flash_bank *bank, const uint8_t *buffer, struct reg_param reg_params[6]; struct armv7m_algorithm armv7m_info; int retval = ERROR_OK; - uint32_t u32FlashType; - uint32_t u32FlashSeqAddress1; - uint32_t u32FlashSeqAddress2; + uint32_t u32_flash_type; + uint32_t u32_flash_seq_address1; + uint32_t u32_flash_seq_address2; /* Increase buffer_size if needed */ if (buffer_size < (target->working_area_size / 2)) buffer_size = (target->working_area_size / 2); - u32FlashType = (uint32_t) fm3_info->flashtype; + u32_flash_type = (uint32_t) fm3_info->flashtype; - if (u32FlashType == fm3_flash_type1) { - u32FlashSeqAddress1 = 0x00001550; - u32FlashSeqAddress2 = 0x00000AA8; - } else if (u32FlashType == fm3_flash_type2) { - u32FlashSeqAddress1 = 0x00000AA8; - u32FlashSeqAddress2 = 0x00000554; + if (u32_flash_type == fm3_flash_type1) { + u32_flash_seq_address1 = 0x00001550; + u32_flash_seq_address2 = 0x00000AA8; + } else if (u32_flash_type == fm3_flash_type2) { + u32_flash_seq_address1 = 0x00000AA8; + u32_flash_seq_address2 = 0x00000554; } else { LOG_ERROR("Flash/Device type unknown!"); return ERROR_FLASH_OPERATION_FAILED; @@ -402,8 +401,8 @@ static int fm3_write_block(struct flash_bank *bank, const uint8_t *buffer, 0x55, 0xF0, 0x01, 0x05, /* ORRS.W R5, R5, #1 */ 0x5F, 0xF0, 0x80, 0x46, /* MOVS.W R6, #(fm3_FLASH_IF->FASZ) */ 0x35, 0x60, /* STR R5, [R6] */ - /* u32DummyRead = fm3_FLASH_IF->FASZ; */ - 0x28, 0x4D, /* LDR.N R5, ??u32DummyRead */ + /* u32_dummy_read = fm3_FLASH_IF->FASZ; */ + 0x28, 0x4D, /* LDR.N R5, ??u32_dummy_read */ 0x5F, 0xF0, 0x80, 0x46, /* MOVS.W R6, #(fm3_FLASH_IF->FASZ) */ 0x36, 0x68, /* LDR R6, [R6] */ 0x2E, 0x60, /* STR R6, [R5] */ @@ -493,8 +492,8 @@ static int fm3_write_block(struct flash_bank *bank, const uint8_t *buffer, 0x55, 0xF0, 0x02, 0x05, /* ORRS.W R5, R5, #2 */ 0x5F, 0xF0, 0x80, 0x46, /* MOVS.W R6, #(fm3_FLASH_IF->FASZ) */ 0x35, 0x60, /* STR R5, [R6] */ - /* u32DummyRead = fm3_FLASH_IF->FASZ; */ - 0x04, 0x4D, /* LDR.N R5, ??u32DummyRead */ + /* u32_dummy_read = fm3_FLASH_IF->FASZ; */ + 0x04, 0x4D, /* LDR.N R5, ??u32_dummy_read */ 0x5F, 0xF0, 0x80, 0x46, /* MOVS.W R6, #(fm3_FLASH_IF->FASZ) */ 0x36, 0x68, /* LDR R6, [R6] */ 0x2E, 0x60, /* STR R6, [R5] */ @@ -509,7 +508,7 @@ static int fm3_write_block(struct flash_bank *bank, const uint8_t *buffer, /* SRAM basic-address + 8.These address pointers will be patched, if a */ /* different start address in RAM is used (e.g. for Flash type 2)! */ /* Default SRAM basic-address is 0x20000000. */ - 0x00, 0x00, 0x00, 0x20, /* u32DummyRead address in RAM (0x20000000) */ + 0x00, 0x00, 0x00, 0x20, /* u32_dummy_read address in RAM (0x20000000) */ 0x04, 0x00, 0x00, 0x20 /* u32FlashResult address in RAM (0x20000004) */ }; @@ -549,7 +548,7 @@ static int fm3_write_block(struct flash_bank *bank, const uint8_t *buffer, return retval; /* Patching 'local variable address' */ - /* Algorithm: u32DummyRead: */ + /* Algorithm: u32_dummy_read: */ retval = target_write_u32(target, (write_algorithm->address + 8) + sizeof(fm3_flash_write_code) - 8, (write_algorithm->address)); if (retval != ERROR_OK) @@ -596,8 +595,8 @@ static int fm3_write_block(struct flash_bank *bank, const uint8_t *buffer, buf_set_u32(reg_params[0].value, 0, 32, source->address); buf_set_u32(reg_params[1].value, 0, 32, address); buf_set_u32(reg_params[2].value, 0, 32, thisrun_count); - buf_set_u32(reg_params[3].value, 0, 32, u32FlashSeqAddress1); - buf_set_u32(reg_params[4].value, 0, 32, u32FlashSeqAddress2); + buf_set_u32(reg_params[3].value, 0, 32, u32_flash_seq_address1); + buf_set_u32(reg_params[4].value, 0, 32, u32_flash_seq_address2); retval = target_run_algorithm(target, 0, NULL, 6, reg_params, (write_algorithm->address + 8), 0, 1000, &armv7m_info); @@ -658,7 +657,7 @@ static int fm3_probe(struct flash_bank *bank) */ num_pages = 10; /* max number of Flash pages for malloc */ - fm3_info->probed = 0; + fm3_info->probed = false; bank->sectors = malloc(sizeof(struct flash_sector) * num_pages); bank->base = 0x00000000; @@ -798,7 +797,7 @@ static int fm3_probe(struct flash_bank *bank) bank->sectors[9].is_protected = -1; } - fm3_info->probed = 1; + fm3_info->probed = true; return ERROR_OK; } @@ -817,25 +816,25 @@ static int fm3_chip_erase(struct flash_bank *bank) struct target *target = bank->target; struct fm3_flash_bank *fm3_info2 = bank->driver_priv; int retval = ERROR_OK; - uint32_t u32DummyRead; - uint32_t u32FlashType; - uint32_t u32FlashSeqAddress1; - uint32_t u32FlashSeqAddress2; + uint32_t u32_dummy_read; + uint32_t u32_flash_type; + uint32_t u32_flash_seq_address1; + uint32_t u32_flash_seq_address2; struct working_area *write_algorithm; struct reg_param reg_params[3]; struct armv7m_algorithm armv7m_info; - u32FlashType = (uint32_t) fm3_info2->flashtype; + u32_flash_type = (uint32_t) fm3_info2->flashtype; - if (u32FlashType == fm3_flash_type1) { + if (u32_flash_type == fm3_flash_type1) { LOG_INFO("*** Erasing mb9bfxxx type"); - u32FlashSeqAddress1 = 0x00001550; - u32FlashSeqAddress2 = 0x00000AA8; - } else if (u32FlashType == fm3_flash_type2) { + u32_flash_seq_address1 = 0x00001550; + u32_flash_seq_address2 = 0x00000AA8; + } else if (u32_flash_type == fm3_flash_type2) { LOG_INFO("*** Erasing mb9afxxx type"); - u32FlashSeqAddress1 = 0x00000AA8; - u32FlashSeqAddress2 = 0x00000554; + u32_flash_seq_address1 = 0x00000AA8; + u32_flash_seq_address2 = 0x00000554; } else { LOG_ERROR("Flash/Device type unknown!"); return ERROR_FLASH_OPERATION_FAILED; @@ -892,7 +891,7 @@ static int fm3_chip_erase(struct flash_bank *bank) return retval; /* dummy read of FASZR */ - retval = target_read_u32(target, 0x40000000, &u32DummyRead); + retval = target_read_u32(target, 0x40000000, &u32_dummy_read); if (retval != ERROR_OK) return retval; @@ -910,11 +909,11 @@ static int fm3_chip_erase(struct flash_bank *bank) armv7m_info.common_magic = ARMV7M_COMMON_MAGIC; armv7m_info.core_mode = ARM_MODE_THREAD; - init_reg_param(®_params[0], "r0", 32, PARAM_OUT); /* u32FlashSeqAddress1 */ - init_reg_param(®_params[1], "r1", 32, PARAM_OUT); /* u32FlashSeqAddress2 */ + init_reg_param(®_params[0], "r0", 32, PARAM_OUT); /* u32_flash_seq_address1 */ + init_reg_param(®_params[1], "r1", 32, PARAM_OUT); /* u32_flash_seq_address2 */ - buf_set_u32(reg_params[0].value, 0, 32, u32FlashSeqAddress1); - buf_set_u32(reg_params[1].value, 0, 32, u32FlashSeqAddress2); + buf_set_u32(reg_params[0].value, 0, 32, u32_flash_seq_address1); + buf_set_u32(reg_params[1].value, 0, 32, u32_flash_seq_address2); retval = target_run_algorithm(target, 0, NULL, 2, reg_params, write_algorithm->address, 0, 100000, &armv7m_info); @@ -929,7 +928,7 @@ static int fm3_chip_erase(struct flash_bank *bank) destroy_reg_param(®_params[0]); destroy_reg_param(®_params[1]); - retval = fm3_busy_wait(target, u32FlashSeqAddress2, 20000); /* 20s timeout */ + retval = fm3_busy_wait(target, u32_flash_seq_address2, 20000); /* 20s timeout */ if (retval != ERROR_OK) return retval; @@ -938,15 +937,13 @@ static int fm3_chip_erase(struct flash_bank *bank) if (retval != ERROR_OK) return retval; - retval = target_read_u32(target, 0x40000000, &u32DummyRead); /* dummy read of FASZR */ + retval = target_read_u32(target, 0x40000000, &u32_dummy_read); /* dummy read of FASZR */ return retval; } COMMAND_HANDLER(fm3_handle_chip_erase_command) { - int i; - if (CMD_ARGC < 1) return ERROR_COMMAND_SYNTAX_ERROR; @@ -957,12 +954,12 @@ COMMAND_HANDLER(fm3_handle_chip_erase_command) if (fm3_chip_erase(bank) == ERROR_OK) { /* set all sectors as erased */ - for (i = 0; i < bank->num_sectors; i++) + for (unsigned int i = 0; i < bank->num_sectors; i++) bank->sectors[i].is_erased = 1; - command_print(CMD_CTX, "fm3 chip erase complete"); + command_print(CMD, "fm3 chip erase complete"); } else { - command_print(CMD_CTX, "fm3 chip erase failed"); + command_print(CMD, "fm3 chip erase failed"); } return ERROR_OK; @@ -990,7 +987,7 @@ static const struct command_registration fm3_command_handlers[] = { COMMAND_REGISTRATION_DONE }; -struct flash_driver fm3_flash = { +const struct flash_driver fm3_flash = { .name = "fm3", .commands = fm3_command_handlers, .flash_bank_command = fm3_flash_bank_command, @@ -999,4 +996,5 @@ struct flash_driver fm3_flash = { .probe = fm3_probe, .auto_probe = fm3_auto_probe, .erase_check = default_flash_blank_check, + .free_driver_priv = default_flash_free_driver_priv, };