X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Fflash%2Fnor%2Fstm32f1x.c;h=26231e9cbbab789cda33438cfc533e20b5759dee;hb=b801452d42c189a13f6cc1ff769fc98bededc7c5;hp=91f2aef86246f11d5450aa5a870a9b59efc17637;hpb=64c2e03b23d9cadc1b919d38e902a079d015ddc6;p=openocd.git diff --git a/src/flash/nor/stm32f1x.c b/src/flash/nor/stm32f1x.c index 91f2aef862..26231e9cbb 100644 --- a/src/flash/nor/stm32f1x.c +++ b/src/flash/nor/stm32f1x.c @@ -29,7 +29,7 @@ #include "imp.h" #include #include -#include +#include /* stm32x register locations */ @@ -131,7 +131,7 @@ struct stm32x_flash_bank { static int stm32x_mass_erase(struct flash_bank *bank); static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id); static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer, - uint32_t address, uint32_t count); + uint32_t address, uint32_t hwords_count); /* flash bank stm32x 0 0 */ @@ -151,6 +151,9 @@ FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command) stm32x_info->register_base = FLASH_REG_BASE_B0; stm32x_info->user_bank_size = bank->size; + /* The flash write must be aligned to a halfword boundary */ + bank->write_start_alignment = bank->write_end_alignment = 2; + return ERROR_OK; } @@ -182,19 +185,19 @@ static int stm32x_wait_status_busy(struct flash_bank *bank, int timeout) break; if (timeout-- <= 0) { LOG_ERROR("timed out waiting for flash"); - return ERROR_FAIL; + return ERROR_FLASH_BUSY; } alive_sleep(1); } if (status & FLASH_WRPRTERR) { LOG_ERROR("stm32x device protected"); - retval = ERROR_FAIL; + retval = ERROR_FLASH_PROTECTED; } if (status & FLASH_PGERR) { - LOG_ERROR("stm32x device programming failed"); - retval = ERROR_FAIL; + LOG_ERROR("stm32x device programming failed / flash not erased"); + retval = ERROR_FLASH_OPERATION_FAILED; } /* Clear but report errors */ @@ -329,12 +332,14 @@ static int stm32x_write_options(struct flash_bank *bank) target_buffer_set_u16(target, opt_bytes + 12, (stm32x_info->option_bytes.protection >> 16) & 0xff); target_buffer_set_u16(target, opt_bytes + 14, (stm32x_info->option_bytes.protection >> 24) & 0xff); + /* Block write is preferred in favour of operation with ancient ST-Link + * firmwares without 16-bit memory access. See + * 480: flash: stm32f1x: write option bytes using the loader + * https://review.openocd.org/c/openocd/+/480 + */ retval = stm32x_write_block(bank, opt_bytes, STM32_OB_RDP, sizeof(opt_bytes) / 2); - if (retval != ERROR_OK) { - if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) - LOG_ERROR("working area required to erase options bytes"); + if (retval != ERROR_OK) return retval; - } retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_LOCK); if (retval != ERROR_OK) @@ -349,7 +354,7 @@ static int stm32x_protect_check(struct flash_bank *bank) uint32_t protection; int retval = stm32x_check_operation_supported(bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; /* medium density - each bit refers to a 4 sector protection block @@ -402,8 +407,6 @@ static int stm32x_erase(struct flash_bank *bank, unsigned int first, retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT); if (retval != ERROR_OK) return retval; - - bank->sectors[i].is_erased = 1; } retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK); @@ -444,17 +447,16 @@ static int stm32x_protect(struct flash_bank *bank, int set, unsigned int first, return stm32x_write_options(bank); } -static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer, - uint32_t address, uint32_t count) +static int stm32x_write_block_async(struct flash_bank *bank, const uint8_t *buffer, + uint32_t address, uint32_t hwords_count) { struct stm32x_flash_bank *stm32x_info = bank->driver_priv; struct target *target = bank->target; - uint32_t buffer_size = 16384; + uint32_t buffer_size; struct working_area *write_algorithm; struct working_area *source; - struct reg_param reg_params[5]; struct armv7m_algorithm armv7m_info; - int retval = ERROR_OK; + int retval; static const uint8_t stm32x_flash_write_code[] = { #include "../../../contrib/loaders/flash/stm32/stm32f1x.inc" @@ -475,19 +477,28 @@ static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer, } /* memory buffer */ - while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) { - buffer_size /= 2; - buffer_size &= ~3UL; /* Make sure it's 4 byte aligned */ - if (buffer_size <= 256) { - /* we already allocated the writing code, but failed to get a - * buffer, free the algorithm */ - target_free_working_area(target, write_algorithm); - - LOG_WARNING("no large enough working area available, can't do block memory writes"); - return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; - } + buffer_size = target_get_working_area_avail(target); + buffer_size = MIN(hwords_count * 2, MAX(buffer_size, 256)); + /* Normally we allocate all available working area. + * MIN shrinks buffer_size if the size of the written block is smaller. + * MAX prevents using async algo if the available working area is smaller + * than 256, the following allocation fails with + * ERROR_TARGET_RESOURCE_NOT_AVAILABLE and slow flashing takes place. + */ + + retval = target_alloc_working_area(target, buffer_size, &source); + /* Allocated size is always 32-bit word aligned */ + if (retval != ERROR_OK) { + target_free_working_area(target, write_algorithm); + LOG_WARNING("no large enough working area available, can't do block memory writes"); + /* target_alloc_working_area() may return ERROR_FAIL if area backup fails: + * convert any error to ERROR_TARGET_RESOURCE_NOT_AVAILABLE + */ + return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } + struct reg_param reg_params[5]; + init_reg_param(®_params[0], "r0", 32, PARAM_IN_OUT); /* flash base (in), status (out) */ init_reg_param(®_params[1], "r1", 32, PARAM_OUT); /* count (halfword-16bit) */ init_reg_param(®_params[2], "r2", 32, PARAM_OUT); /* buffer start */ @@ -495,7 +506,7 @@ static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer, init_reg_param(®_params[4], "r4", 32, PARAM_IN_OUT); /* target address */ buf_set_u32(reg_params[0].value, 0, 32, stm32x_info->register_base); - buf_set_u32(reg_params[1].value, 0, 32, count); + buf_set_u32(reg_params[1].value, 0, 32, hwords_count); buf_set_u32(reg_params[2].value, 0, 32, source->address); buf_set_u32(reg_params[3].value, 0, 32, source->address + source->size); buf_set_u32(reg_params[4].value, 0, 32, address); @@ -503,39 +514,73 @@ static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer, armv7m_info.common_magic = ARMV7M_COMMON_MAGIC; armv7m_info.core_mode = ARM_MODE_THREAD; - retval = target_run_flash_async_algorithm(target, buffer, count, 2, + retval = target_run_flash_async_algorithm(target, buffer, hwords_count, 2, 0, NULL, - 5, reg_params, + ARRAY_SIZE(reg_params), reg_params, source->address, source->size, write_algorithm->address, 0, &armv7m_info); if (retval == ERROR_FLASH_OPERATION_FAILED) { - LOG_ERROR("flash write failed at address 0x%"PRIx32, - buf_get_u32(reg_params[4].value, 0, 32)); - - if (buf_get_u32(reg_params[0].value, 0, 32) & FLASH_PGERR) { - LOG_ERROR("flash memory not erased before writing"); - /* Clear but report errors */ - target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), FLASH_PGERR); - } + /* Actually we just need to check for programming errors + * stm32x_wait_status_busy also reports error and clears status bits. + * + * Target algo returns flash status in r0 only if properly finished. + * It is safer to re-read status register. + */ + int retval2 = stm32x_wait_status_busy(bank, 5); + if (retval2 != ERROR_OK) + retval = retval2; - if (buf_get_u32(reg_params[0].value, 0, 32) & FLASH_WRPRTERR) { - LOG_ERROR("flash memory write protected"); - /* Clear but report errors */ - target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), FLASH_WRPRTERR); - } + LOG_ERROR("flash write failed just before address 0x%"PRIx32, + buf_get_u32(reg_params[4].value, 0, 32)); } + for (unsigned int i = 0; i < ARRAY_SIZE(reg_params); i++) + destroy_reg_param(®_params[i]); + target_free_working_area(target, source); target_free_working_area(target, write_algorithm); - destroy_reg_param(®_params[0]); - destroy_reg_param(®_params[1]); - destroy_reg_param(®_params[2]); - destroy_reg_param(®_params[3]); - destroy_reg_param(®_params[4]); + return retval; +} +/** Writes a block to flash either using target algorithm + * or use fallback, host controlled halfword-by-halfword access. + * Flash controller must be unlocked before this call. + */ +static int stm32x_write_block(struct flash_bank *bank, + const uint8_t *buffer, uint32_t address, uint32_t hwords_count) +{ + struct target *target = bank->target; + + /* The flash write must be aligned to a halfword boundary. + * The flash infrastructure ensures it, do just a security check + */ + assert(address % 2 == 0); + + /* try using a block write - on ARM architecture or... */ + int retval = stm32x_write_block_async(bank, buffer, address, hwords_count); + + if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) { + /* if block write failed (no sufficient working area), + * we use normal (slow) single halfword accesses */ + LOG_WARNING("couldn't use block writes, falling back to single memory accesses"); + + while (hwords_count > 0) { + retval = target_write_memory(target, address, 2, 1, buffer); + if (retval != ERROR_OK) + return retval; + + retval = stm32x_wait_status_busy(bank, 5); + if (retval != ERROR_OK) + return retval; + + hwords_count--; + buffer += 2; + address += 2; + } + } return retval; } @@ -543,114 +588,74 @@ static int stm32x_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t offset, uint32_t count) { struct target *target = bank->target; - uint8_t *new_buffer = NULL; if (bank->target->state != TARGET_HALTED) { LOG_ERROR("Target not halted"); return ERROR_TARGET_NOT_HALTED; } - if (offset & 0x1) { - LOG_ERROR("offset 0x%" PRIx32 " breaks required 2-byte alignment", offset); - return ERROR_FLASH_DST_BREAKS_ALIGNMENT; - } + /* The flash write must be aligned to a halfword boundary. + * The flash infrastructure ensures it, do just a security check + */ + assert(offset % 2 == 0); + assert(count % 2 == 0); - /* If there's an odd number of bytes, the data has to be padded. Duplicate - * the buffer and use the normal code path with a single block write since - * it's probably cheaper than to special case the last odd write using - * discrete accesses. */ - if (count & 1) { - new_buffer = malloc(count + 1); - if (new_buffer == NULL) { - LOG_ERROR("odd number of bytes to write and no memory for padding buffer"); - return ERROR_FAIL; - } - LOG_INFO("odd number of bytes to write, padding with 0xff"); - buffer = memcpy(new_buffer, buffer, count); - new_buffer[count++] = 0xff; - } - - uint32_t words_remaining = count / 2; int retval, retval2; /* unlock flash registers */ retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1); if (retval != ERROR_OK) - goto cleanup; + return retval; retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2); if (retval != ERROR_OK) - goto cleanup; + goto reset_pg_and_lock; + /* enable flash programming */ retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PG); if (retval != ERROR_OK) - goto cleanup; + goto reset_pg_and_lock; - /* try using a block write */ - retval = stm32x_write_block(bank, buffer, bank->base + offset, words_remaining); - - if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) { - /* if block write failed (no sufficient working area), - * we use normal (slow) single halfword accesses */ - LOG_WARNING("couldn't use block writes, falling back to single memory accesses"); - - while (words_remaining > 0) { - uint16_t value; - memcpy(&value, buffer, sizeof(uint16_t)); - - retval = target_write_u16(target, bank->base + offset, value); - if (retval != ERROR_OK) - goto reset_pg_and_lock; - - retval = stm32x_wait_status_busy(bank, 5); - if (retval != ERROR_OK) - goto reset_pg_and_lock; - - words_remaining--; - buffer += 2; - offset += 2; - } - } + /* write to flash */ + retval = stm32x_write_block(bank, buffer, bank->base + offset, count / 2); reset_pg_and_lock: retval2 = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK); if (retval == ERROR_OK) retval = retval2; -cleanup: - free(new_buffer); return retval; } static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id) { - /* This check the device CPUID core register to detect - * the M0 from the M3 devices. */ - struct target *target = bank->target; - uint32_t cpuid, device_id_register = 0; + uint32_t device_id_register = 0; - /* Get the CPUID from the ARM Core - * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0432c/DDI0432C_cortex_m0_r0p0_trm.pdf 4.2.1 */ - int retval = target_read_u32(target, 0xE000ED00, &cpuid); - if (retval != ERROR_OK) - return retval; + if (!target_was_examined(target)) { + LOG_ERROR("Target not examined yet"); + return ERROR_TARGET_NOT_EXAMINED; + } - if (((cpuid >> 4) & 0xFFF) == 0xC20) { - /* 0xC20 is M0 devices */ + switch (cortex_m_get_partno_safe(target)) { + case CORTEX_M0_PARTNO: /* STM32F0x devices */ device_id_register = 0x40015800; - } else if (((cpuid >> 4) & 0xFFF) == 0xC23) { - /* 0xC23 is M3 devices */ + break; + case CORTEX_M3_PARTNO: /* STM32F1x devices */ device_id_register = 0xE0042000; - } else if (((cpuid >> 4) & 0xFFF) == 0xC24) { - /* 0xC24 is M4 devices */ + break; + case CORTEX_M4_PARTNO: /* STM32F3x devices */ device_id_register = 0xE0042000; - } else { + break; + case CORTEX_M23_PARTNO: /* GD32E23x devices */ + device_id_register = 0x40015800; + break; + default: LOG_ERROR("Cannot identify target as a stm32x"); return ERROR_FAIL; } /* read stm32 device id register */ - retval = target_read_u32(target, device_id_register, device_id); + int retval = target_read_u32(target, device_id_register, device_id); if (retval != ERROR_OK) return retval; @@ -660,27 +665,32 @@ static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id) static int stm32x_get_flash_size(struct flash_bank *bank, uint16_t *flash_size_in_kb) { struct target *target = bank->target; - uint32_t cpuid, flash_size_reg; + uint32_t flash_size_reg; - int retval = target_read_u32(target, 0xE000ED00, &cpuid); - if (retval != ERROR_OK) - return retval; + if (!target_was_examined(target)) { + LOG_ERROR("Target not examined yet"); + return ERROR_TARGET_NOT_EXAMINED; + } - if (((cpuid >> 4) & 0xFFF) == 0xC20) { - /* 0xC20 is M0 devices */ + switch (cortex_m_get_partno_safe(target)) { + case CORTEX_M0_PARTNO: /* STM32F0x devices */ flash_size_reg = 0x1FFFF7CC; - } else if (((cpuid >> 4) & 0xFFF) == 0xC23) { - /* 0xC23 is M3 devices */ + break; + case CORTEX_M3_PARTNO: /* STM32F1x devices */ flash_size_reg = 0x1FFFF7E0; - } else if (((cpuid >> 4) & 0xFFF) == 0xC24) { - /* 0xC24 is M4 devices */ + break; + case CORTEX_M4_PARTNO: /* STM32F3x devices */ flash_size_reg = 0x1FFFF7CC; - } else { + break; + case CORTEX_M23_PARTNO: /* GD32E23x devices */ + flash_size_reg = 0x1FFFF7E0; + break; + default: LOG_ERROR("Cannot identify target as a stm32x"); return ERROR_FAIL; } - retval = target_read_u16(target, flash_size_reg, flash_size_in_kb); + int retval = target_read_u16(target, flash_size_reg, flash_size_in_kb); if (retval != ERROR_OK) return retval; @@ -757,8 +767,8 @@ static int stm32x_probe(struct flash_bank *bank) page_size = 1024; stm32x_info->ppage_size = 4; max_flash_size_in_kb = 128; - /* GigaDevice GD32F1x0 & GD32F3x0 series devices share DEV_ID - with STM32F101/2/3 medium-density line, + /* GigaDevice GD32F1x0 & GD32F3x0 & GD32E23x series devices + share DEV_ID with STM32F101/2/3 medium-density line, however they use a REV_ID different from any STM32 device. The main difference is another offset of user option bits (like WDG_SW, nRST_STOP, nRST_STDBY) in option byte register @@ -775,6 +785,11 @@ static int stm32x_probe(struct flash_bank *bank) stm32x_info->user_data_offset = 16; stm32x_info->option_offset = 6; break; + case 0x1909: /* gd32e23x */ + stm32x_info->user_data_offset = 16; + stm32x_info->option_offset = 6; + max_flash_size_in_kb = 64; + break; } break; case 0x412: /* stm32f1x low-density */ @@ -985,6 +1000,10 @@ static int get_stm32x_info(struct flash_bank *bank, struct command_invocation *c device_str = "GD32F3x0"; break; + case 0x1909: /* gd32e23x */ + device_str = "GD32E23x"; + break; + case 0x2000: rev_str = "B"; break; @@ -1178,7 +1197,7 @@ static int get_stm32x_info(struct flash_bank *bank, struct command_invocation *c return ERROR_FAIL; } - if (rev_str != NULL) + if (rev_str) command_print_sameline(cmd, "%s - Rev: %s", device_str, rev_str); else command_print_sameline(cmd, "%s - Rev: unknown (0x%04x)", device_str, rev_id); @@ -1196,7 +1215,7 @@ COMMAND_HANDLER(stm32x_handle_lock_command) struct flash_bank *bank; int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; stm32x_info = bank->driver_priv; @@ -1209,7 +1228,7 @@ COMMAND_HANDLER(stm32x_handle_lock_command) } retval = stm32x_check_operation_supported(bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; if (stm32x_erase_options(bank) != ERROR_OK) { @@ -1239,7 +1258,7 @@ COMMAND_HANDLER(stm32x_handle_unlock_command) struct flash_bank *bank; int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; target = bank->target; @@ -1250,7 +1269,7 @@ COMMAND_HANDLER(stm32x_handle_unlock_command) } retval = stm32x_check_operation_supported(bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; if (stm32x_erase_options(bank) != ERROR_OK) { @@ -1281,7 +1300,7 @@ COMMAND_HANDLER(stm32x_handle_options_read_command) struct flash_bank *bank; int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; stm32x_info = bank->driver_priv; @@ -1294,7 +1313,7 @@ COMMAND_HANDLER(stm32x_handle_options_read_command) } retval = stm32x_check_operation_supported(bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; retval = target_read_u32(target, STM32_FLASH_OBR_B0, &optionbyte); @@ -1348,7 +1367,7 @@ COMMAND_HANDLER(stm32x_handle_options_write_command) struct flash_bank *bank; int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; stm32x_info = bank->driver_priv; @@ -1361,11 +1380,11 @@ COMMAND_HANDLER(stm32x_handle_options_write_command) } retval = stm32x_check_operation_supported(bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; retval = stm32x_read_options(bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; /* start with current options */ @@ -1437,7 +1456,7 @@ COMMAND_HANDLER(stm32x_handle_options_load_command) struct flash_bank *bank; int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; struct stm32x_flash_bank *stm32x_info = bank->driver_priv; @@ -1456,7 +1475,7 @@ COMMAND_HANDLER(stm32x_handle_options_load_command) } retval = stm32x_check_operation_supported(bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; /* unlock option flash registers */ @@ -1519,23 +1538,19 @@ COMMAND_HANDLER(stm32x_handle_mass_erase_command) struct flash_bank *bank; int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; retval = stm32x_mass_erase(bank); - if (retval == ERROR_OK) { - /* set all sectors as erased */ - for (unsigned int i = 0; i < bank->num_sectors; i++) - bank->sectors[i].is_erased = 1; - + if (retval == ERROR_OK) command_print(CMD, "stm32x mass erase complete"); - } else + else command_print(CMD, "stm32x mass erase failed"); return retval; } -static const struct command_registration stm32x_exec_command_handlers[] = { +static const struct command_registration stm32f1x_exec_command_handlers[] = { { .name = "lock", .handler = stm32x_handle_lock_command, @@ -1583,20 +1598,20 @@ static const struct command_registration stm32x_exec_command_handlers[] = { COMMAND_REGISTRATION_DONE }; -static const struct command_registration stm32x_command_handlers[] = { +static const struct command_registration stm32f1x_command_handlers[] = { { .name = "stm32f1x", .mode = COMMAND_ANY, .help = "stm32f1x flash command group", .usage = "", - .chain = stm32x_exec_command_handlers, + .chain = stm32f1x_exec_command_handlers, }, COMMAND_REGISTRATION_DONE }; const struct flash_driver stm32f1x_flash = { .name = "stm32f1x", - .commands = stm32x_command_handlers, + .commands = stm32f1x_command_handlers, .flash_bank_command = stm32x_flash_bank_command, .erase = stm32x_erase, .protect = stm32x_protect,