X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Fflash%2Fnor%2Fstm32f2x.c;h=dcaf260d97d807c4eefabddd92ce734471d137be;hb=a5d34202c6880bc9b8d0b326628ba1f2e5b061ff;hp=c1283bb3f4dc382adf4bf896ea3267df6bdde8d5;hpb=9f1529da4fcc7d1e508ab9ea4dc915800d68e730;p=openocd.git
diff --git a/src/flash/nor/stm32f2x.c b/src/flash/nor/stm32f2x.c
index c1283bb3f4..dcaf260d97 100644
--- a/src/flash/nor/stm32f2x.c
+++ b/src/flash/nor/stm32f2x.c
@@ -1,3 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
/***************************************************************************
* Copyright (C) 2005 by Dominic Rath *
* Dominic.Rath@gmx.de *
@@ -7,19 +9,6 @@
* *
* Copyright (C) 2011 Ãyvind Harboe *
* oyvind.harboe@zylin.com *
- * *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program. If not, see . *
***************************************************************************/
#ifdef HAVE_CONFIG_H
@@ -29,7 +18,7 @@
#include "imp.h"
#include
#include
-#include
+#include
/* Regarding performance:
*
@@ -55,7 +44,7 @@
* can be very different.
*
* To reduce testing complexity and dangers of regressions,
- * a seperate file is used for stm32fx2x.
+ * a separate file is used for stm32fx2x.
*
* Sector sizes in kiBytes:
* 1 MiByte part with 4 x 16, 1 x 64, 7 x 128.
@@ -204,7 +193,7 @@ struct stm32x_flash_bank {
bool has_extra_options; /* F42x/43x/469/479/7xx */
bool has_boot_addr; /* F7xx */
bool has_optcr2_pcrop; /* F72x/73x */
- int protection_bits; /* F413/423 */
+ unsigned int protection_bits; /* F413/423 */
uint32_t user_bank_size;
};
@@ -230,7 +219,7 @@ static int stm32x_otp_disable(struct flash_bank *bank)
{
struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
- LOG_INFO("OTP memory bank #%d is disabled for write commands.",
+ LOG_INFO("OTP memory bank #%u is disabled for write commands.",
bank->bank_number);
stm32x_info->otp_unlocked = false;
return ERROR_OK;
@@ -241,11 +230,11 @@ static int stm32x_otp_enable(struct flash_bank *bank)
struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
if (!stm32x_info->otp_unlocked) {
- LOG_INFO("OTP memory bank #%d is is enabled for write commands.",
+ LOG_INFO("OTP memory bank #%u is enabled for write commands.",
bank->bank_number);
stm32x_info->otp_unlocked = true;
} else {
- LOG_WARNING("OTP memory bank #%d is is already enabled for write commands.",
+ LOG_WARNING("OTP memory bank #%u is already enabled for write commands.",
bank->bank_number);
}
return ERROR_OK;
@@ -292,7 +281,7 @@ static int stm32x_wait_status_busy(struct flash_bank *bank, int timeout)
retval = stm32x_get_flash_status(bank, &status);
if (retval != ERROR_OK)
return retval;
- LOG_DEBUG("status: 0x%" PRIx32 "", status);
+ LOG_DEBUG("status: 0x%" PRIx32, status);
if ((status & FLASH_BSY) == 0)
break;
if (timeout-- <= 0) {
@@ -349,7 +338,7 @@ static int stm32x_unlock_reg(struct target *target)
return retval;
if (ctrl & FLASH_LOCK) {
- LOG_ERROR("flash not unlocked STM32_FLASH_CR: %" PRIx32, ctrl);
+ LOG_ERROR("flash not unlocked STM32_FLASH_CR: 0x%" PRIx32, ctrl);
return ERROR_TARGET_FAILURE;
}
@@ -381,7 +370,7 @@ static int stm32x_unlock_option_reg(struct target *target)
return retval;
if (ctrl & OPTCR_LOCK) {
- LOG_ERROR("options not unlocked STM32_FLASH_OPTCR: %" PRIx32, ctrl);
+ LOG_ERROR("options not unlocked STM32_FLASH_OPTCR: 0x%" PRIx32, ctrl);
return ERROR_TARGET_FAILURE;
}
@@ -419,7 +408,7 @@ static int stm32x_read_options(struct flash_bank *bank)
if (retval != ERROR_OK)
return retval;
- /* FLASH_OPTCR1 has quite diffent meanings ... */
+ /* FLASH_OPTCR1 has quite different meanings ... */
if (stm32x_info->has_boot_addr) {
/* for F7xx it contains boot0 and boot1 */
stm32x_info->option_bytes.boot_addr = optiondata;
@@ -522,13 +511,13 @@ static int stm32x_otp_read_protect(struct flash_bank *bank)
{
struct target *target = bank->target;
uint32_t lock_base;
- int i, retval;
+ int retval;
uint8_t lock;
lock_base = stm32x_otp_is_f7(bank) ? STM32F7_OTP_LOCK_BASE
: STM32F2_OTP_LOCK_BASE;
- for (i = 0; i < bank->num_sectors; i++) {
+ for (unsigned int i = 0; i < bank->num_sectors; i++) {
retval = target_read_u8(target, lock_base + i, &lock);
if (retval != ERROR_OK)
return retval;
@@ -538,14 +527,15 @@ static int stm32x_otp_read_protect(struct flash_bank *bank)
return ERROR_OK;
}
-static int stm32x_otp_protect(struct flash_bank *bank, int first, int last)
+static int stm32x_otp_protect(struct flash_bank *bank, unsigned int first,
+ unsigned int last)
{
struct target *target = bank->target;
uint32_t lock_base;
int i, retval;
uint8_t lock;
- assert((0 <= first) && (first <= last) && (last < bank->num_sectors));
+ assert((first <= last) && (last < bank->num_sectors));
lock_base = stm32x_otp_is_f7(bank) ? STM32F7_OTP_LOCK_BASE
: STM32F2_OTP_LOCK_BASE;
@@ -570,7 +560,7 @@ static int stm32x_protect_check(struct flash_bank *bank)
{
struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
struct flash_sector *prot_blocks;
- int num_prot_blocks;
+ unsigned int num_prot_blocks;
int retval;
/* if it's the OTP bank, look at the lock bits there */
@@ -592,25 +582,25 @@ static int stm32x_protect_check(struct flash_bank *bank)
prot_blocks = bank->sectors;
}
- for (int i = 0; i < num_prot_blocks; i++)
+ for (unsigned int i = 0; i < num_prot_blocks; i++)
prot_blocks[i].is_protected =
~(stm32x_info->option_bytes.protection >> i) & 1;
return ERROR_OK;
}
-static int stm32x_erase(struct flash_bank *bank, int first, int last)
+static int stm32x_erase(struct flash_bank *bank, unsigned int first,
+ unsigned int last)
{
struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
struct target *target = bank->target;
- int i;
if (stm32x_is_otp(bank)) {
LOG_ERROR("Cannot erase OTP memory");
return ERROR_FAIL;
}
- assert((0 <= first) && (first <= last) && (last < bank->num_sectors));
+ assert((first <= last) && (last < bank->num_sectors));
if (bank->target->state != TARGET_HALTED) {
LOG_ERROR("Target not halted");
@@ -633,10 +623,10 @@ static int stm32x_erase(struct flash_bank *bank, int first, int last)
4. Wait for the BSY bit to be cleared
*/
- for (i = first; i <= last; i++) {
+ for (unsigned int i = first; i <= last; i++) {
unsigned int snb;
- if (stm32x_info->has_large_mem && i >= 12)
- snb = (i - 12) | 0x10;
+ if (stm32x_info->has_large_mem && i >= (bank->num_sectors / 2))
+ snb = (i - (bank->num_sectors / 2)) | 0x10;
else
snb = i;
@@ -648,8 +638,6 @@ static int stm32x_erase(struct flash_bank *bank, int first, int last)
retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
if (retval != ERROR_OK)
return retval;
-
- bank->sectors[i].is_erased = 1;
}
retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
@@ -659,7 +647,8 @@ static int stm32x_erase(struct flash_bank *bank, int first, int last)
return ERROR_OK;
}
-static int stm32x_protect(struct flash_bank *bank, int set, int first, int last)
+static int stm32x_protect(struct flash_bank *bank, int set, unsigned int first,
+ unsigned int last)
{
struct target *target = bank->target;
struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
@@ -670,8 +659,10 @@ static int stm32x_protect(struct flash_bank *bank, int set, int first, int last)
}
if (stm32x_is_otp(bank)) {
- if (!set)
+ if (!set) {
+ LOG_ERROR("OTP protection can only be enabled");
return ERROR_COMMAND_ARGUMENT_INVALID;
+ }
return stm32x_otp_protect(bank, first, last);
}
@@ -683,7 +674,7 @@ static int stm32x_protect(struct flash_bank *bank, int set, int first, int last)
return retval;
}
- for (int i = first; i <= last; i++) {
+ for (unsigned int i = first; i <= last; i++) {
if (set)
stm32x_info->option_bytes.protection &= ~(1 << i);
else
@@ -776,7 +767,7 @@ static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer,
LOG_ERROR("flash memory write protected");
if (error != 0) {
- LOG_ERROR("flash write failed = %08" PRIx32, error);
+ LOG_ERROR("flash write failed = 0x%08" PRIx32, error);
/* Clear but report errors */
target_write_u32(target, STM32_FLASH_SR, error);
retval = ERROR_FAIL;
@@ -856,15 +847,12 @@ static int stm32x_write(struct flash_bank *bank, const uint8_t *buffer,
Wait for the BSY bit to be cleared
*/
while (words_remaining > 0) {
- uint16_t value;
- memcpy(&value, buffer + bytes_written, sizeof(uint16_t));
-
retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR),
FLASH_PG | FLASH_PSIZE_16);
if (retval != ERROR_OK)
return retval;
- retval = target_write_u16(target, address, value);
+ retval = target_write_memory(target, address, 2, 1, buffer + bytes_written);
if (retval != ERROR_OK)
return retval;
@@ -894,18 +882,18 @@ static int stm32x_write(struct flash_bank *bank, const uint8_t *buffer,
return target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
}
-static void setup_sector(struct flash_bank *bank, int i, int size)
+static void setup_sector(struct flash_bank *bank, unsigned int i,
+ unsigned int size)
{
assert(i < bank->num_sectors);
bank->sectors[i].offset = bank->size;
bank->sectors[i].size = size;
bank->size += bank->sectors[i].size;
- LOG_DEBUG("sector %d: %dkBytes", i, size >> 10);
+ LOG_DEBUG("sector %u: %ukBytes", i, size >> 10);
}
-static uint16_t sector_size_in_kb(int i, uint16_t max_sector_size_in_kb)
+static uint16_t sector_size_in_kb(unsigned int i, uint16_t max_sector_size_in_kb)
{
- assert(i >= 0);
if (i < 4)
return max_sector_size_in_kb / 8;
if (i == 4)
@@ -913,13 +901,13 @@ static uint16_t sector_size_in_kb(int i, uint16_t max_sector_size_in_kb)
return max_sector_size_in_kb;
}
-static int calculate_number_of_sectors(struct flash_bank *bank,
+static unsigned int calculate_number_of_sectors(struct flash_bank *bank,
uint16_t flash_size_in_kb,
uint16_t max_sector_size_in_kb)
{
struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
uint16_t remaining_flash_size_in_kb = flash_size_in_kb;
- int nr_sectors;
+ unsigned int nr_sectors;
/* Dual Bank Flash has two identically-arranged banks of sectors. */
if (stm32x_info->has_large_mem)
@@ -940,11 +928,11 @@ static int calculate_number_of_sectors(struct flash_bank *bank,
return stm32x_info->has_large_mem ? nr_sectors*2 : nr_sectors;
}
-static void setup_bank(struct flash_bank *bank, int start,
+static void setup_bank(struct flash_bank *bank, unsigned int start,
uint16_t flash_size_in_kb, uint16_t max_sector_size_in_kb)
{
uint16_t remaining_flash_size_in_kb = flash_size_in_kb;
- int sector_index = 0;
+ unsigned int sector_index = 0;
while (remaining_flash_size_in_kb > 0) {
uint16_t size_in_kb = sector_size_in_kb(sector_index, max_sector_size_in_kb);
if (size_in_kb > remaining_flash_size_in_kb) {
@@ -966,25 +954,17 @@ static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id)
* Only effects Rev A silicon */
struct target *target = bank->target;
- uint32_t cpuid;
/* read stm32 device id register */
int retval = target_read_u32(target, 0xE0042000, device_id);
if (retval != ERROR_OK)
return retval;
- if ((*device_id & 0xfff) == 0x411) {
- /* read CPUID reg to check core type */
- retval = target_read_u32(target, 0xE000ED00, &cpuid);
- if (retval != ERROR_OK)
- return retval;
-
- /* check for cortex_m4 */
- if (((cpuid >> 4) & 0xFFF) == 0xC24) {
- *device_id &= ~((0xFFFF << 16) | 0xfff);
- *device_id |= (0x1000 << 16) | 0x413;
- LOG_INFO("stm32f4x errata detected - fixing incorrect MCU_IDCODE");
- }
+ if ((*device_id & 0xfff) == 0x411
+ && cortex_m_get_partno_safe(target) == CORTEX_M4_PARTNO) {
+ *device_id &= ~((0xFFFF << 16) | 0xfff);
+ *device_id |= (0x1000 << 16) | 0x413;
+ LOG_INFO("stm32f4x errata detected - fixing incorrect MCU_IDCODE");
}
return retval;
}
@@ -993,7 +973,7 @@ static int stm32x_probe(struct flash_bank *bank)
{
struct target *target = bank->target;
struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
- int i, num_prot_blocks, num_sectors;
+ unsigned int num_prot_blocks, num_sectors;
uint16_t flash_size_in_kb;
uint16_t otp_size_in_b;
uint16_t otp_sector_size;
@@ -1011,19 +991,20 @@ static int stm32x_probe(struct flash_bank *bank)
stm32x_info->protection_bits = 12; /* max. number of nWRPi bits (in FLASH_OPTCR !!!) */
num_prot_blocks = 0;
- if (bank->sectors) {
- free(bank->sectors);
- bank->num_sectors = 0;
- bank->sectors = NULL;
- }
+ free(bank->sectors);
+ bank->num_sectors = 0;
+ bank->sectors = NULL;
- if (bank->prot_blocks) {
- free(bank->prot_blocks);
- bank->num_prot_blocks = 0;
- bank->prot_blocks = NULL;
+ free(bank->prot_blocks);
+ bank->num_prot_blocks = 0;
+ bank->prot_blocks = NULL;
+
+ if (!target_was_examined(target)) {
+ LOG_ERROR("Target not examined yet");
+ return ERROR_TARGET_NOT_EXAMINED;
}
- /* if explicitely called out as OTP bank, short circuit probe */
+ /* if explicitly called out as OTP bank, short circuit probe */
if (stm32x_is_otp(bank)) {
if (stm32x_otp_is_f7(bank)) {
otp_size_in_b = STM32F7_OTP_SIZE;
@@ -1034,7 +1015,7 @@ static int stm32x_probe(struct flash_bank *bank)
}
num_sectors = otp_size_in_b / otp_sector_size;
- LOG_INFO("flash size = %d bytes", otp_size_in_b);
+ LOG_INFO("flash size = %" PRIu16 " bytes", otp_size_in_b);
assert(num_sectors > 0);
@@ -1046,7 +1027,7 @@ static int stm32x_probe(struct flash_bank *bank)
else
bank->size = STM32F2_OTP_SIZE;
- for (i = 0; i < num_sectors; i++) {
+ for (unsigned int i = 0; i < num_sectors; i++) {
bank->sectors[i].offset = i * otp_sector_size;
bank->sectors[i].size = otp_sector_size;
bank->sectors[i].is_erased = 1;
@@ -1061,7 +1042,7 @@ static int stm32x_probe(struct flash_bank *bank)
int retval = stm32x_get_device_id(bank, &device_id);
if (retval != ERROR_OK)
return retval;
- LOG_INFO("device id = 0x%08" PRIx32 "", device_id);
+ LOG_INFO("device id = 0x%08" PRIx32, device_id);
device_id &= 0xfff; /* only bits 0-11 are used further on */
/* set max flash size depending on family, id taken from AN2606 */
@@ -1134,7 +1115,7 @@ static int stm32x_probe(struct flash_bank *bank)
/* failed reading flash size or flash size invalid (early silicon),
* default to max target family */
if (retval != ERROR_OK || flash_size_in_kb == 0xffff || flash_size_in_kb == 0) {
- LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash",
+ LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %" PRIu16 "k flash",
max_flash_size_in_kb);
flash_size_in_kb = max_flash_size_in_kb;
}
@@ -1146,7 +1127,7 @@ static int stm32x_probe(struct flash_bank *bank)
flash_size_in_kb = stm32x_info->user_bank_size / 1024;
}
- LOG_INFO("flash size = %d kbytes", flash_size_in_kb);
+ LOG_INFO("flash size = %" PRIu16 " KiB", flash_size_in_kb);
/* did we assign flash size? */
assert(flash_size_in_kb != 0xffff);
@@ -1161,10 +1142,10 @@ static int stm32x_probe(struct flash_bank *bank)
}
if ((flash_size_in_kb > 1024) || (optiondata & OPTCR_DB1M)) {
stm32x_info->has_large_mem = true;
- LOG_INFO("Dual Bank %d kiB STM32F42x/43x/469/479 found", flash_size_in_kb);
+ LOG_INFO("Dual Bank %" PRIu16 " kiB STM32F42x/43x/469/479 found", flash_size_in_kb);
} else {
stm32x_info->has_large_mem = false;
- LOG_INFO("Single Bank %d kiB STM32F42x/43x/469/479 found", flash_size_in_kb);
+ LOG_INFO("Single Bank %" PRIu16 " kiB STM32F42x/43x/469/479 found", flash_size_in_kb);
}
}
@@ -1178,27 +1159,27 @@ static int stm32x_probe(struct flash_bank *bank)
}
if (optiondata & OPTCR_NDBANK) {
stm32x_info->has_large_mem = false;
- LOG_INFO("Single Bank %d kiB STM32F76x/77x found", flash_size_in_kb);
+ LOG_INFO("Single Bank %" PRIu16 " kiB STM32F76x/77x found", flash_size_in_kb);
} else {
stm32x_info->has_large_mem = true;
max_sector_size_in_kb >>= 1; /* sector size divided by 2 in dual-bank mode */
- LOG_INFO("Dual Bank %d kiB STM32F76x/77x found", flash_size_in_kb);
+ LOG_INFO("Dual Bank %" PRIu16 " kiB STM32F76x/77x found", flash_size_in_kb);
}
}
/* calculate numbers of pages */
- int num_pages = calculate_number_of_sectors(
+ unsigned int num_pages = calculate_number_of_sectors(
bank, flash_size_in_kb, max_sector_size_in_kb);
bank->base = base_address;
bank->num_sectors = num_pages;
bank->sectors = calloc(num_pages, sizeof(struct flash_sector));
- for (i = 0; i < num_pages; i++) {
+ for (unsigned int i = 0; i < num_pages; i++) {
bank->sectors[i].is_erased = -1;
bank->sectors[i].is_protected = 0;
}
bank->size = 0;
- LOG_DEBUG("allocated %d sectors", num_pages);
+ LOG_DEBUG("allocated %u sectors", num_pages);
/* F76x/77x in dual bank mode */
if ((device_id == 0x451) && stm32x_info->has_large_mem)
@@ -1206,9 +1187,9 @@ static int stm32x_probe(struct flash_bank *bank)
if (num_prot_blocks) {
bank->prot_blocks = malloc(sizeof(struct flash_sector) * num_prot_blocks);
- for (i = 0; i < num_prot_blocks; i++)
+ for (unsigned int i = 0; i < num_prot_blocks; i++)
bank->prot_blocks[i].is_protected = 0;
- LOG_DEBUG("allocated %d prot blocks", num_prot_blocks);
+ LOG_DEBUG("allocated %u prot blocks", num_prot_blocks);
}
if (stm32x_info->has_large_mem) {
@@ -1219,7 +1200,7 @@ static int stm32x_probe(struct flash_bank *bank)
/* F767x/F77x in dual mode, one protection bit refers to two adjacent sectors */
if (device_id == 0x451) {
- for (i = 0; i < num_prot_blocks; i++) {
+ for (unsigned int i = 0; i < num_prot_blocks; i++) {
bank->prot_blocks[i].offset = bank->sectors[i << 1].offset;
bank->prot_blocks[i].size = bank->sectors[i << 1].size
+ bank->sectors[(i << 1) + 1].size;
@@ -1231,7 +1212,7 @@ static int stm32x_probe(struct flash_bank *bank)
/* F413/F423, sectors 14 and 15 share one common protection bit */
if (device_id == 0x463) {
- for (i = 0; i < num_prot_blocks; i++) {
+ for (unsigned int i = 0; i < num_prot_blocks; i++) {
bank->prot_blocks[i].offset = bank->sectors[i].offset;
bank->prot_blocks[i].size = bank->sectors[i].size;
}
@@ -1253,7 +1234,7 @@ static int stm32x_auto_probe(struct flash_bank *bank)
return stm32x_probe(bank);
}
-static int get_stm32x_info(struct flash_bank *bank, char *buf, int buf_size)
+static int get_stm32x_info(struct flash_bank *bank, struct command_invocation *cmd)
{
uint32_t dbgmcu_idcode;
@@ -1418,14 +1399,14 @@ static int get_stm32x_info(struct flash_bank *bank, char *buf, int buf_size)
break;
default:
- snprintf(buf, buf_size, "Cannot identify target as a STM32F2/4/7\n");
+ command_print_sameline(cmd, "Cannot identify target as a STM32F2/4/7\n");
return ERROR_FAIL;
}
- if (rev_str != NULL)
- snprintf(buf, buf_size, "%s - Rev: %s", device_str, rev_str);
+ if (rev_str)
+ command_print_sameline(cmd, "%s - Rev: %s", device_str, rev_str);
else
- snprintf(buf, buf_size, "%s - Rev: unknown (0x%04x)", device_str, rev_id);
+ command_print_sameline(cmd, "%s - Rev: unknown (0x%04" PRIx16 ")", device_str, rev_id);
return ERROR_OK;
}
@@ -1440,7 +1421,7 @@ COMMAND_HANDLER(stm32x_handle_lock_command)
struct flash_bank *bank;
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
stm32x_info = bank->driver_priv;
@@ -1479,7 +1460,7 @@ COMMAND_HANDLER(stm32x_handle_unlock_command)
struct flash_bank *bank;
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
stm32x_info = bank->driver_priv;
@@ -1559,8 +1540,6 @@ static int stm32x_mass_erase(struct flash_bank *bank)
COMMAND_HANDLER(stm32x_handle_mass_erase_command)
{
- int i;
-
if (CMD_ARGC < 1) {
command_print(CMD, "stm32x mass_erase ");
return ERROR_COMMAND_SYNTAX_ERROR;
@@ -1568,15 +1547,11 @@ COMMAND_HANDLER(stm32x_handle_mass_erase_command)
struct flash_bank *bank;
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
retval = stm32x_mass_erase(bank);
if (retval == ERROR_OK) {
- /* set all sectors as erased */
- for (i = 0; i < bank->num_sectors; i++)
- bank->sectors[i].is_erased = 1;
-
command_print(CMD, "stm32x mass erase complete");
} else {
command_print(CMD, "stm32x mass erase failed");
@@ -1597,11 +1572,11 @@ COMMAND_HANDLER(stm32f2x_handle_options_read_command)
}
retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
retval = stm32x_read_options(bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
stm32x_info = bank->driver_priv;
@@ -1609,20 +1584,20 @@ COMMAND_HANDLER(stm32f2x_handle_options_read_command)
if (stm32x_info->has_boot_addr) {
uint32_t boot_addr = stm32x_info->option_bytes.boot_addr;
- command_print(CMD, "stm32f2x user_options 0x%03X,"
- " boot_add0 0x%04X, boot_add1 0x%04X",
+ command_print(CMD, "stm32f2x user_options 0x%03" PRIX16 ","
+ " boot_add0 0x%04" PRIX32 ", boot_add1 0x%04" PRIX32,
stm32x_info->option_bytes.user_options,
boot_addr & 0xffff, (boot_addr & 0xffff0000) >> 16);
if (stm32x_info->has_optcr2_pcrop) {
- command_print(CMD, "stm32f2x optcr2_pcrop 0x%08X",
+ command_print(CMD, "stm32f2x optcr2_pcrop 0x%08" PRIX32,
stm32x_info->option_bytes.optcr2_pcrop);
}
} else {
- command_print(CMD, "stm32f2x user_options 0x%03X",
+ command_print(CMD, "stm32f2x user_options 0x%03" PRIX16,
stm32x_info->option_bytes.user_options);
}
} else {
- command_print(CMD, "stm32f2x user_options 0x%02X",
+ command_print(CMD, "stm32f2x user_options 0x%02" PRIX16,
stm32x_info->option_bytes.user_options);
}
@@ -1643,11 +1618,11 @@ COMMAND_HANDLER(stm32f2x_handle_options_write_command)
}
retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
retval = stm32x_read_options(bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
stm32x_info = bank->driver_priv;
@@ -1705,7 +1680,7 @@ COMMAND_HANDLER(stm32f2x_handle_optcr2_write_command)
}
retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
stm32x_info = bank->driver_priv;
@@ -1719,7 +1694,7 @@ COMMAND_HANDLER(stm32f2x_handle_optcr2_write_command)
" finally unlock it. Clears PCROP and mass erases flash.");
retval = stm32x_read_options(bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], optcr2_pcrop);
@@ -1743,7 +1718,7 @@ COMMAND_HANDLER(stm32x_handle_otp_command)
struct flash_bank *bank;
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
if (stm32x_is_otp(bank)) {
if (strcmp(CMD_ARGV[1], "enable") == 0) {
@@ -1752,7 +1727,7 @@ COMMAND_HANDLER(stm32x_handle_otp_command)
stm32x_otp_disable(bank);
} else if (strcmp(CMD_ARGV[1], "show") == 0) {
command_print(CMD,
- "OTP memory bank #%d is %s for write commands.",
+ "OTP memory bank #%u is %s for write commands.",
bank->bank_number,
stm32x_is_otp_unlocked(bank) ? "enabled" : "disabled");
} else {
@@ -1765,7 +1740,7 @@ COMMAND_HANDLER(stm32x_handle_otp_command)
return retval;
}
-static const struct command_registration stm32x_exec_command_handlers[] = {
+static const struct command_registration stm32f2x_exec_command_handlers[] = {
{
.name = "lock",
.handler = stm32x_handle_lock_command,
@@ -1818,20 +1793,20 @@ static const struct command_registration stm32x_exec_command_handlers[] = {
COMMAND_REGISTRATION_DONE
};
-static const struct command_registration stm32x_command_handlers[] = {
+static const struct command_registration stm32f2x_command_handlers[] = {
{
.name = "stm32f2x",
.mode = COMMAND_ANY,
.help = "stm32f2x flash command group",
.usage = "",
- .chain = stm32x_exec_command_handlers,
+ .chain = stm32f2x_exec_command_handlers,
},
COMMAND_REGISTRATION_DONE
};
const struct flash_driver stm32f2x_flash = {
.name = "stm32f2x",
- .commands = stm32x_command_handlers,
+ .commands = stm32f2x_command_handlers,
.flash_bank_command = stm32x_flash_bank_command,
.erase = stm32x_erase,
.protect = stm32x_protect,