X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Fflash%2Fnor%2Fstm32l4x.c;h=5bc23090fbc6806e5a32e93405a1336b97d3b5ad;hb=1247eee4e6e55889b14bec8d81c4748767bb67b8;hp=89c5ac3fe28aca757a9ca5135c764f4854257ed1;hpb=8d6f7c92239a54ce77d7a268f51b49445470fe00;p=openocd.git diff --git a/src/flash/nor/stm32l4x.c b/src/flash/nor/stm32l4x.c index 89c5ac3fe2..5bc23090fb 100644 --- a/src/flash/nor/stm32l4x.c +++ b/src/flash/nor/stm32l4x.c @@ -24,6 +24,7 @@ #endif #include "imp.h" +#include #include #include #include @@ -115,6 +116,22 @@ /* Erase time can be as high as 25ms, 10x this and assume it's toast... */ #define FLASH_ERASE_TIMEOUT 250 +#define FLASH_WRITE_TIMEOUT 50 + + +/* relevant STM32L4 flags ****************************************************/ +#define F_NONE 0 +/* this flag indicates if the device flash is with dual bank architecture */ +#define F_HAS_DUAL_BANK BIT(0) +/* this flags is used for dual bank devices only, it indicates if the + * 4 WRPxx are usable if the device is configured in single-bank mode */ +#define F_USE_ALL_WRPXX BIT(1) +/* this flag indicates if the device embeds a TrustZone security feature */ +#define F_HAS_TZ BIT(2) +/* this flag indicates if the device has the same flash registers as STM32L5 */ +#define F_HAS_L5_FLASH_REGS BIT(3) +/* end of STM32L4 flags ******************************************************/ + enum stm32l4_flash_reg_index { STM32_FLASH_ACR_INDEX, @@ -130,6 +147,13 @@ enum stm32l4_flash_reg_index { STM32_FLASH_REG_INDEX_NUM, }; +enum stm32l4_rdp { + RDP_LEVEL_0 = 0xAA, + RDP_LEVEL_0_5 = 0x55, /* for devices with TrustZone enabled */ + RDP_LEVEL_1 = 0x00, + RDP_LEVEL_2 = 0xCC +}; + static const uint32_t stm32l4_flash_regs[STM32_FLASH_REG_INDEX_NUM] = { [STM32_FLASH_ACR_INDEX] = 0x000, [STM32_FLASH_KEYR_INDEX] = 0x008, @@ -145,10 +169,23 @@ static const uint32_t stm32l4_flash_regs[STM32_FLASH_REG_INDEX_NUM] = { static const uint32_t stm32l5_ns_flash_regs[STM32_FLASH_REG_INDEX_NUM] = { [STM32_FLASH_ACR_INDEX] = 0x000, - [STM32_FLASH_KEYR_INDEX] = 0x008, + [STM32_FLASH_KEYR_INDEX] = 0x008, /* NSKEYR */ + [STM32_FLASH_OPTKEYR_INDEX] = 0x010, + [STM32_FLASH_SR_INDEX] = 0x020, /* NSSR */ + [STM32_FLASH_CR_INDEX] = 0x028, /* NSCR */ + [STM32_FLASH_OPTR_INDEX] = 0x040, + [STM32_FLASH_WRP1AR_INDEX] = 0x058, + [STM32_FLASH_WRP1BR_INDEX] = 0x05C, + [STM32_FLASH_WRP2AR_INDEX] = 0x068, + [STM32_FLASH_WRP2BR_INDEX] = 0x06C, +}; + +static const uint32_t stm32l5_s_flash_regs[STM32_FLASH_REG_INDEX_NUM] = { + [STM32_FLASH_ACR_INDEX] = 0x000, + [STM32_FLASH_KEYR_INDEX] = 0x00C, /* SECKEYR */ [STM32_FLASH_OPTKEYR_INDEX] = 0x010, - [STM32_FLASH_SR_INDEX] = 0x020, - [STM32_FLASH_CR_INDEX] = 0x028, + [STM32_FLASH_SR_INDEX] = 0x024, /* SECSR */ + [STM32_FLASH_CR_INDEX] = 0x02C, /* SECCR */ [STM32_FLASH_OPTR_INDEX] = 0x040, [STM32_FLASH_WRP1AR_INDEX] = 0x058, [STM32_FLASH_WRP1BR_INDEX] = 0x05C, @@ -167,10 +204,12 @@ struct stm32l4_part_info { const struct stm32l4_rev *revs; const size_t num_revs; const uint16_t max_flash_size_kb; - const bool has_dual_bank; + const uint32_t flags; /* one bit per feature, see STM32L4 flags: macros F_XXX */ const uint32_t flash_regs_base; const uint32_t *default_flash_regs; const uint32_t fsize_addr; + const uint32_t otp_base; + const uint32_t otp_size; }; struct stm32l4_flash_bank { @@ -182,7 +221,28 @@ struct stm32l4_flash_bank { uint32_t user_bank_size; uint32_t wrpxxr_mask; const struct stm32l4_part_info *part_info; + uint32_t flash_regs_base; const uint32_t *flash_regs; + bool otp_enabled; + bool use_flashloader; + enum stm32l4_rdp rdp; + bool tzen; + uint32_t optr; +}; + +enum stm32_bank_id { + STM32_BANK1, + STM32_BANK2, + STM32_ALL_BANKS +}; + +struct stm32l4_wrp { + enum stm32l4_flash_reg_index reg_idx; + uint32_t value; + bool used; + int first; + int last; + int offset; }; /* human readable list of families this drivers supports (sorted alphabetically) */ @@ -259,10 +319,12 @@ static const struct stm32l4_part_info stm32l4_parts[] = { .num_revs = ARRAY_SIZE(stm32_415_revs), .device_str = "STM32L47/L48xx", .max_flash_size_kb = 1024, - .has_dual_bank = true, + .flags = F_HAS_DUAL_BANK, .flash_regs_base = 0x40022000, .default_flash_regs = stm32l4_flash_regs, .fsize_addr = 0x1FFF75E0, + .otp_base = 0x1FFF7000, + .otp_size = 1024, }, { .id = 0x435, @@ -270,10 +332,12 @@ static const struct stm32l4_part_info stm32l4_parts[] = { .num_revs = ARRAY_SIZE(stm32_435_revs), .device_str = "STM32L43/L44xx", .max_flash_size_kb = 256, - .has_dual_bank = false, + .flags = F_NONE, .flash_regs_base = 0x40022000, .default_flash_regs = stm32l4_flash_regs, .fsize_addr = 0x1FFF75E0, + .otp_base = 0x1FFF7000, + .otp_size = 1024, }, { .id = 0x460, @@ -281,10 +345,12 @@ static const struct stm32l4_part_info stm32l4_parts[] = { .num_revs = ARRAY_SIZE(stm32_460_revs), .device_str = "STM32G07/G08xx", .max_flash_size_kb = 128, - .has_dual_bank = false, + .flags = F_NONE, .flash_regs_base = 0x40022000, .default_flash_regs = stm32l4_flash_regs, .fsize_addr = 0x1FFF75E0, + .otp_base = 0x1FFF7000, + .otp_size = 1024, }, { .id = 0x461, @@ -292,10 +358,12 @@ static const struct stm32l4_part_info stm32l4_parts[] = { .num_revs = ARRAY_SIZE(stm32_461_revs), .device_str = "STM32L49/L4Axx", .max_flash_size_kb = 1024, - .has_dual_bank = true, + .flags = F_HAS_DUAL_BANK, .flash_regs_base = 0x40022000, .default_flash_regs = stm32l4_flash_regs, .fsize_addr = 0x1FFF75E0, + .otp_base = 0x1FFF7000, + .otp_size = 1024, }, { .id = 0x462, @@ -303,10 +371,12 @@ static const struct stm32l4_part_info stm32l4_parts[] = { .num_revs = ARRAY_SIZE(stm32_462_revs), .device_str = "STM32L45/L46xx", .max_flash_size_kb = 512, - .has_dual_bank = false, + .flags = F_NONE, .flash_regs_base = 0x40022000, .default_flash_regs = stm32l4_flash_regs, .fsize_addr = 0x1FFF75E0, + .otp_base = 0x1FFF7000, + .otp_size = 1024, }, { .id = 0x464, @@ -314,10 +384,12 @@ static const struct stm32l4_part_info stm32l4_parts[] = { .num_revs = ARRAY_SIZE(stm32_464_revs), .device_str = "STM32L41/L42xx", .max_flash_size_kb = 128, - .has_dual_bank = false, + .flags = F_NONE, .flash_regs_base = 0x40022000, .default_flash_regs = stm32l4_flash_regs, .fsize_addr = 0x1FFF75E0, + .otp_base = 0x1FFF7000, + .otp_size = 1024, }, { .id = 0x466, @@ -325,10 +397,12 @@ static const struct stm32l4_part_info stm32l4_parts[] = { .num_revs = ARRAY_SIZE(stm32_466_revs), .device_str = "STM32G03/G04xx", .max_flash_size_kb = 64, - .has_dual_bank = false, + .flags = F_NONE, .flash_regs_base = 0x40022000, .default_flash_regs = stm32l4_flash_regs, .fsize_addr = 0x1FFF75E0, + .otp_base = 0x1FFF7000, + .otp_size = 1024, }, { .id = 0x468, @@ -336,10 +410,12 @@ static const struct stm32l4_part_info stm32l4_parts[] = { .num_revs = ARRAY_SIZE(stm32_468_revs), .device_str = "STM32G43/G44xx", .max_flash_size_kb = 128, - .has_dual_bank = false, + .flags = F_NONE, .flash_regs_base = 0x40022000, .default_flash_regs = stm32l4_flash_regs, .fsize_addr = 0x1FFF75E0, + .otp_base = 0x1FFF7000, + .otp_size = 1024, }, { .id = 0x469, @@ -347,10 +423,12 @@ static const struct stm32l4_part_info stm32l4_parts[] = { .num_revs = ARRAY_SIZE(stm32_469_revs), .device_str = "STM32G47/G48xx", .max_flash_size_kb = 512, - .has_dual_bank = true, + .flags = F_HAS_DUAL_BANK | F_USE_ALL_WRPXX, .flash_regs_base = 0x40022000, .default_flash_regs = stm32l4_flash_regs, .fsize_addr = 0x1FFF75E0, + .otp_base = 0x1FFF7000, + .otp_size = 1024, }, { .id = 0x470, @@ -358,10 +436,12 @@ static const struct stm32l4_part_info stm32l4_parts[] = { .num_revs = ARRAY_SIZE(stm32_470_revs), .device_str = "STM32L4R/L4Sxx", .max_flash_size_kb = 2048, - .has_dual_bank = true, + .flags = F_HAS_DUAL_BANK | F_USE_ALL_WRPXX, .flash_regs_base = 0x40022000, .default_flash_regs = stm32l4_flash_regs, .fsize_addr = 0x1FFF75E0, + .otp_base = 0x1FFF7000, + .otp_size = 1024, }, { .id = 0x471, @@ -369,10 +449,12 @@ static const struct stm32l4_part_info stm32l4_parts[] = { .num_revs = ARRAY_SIZE(stm32_471_revs), .device_str = "STM32L4P5/L4Q5x", .max_flash_size_kb = 1024, - .has_dual_bank = true, + .flags = F_HAS_DUAL_BANK | F_USE_ALL_WRPXX, .flash_regs_base = 0x40022000, .default_flash_regs = stm32l4_flash_regs, .fsize_addr = 0x1FFF75E0, + .otp_base = 0x1FFF7000, + .otp_size = 1024, }, { .id = 0x472, @@ -380,10 +462,12 @@ static const struct stm32l4_part_info stm32l4_parts[] = { .num_revs = ARRAY_SIZE(stm32_472_revs), .device_str = "STM32L55/L56xx", .max_flash_size_kb = 512, - .has_dual_bank = true, + .flags = F_HAS_DUAL_BANK | F_USE_ALL_WRPXX | F_HAS_TZ | F_HAS_L5_FLASH_REGS, .flash_regs_base = 0x40022000, .default_flash_regs = stm32l5_ns_flash_regs, .fsize_addr = 0x0BFA05E0, + .otp_base = 0x0BFA0000, + .otp_size = 512, }, { .id = 0x479, @@ -391,10 +475,12 @@ static const struct stm32l4_part_info stm32l4_parts[] = { .num_revs = ARRAY_SIZE(stm32_479_revs), .device_str = "STM32G49/G4Axx", .max_flash_size_kb = 512, - .has_dual_bank = false, + .flags = F_NONE, .flash_regs_base = 0x40022000, .default_flash_regs = stm32l4_flash_regs, .fsize_addr = 0x1FFF75E0, + .otp_base = 0x1FFF7000, + .otp_size = 1024, }, { .id = 0x495, @@ -402,10 +488,12 @@ static const struct stm32l4_part_info stm32l4_parts[] = { .num_revs = ARRAY_SIZE(stm32_495_revs), .device_str = "STM32WB5x", .max_flash_size_kb = 1024, - .has_dual_bank = false, + .flags = F_NONE, .flash_regs_base = 0x58004000, .default_flash_regs = stm32l4_flash_regs, .fsize_addr = 0x1FFF75E0, + .otp_base = 0x1FFF7000, + .otp_size = 1024, }, { .id = 0x496, @@ -413,10 +501,12 @@ static const struct stm32l4_part_info stm32l4_parts[] = { .num_revs = ARRAY_SIZE(stm32_496_revs), .device_str = "STM32WB3x", .max_flash_size_kb = 512, - .has_dual_bank = false, + .flags = F_NONE, .flash_regs_base = 0x58004000, .default_flash_regs = stm32l4_flash_regs, .fsize_addr = 0x1FFF75E0, + .otp_base = 0x1FFF7000, + .otp_size = 1024, }, { .id = 0x497, @@ -424,10 +514,12 @@ static const struct stm32l4_part_info stm32l4_parts[] = { .num_revs = ARRAY_SIZE(stm32_497_revs), .device_str = "STM32WLEx", .max_flash_size_kb = 256, - .has_dual_bank = false, + .flags = F_NONE, .flash_regs_base = 0x58004000, .default_flash_regs = stm32l4_flash_regs, .fsize_addr = 0x1FFF75E0, + .otp_base = 0x1FFF7000, + .otp_size = 1024, }, }; @@ -439,6 +531,10 @@ FLASH_BANK_COMMAND_HANDLER(stm32l4_flash_bank_command) if (CMD_ARGC < 6) return ERROR_COMMAND_SYNTAX_ERROR; + /* fix-up bank base address: 0 is used for normal flash memory */ + if (bank->base == 0) + bank->base = STM32_FLASH_BANK_BASE; + stm32l4_info = calloc(1, sizeof(struct stm32l4_flash_bank)); if (!stm32l4_info) return ERROR_FAIL; /* Checkme: What better error to use?*/ @@ -449,15 +545,134 @@ FLASH_BANK_COMMAND_HANDLER(stm32l4_flash_bank_command) bank->write_start_alignment = bank->write_end_alignment = 8; stm32l4_info->probed = false; + stm32l4_info->otp_enabled = false; stm32l4_info->user_bank_size = bank->size; + stm32l4_info->use_flashloader = true; return ERROR_OK; } +/* bitmap helper extension */ +struct range { + unsigned int start; + unsigned int end; +}; + +static void bitmap_to_ranges(unsigned long *bitmap, unsigned int nbits, + struct range *ranges, unsigned int *ranges_count) { + *ranges_count = 0; + bool last_bit = 0, cur_bit; + for (unsigned int i = 0; i < nbits; i++) { + cur_bit = test_bit(i, bitmap); + + if (cur_bit && !last_bit) { + (*ranges_count)++; + ranges[*ranges_count - 1].start = i; + ranges[*ranges_count - 1].end = i; + } else if (cur_bit && last_bit) { + /* update (increment) the end this range */ + ranges[*ranges_count - 1].end = i; + } + + last_bit = cur_bit; + } +} + +static inline int range_print_one(struct range *range, char *str) +{ + if (range->start == range->end) + return sprintf(str, "[%d]", range->start); + + return sprintf(str, "[%d,%d]", range->start, range->end); +} + +static char *range_print_alloc(struct range *ranges, unsigned int ranges_count) +{ + /* each range will be printed like the following: [start,end] + * start and end, both are unsigned int, an unsigned int takes 10 characters max + * plus 3 characters for '[', ',' and ']' + * thus means each range can take maximum 23 character + * after each range we add a ' ' as separator and finally we need the '\0' + * if the ranges_count is zero we reserve one char for '\0' to return an empty string */ + char *str = calloc(1, ranges_count * (24 * sizeof(char)) + 1); + char *ptr = str; + + for (unsigned int i = 0; i < ranges_count; i++) { + ptr += range_print_one(&(ranges[i]), ptr); + + if (i < ranges_count - 1) + *(ptr++) = ' '; + } + + return str; +} + +/* end of bitmap helper extension */ + +static inline bool stm32l4_is_otp(struct flash_bank *bank) +{ + struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv; + return bank->base == stm32l4_info->part_info->otp_base; +} + +static int stm32l4_otp_enable(struct flash_bank *bank, bool enable) +{ + struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv; + + if (!stm32l4_is_otp(bank)) + return ERROR_FAIL; + + char *op_str = enable ? "enabled" : "disabled"; + + LOG_INFO("OTP memory (bank #%d) is %s%s for write commands", + bank->bank_number, + stm32l4_info->otp_enabled == enable ? "already " : "", + op_str); + + stm32l4_info->otp_enabled = enable; + + return ERROR_OK; +} + +static inline bool stm32l4_otp_is_enabled(struct flash_bank *bank) +{ + struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv; + return stm32l4_info->otp_enabled; +} + +static void stm32l4_sync_rdp_tzen(struct flash_bank *bank) +{ + struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv; + + bool tzen = false; + + if (stm32l4_info->part_info->flags & F_HAS_TZ) + tzen = (stm32l4_info->optr & FLASH_TZEN) != 0; + + uint32_t rdp = stm32l4_info->optr & FLASH_RDP_MASK; + + /* for devices without TrustZone: + * RDP level 0 and 2 values are to 0xAA and 0xCC + * Any other value corresponds to RDP level 1 + * for devices with TrusZone: + * RDP level 0 and 2 values are 0xAA and 0xCC + * RDP level 0.5 value is 0x55 only if TZEN = 1 + * Any other value corresponds to RDP level 1, including 0x55 if TZEN = 0 + */ + + if (rdp != RDP_LEVEL_0 && rdp != RDP_LEVEL_2) { + if (!tzen || (tzen && rdp != RDP_LEVEL_0_5)) + rdp = RDP_LEVEL_1; + } + + stm32l4_info->tzen = tzen; + stm32l4_info->rdp = rdp; +} + static inline uint32_t stm32l4_get_flash_reg(struct flash_bank *bank, uint32_t reg_offset) { struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv; - return stm32l4_info->part_info->flash_regs_base + reg_offset; + return stm32l4_info->flash_regs_base + reg_offset; } static inline uint32_t stm32l4_get_flash_reg_by_index(struct flash_bank *bank, @@ -529,6 +744,49 @@ static int stm32l4_wait_status_busy(struct flash_bank *bank, int timeout) return retval; } +/** set all FLASH_SECBB registers to the same value */ +static int stm32l4_set_secbb(struct flash_bank *bank, uint32_t value) +{ + /* This function should be used only with device with TrustZone, do just a security check */ + struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv; + assert(stm32l4_info->part_info->flags & F_HAS_TZ); + + /* based on RM0438 Rev6 for STM32L5x devices: + * to modify a page block-based security attribution, it is recommended to + * 1- check that no flash operation is ongoing on the related page + * 2- add ISB instruction after modifying the page security attribute in SECBBxRy + * this step is not need in case of JTAG direct access + */ + int retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT); + if (retval != ERROR_OK) + return retval; + + /* write SECBBxRy registers */ + LOG_DEBUG("setting secure block-based areas registers (SECBBxRy) to 0x%08x", value); + + const uint8_t secbb_regs[] = { + FLASH_SECBB1(1), FLASH_SECBB1(2), FLASH_SECBB1(3), FLASH_SECBB1(4), /* bank 1 SECBB register offsets */ + FLASH_SECBB2(1), FLASH_SECBB2(2), FLASH_SECBB2(3), FLASH_SECBB2(4) /* bank 2 SECBB register offsets */ + }; + + + unsigned int num_secbb_regs = ARRAY_SIZE(secbb_regs); + + /* in single bank mode, it's useless to modify FLASH_SECBB2Rx registers + * then consider only the first half of secbb_regs + */ + if (!stm32l4_info->dual_bank_mode) + num_secbb_regs /= 2; + + for (unsigned int i = 0; i < num_secbb_regs; i++) { + retval = stm32l4_write_flash_reg(bank, secbb_regs[i], value); + if (retval != ERROR_OK) + return retval; + } + + return ERROR_OK; +} + static int stm32l4_unlock_reg(struct flash_bank *bank) { uint32_t ctrl; @@ -596,9 +854,46 @@ static int stm32l4_unlock_option_reg(struct flash_bank *bank) return ERROR_OK; } +static int stm32l4_perform_obl_launch(struct flash_bank *bank) +{ + int retval, retval2; + + retval = stm32l4_unlock_reg(bank); + if (retval != ERROR_OK) + goto err_lock; + + retval = stm32l4_unlock_option_reg(bank); + if (retval != ERROR_OK) + goto err_lock; + + /* Set OBL_LAUNCH bit in CR -> system reset and option bytes reload, + * but the RMs explicitly do *NOT* list this as power-on reset cause, and: + * "Note: If the read protection is set while the debugger is still + * connected through JTAG/SWD, apply a POR (power-on reset) instead of a system reset." + */ + + /* "Setting OBL_LAUNCH generates a reset so the option byte loading is performed under system reset" */ + /* Due to this reset ST-Link reports an SWD_DP_ERROR, despite the write was successful, + * then just ignore the returned value */ + stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, FLASH_OBL_LAUNCH); + + /* Need to re-probe after change */ + struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv; + stm32l4_info->probed = false; + +err_lock: + retval2 = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, FLASH_LOCK | FLASH_OPTLOCK); + + if (retval != ERROR_OK) + return retval; + + return retval2; +} + static int stm32l4_write_option(struct flash_bank *bank, uint32_t reg_offset, uint32_t value, uint32_t mask) { + struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv; uint32_t optiondata; int retval, retval2; @@ -606,6 +901,12 @@ static int stm32l4_write_option(struct flash_bank *bank, uint32_t reg_offset, if (retval != ERROR_OK) return retval; + /* for STM32L5 and similar devices, use always non-secure + * registers for option bytes programming */ + const uint32_t *saved_flash_regs = stm32l4_info->flash_regs; + if (stm32l4_info->part_info->flags & F_HAS_L5_FLASH_REGS) + stm32l4_info->flash_regs = stm32l5_ns_flash_regs; + retval = stm32l4_unlock_reg(bank); if (retval != ERROR_OK) goto err_lock; @@ -628,6 +929,7 @@ static int stm32l4_write_option(struct flash_bank *bank, uint32_t reg_offset, err_lock: retval2 = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, FLASH_LOCK | FLASH_OPTLOCK); + stm32l4_info->flash_regs = saved_flash_regs; if (retval != ERROR_OK) return retval; @@ -635,53 +937,125 @@ err_lock: return retval2; } -static int stm32l4_protect_check(struct flash_bank *bank) +static int stm32l4_get_one_wrpxy(struct flash_bank *bank, struct stm32l4_wrp *wrpxy, + enum stm32l4_flash_reg_index reg_idx, int offset) { struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv; + int ret; - uint32_t wrp1ar, wrp1br, wrp2ar, wrp2br; - stm32l4_read_flash_reg_by_index(bank, STM32_FLASH_WRP1AR_INDEX, &wrp1ar); - stm32l4_read_flash_reg_by_index(bank, STM32_FLASH_WRP1BR_INDEX, &wrp1br); - if (stm32l4_info->part_info->has_dual_bank) { - stm32l4_read_flash_reg_by_index(bank, STM32_FLASH_WRP2AR_INDEX, &wrp2ar); - stm32l4_read_flash_reg_by_index(bank, STM32_FLASH_WRP2BR_INDEX, &wrp2br); - } else { - /* prevent uninitialized errors */ - wrp2ar = 0; - wrp2br = 0; + wrpxy->reg_idx = reg_idx; + wrpxy->offset = offset; + + ret = stm32l4_read_flash_reg_by_index(bank, wrpxy->reg_idx , &wrpxy->value); + if (ret != ERROR_OK) + return ret; + + wrpxy->first = (wrpxy->value & stm32l4_info->wrpxxr_mask) + wrpxy->offset; + wrpxy->last = ((wrpxy->value >> 16) & stm32l4_info->wrpxxr_mask) + wrpxy->offset; + wrpxy->used = wrpxy->first <= wrpxy->last; + + return ERROR_OK; +} + +static int stm32l4_get_all_wrpxy(struct flash_bank *bank, enum stm32_bank_id dev_bank_id, + struct stm32l4_wrp *wrpxy, unsigned int *n_wrp) +{ + struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv; + int ret; + + *n_wrp = 0; + + /* for single bank devices there is 2 WRP regions. + * for dual bank devices there is 2 WRP regions per bank, + * if configured as single bank only 2 WRP are usable + * except for STM32L4R/S/P/Q, G4 cat3, L5 ... all 4 WRP are usable + * note: this should be revised, if a device will have the SWAP banks option + */ + + int wrp2y_sectors_offset = -1; /* -1 : unused */ + + /* if bank_id is BANK1 or ALL_BANKS */ + if (dev_bank_id != STM32_BANK2) { + /* get FLASH_WRP1AR */ + ret = stm32l4_get_one_wrpxy(bank, &wrpxy[(*n_wrp)++], STM32_FLASH_WRP1AR_INDEX, 0); + if (ret != ERROR_OK) + return ret; + + /* get WRP1BR */ + ret = stm32l4_get_one_wrpxy(bank, &wrpxy[(*n_wrp)++], STM32_FLASH_WRP1BR_INDEX, 0); + if (ret != ERROR_OK) + return ret; + + /* for some devices (like STM32L4R/S) in single-bank mode, the 4 WRPxx are usable */ + if ((stm32l4_info->part_info->flags & F_USE_ALL_WRPXX) && !stm32l4_info->dual_bank_mode) + wrp2y_sectors_offset = 0; } - const uint8_t wrp1a_start = wrp1ar & stm32l4_info->wrpxxr_mask; - const uint8_t wrp1a_end = (wrp1ar >> 16) & stm32l4_info->wrpxxr_mask; - const uint8_t wrp1b_start = wrp1br & stm32l4_info->wrpxxr_mask; - const uint8_t wrp1b_end = (wrp1br >> 16) & stm32l4_info->wrpxxr_mask; - const uint8_t wrp2a_start = wrp2ar & stm32l4_info->wrpxxr_mask; - const uint8_t wrp2a_end = (wrp2ar >> 16) & stm32l4_info->wrpxxr_mask; - const uint8_t wrp2b_start = wrp2br & stm32l4_info->wrpxxr_mask; - const uint8_t wrp2b_end = (wrp2br >> 16) & stm32l4_info->wrpxxr_mask; + /* if bank_id is BANK2 or ALL_BANKS */ + if (dev_bank_id != STM32_BANK1 && stm32l4_info->dual_bank_mode) + wrp2y_sectors_offset = stm32l4_info->bank1_sectors; - for (unsigned int i = 0; i < bank->num_sectors; i++) { - if (i < stm32l4_info->bank1_sectors) { - if (((i >= wrp1a_start) && - (i <= wrp1a_end)) || - ((i >= wrp1b_start) && - (i <= wrp1b_end))) - bank->sectors[i].is_protected = 1; - else - bank->sectors[i].is_protected = 0; - } else { - assert(stm32l4_info->part_info->has_dual_bank == true); - uint8_t snb; - snb = i - stm32l4_info->bank1_sectors; - if (((snb >= wrp2a_start) && - (snb <= wrp2a_end)) || - ((snb >= wrp2b_start) && - (snb <= wrp2b_end))) - bank->sectors[i].is_protected = 1; - else - bank->sectors[i].is_protected = 0; + if (wrp2y_sectors_offset > -1) { + /* get WRP2AR */ + ret = stm32l4_get_one_wrpxy(bank, &wrpxy[(*n_wrp)++], STM32_FLASH_WRP2AR_INDEX, wrp2y_sectors_offset); + if (ret != ERROR_OK) + return ret; + + /* get WRP2BR */ + ret = stm32l4_get_one_wrpxy(bank, &wrpxy[(*n_wrp)++], STM32_FLASH_WRP2BR_INDEX, wrp2y_sectors_offset); + if (ret != ERROR_OK) + return ret; + } + + return ERROR_OK; +} + +static int stm32l4_write_one_wrpxy(struct flash_bank *bank, struct stm32l4_wrp *wrpxy) +{ + struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv; + + int wrp_start = wrpxy->first - wrpxy->offset; + int wrp_end = wrpxy->last - wrpxy->offset; + + uint32_t wrp_value = (wrp_start & stm32l4_info->wrpxxr_mask) | ((wrp_end & stm32l4_info->wrpxxr_mask) << 16); + + return stm32l4_write_option(bank, stm32l4_info->flash_regs[wrpxy->reg_idx], wrp_value, 0xffffffff); +} + +static int stm32l4_write_all_wrpxy(struct flash_bank *bank, struct stm32l4_wrp *wrpxy, unsigned int n_wrp) +{ + int ret; + + for (unsigned int i = 0; i < n_wrp; i++) { + ret = stm32l4_write_one_wrpxy(bank, &wrpxy[i]); + if (ret != ERROR_OK) + return ret; + } + + return ERROR_OK; +} + +static int stm32l4_protect_check(struct flash_bank *bank) +{ + unsigned int n_wrp; + struct stm32l4_wrp wrpxy[4]; + + int ret = stm32l4_get_all_wrpxy(bank, STM32_ALL_BANKS, wrpxy, &n_wrp); + if (ret != ERROR_OK) + return ret; + + /* initialize all sectors as unprotected */ + for (unsigned int i = 0; i < bank->num_sectors; i++) + bank->sectors[i].is_protected = 0; + + /* now check WRPxy and mark the protected sectors */ + for (unsigned int i = 0; i < n_wrp; i++) { + if (wrpxy[i].used) { + for (int s = wrpxy[i].first; s <= wrpxy[i].last; s++) + bank->sectors[s].is_protected = 1; } } + return ERROR_OK; } @@ -693,11 +1067,26 @@ static int stm32l4_erase(struct flash_bank *bank, unsigned int first, assert((first <= last) && (last < bank->num_sectors)); + if (stm32l4_is_otp(bank)) { + LOG_ERROR("cannot erase OTP memory"); + return ERROR_FLASH_OPER_UNSUPPORTED; + } + if (bank->target->state != TARGET_HALTED) { LOG_ERROR("Target not halted"); return ERROR_TARGET_NOT_HALTED; } + if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0)) { + /* set all FLASH pages as secure */ + retval = stm32l4_set_secbb(bank, FLASH_SECBB_SECURE); + if (retval != ERROR_OK) { + /* restore all FLASH pages as non-secure */ + stm32l4_set_secbb(bank, FLASH_SECBB_NON_SECURE); /* ignore the return value */ + return retval; + } + } + retval = stm32l4_unlock_reg(bank); if (retval != ERROR_OK) goto err_lock; @@ -730,53 +1119,151 @@ static int stm32l4_erase(struct flash_bank *bank, unsigned int first, retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT); if (retval != ERROR_OK) break; - - bank->sectors[i].is_erased = 1; } err_lock: retval2 = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, FLASH_LOCK); + if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0)) { + /* restore all FLASH pages as non-secure */ + int retval3 = stm32l4_set_secbb(bank, FLASH_SECBB_NON_SECURE); + if (retval3 != ERROR_OK) + return retval3; + } + if (retval != ERROR_OK) return retval; return retval2; } -static int stm32l4_protect(struct flash_bank *bank, int set, unsigned int first, - unsigned int last) +static int stm32l4_protect(struct flash_bank *bank, int set, unsigned int first, unsigned int last) { struct target *target = bank->target; struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv; + int ret = ERROR_OK; + unsigned int i; + + if (stm32l4_is_otp(bank)) { + LOG_ERROR("cannot protect/unprotect OTP memory"); + return ERROR_FLASH_OPER_UNSUPPORTED; + } if (target->state != TARGET_HALTED) { LOG_ERROR("Target not halted"); return ERROR_TARGET_NOT_HALTED; } - int ret = ERROR_OK; - /* Bank 2 */ - uint32_t reg_value = 0xFF; /* Default to bank un-protected */ + /* the requested sectors could be located into bank1 and/or bank2 */ + bool use_bank2 = false; if (last >= stm32l4_info->bank1_sectors) { - if (set == 1) { - uint8_t begin = first > stm32l4_info->bank1_sectors ? first : 0x00; - reg_value = ((last & 0xFF) << 16) | begin; + if (first < stm32l4_info->bank1_sectors) { + /* the requested sectors for (un)protection are shared between + * bank 1 and 2, then split the operation */ + + /* 1- deal with bank 1 sectors */ + LOG_DEBUG("The requested sectors for %s are shared between bank 1 and 2", + set ? "protection" : "unprotection"); + ret = stm32l4_protect(bank, set, first, stm32l4_info->bank1_sectors - 1); + if (ret != ERROR_OK) + return ret; + + /* 2- then continue with bank 2 sectors */ + first = stm32l4_info->bank1_sectors; } - ret = stm32l4_write_option(bank, stm32l4_info->flash_regs[STM32_FLASH_WRP2AR_INDEX], reg_value, 0xffffffff); + use_bank2 = true; } - /* Bank 1 */ - reg_value = 0xFF; /* Default to bank un-protected */ - if (first < stm32l4_info->bank1_sectors) { - if (set == 1) { - uint8_t end = last >= stm32l4_info->bank1_sectors ? 0xFF : last; - reg_value = (end << 16) | (first & 0xFF); + + /* refresh the sectors' protection */ + ret = stm32l4_protect_check(bank); + if (ret != ERROR_OK) + return ret; + + /* check if the desired protection is already configured */ + for (i = first; i <= last; i++) { + if (bank->sectors[i].is_protected != set) + break; + else if (i == last) { + LOG_INFO("The specified sectors are already %s", set ? "protected" : "unprotected"); + return ERROR_OK; } + } + + /* all sectors from first to last (or part of them) could have different + * protection other than the requested */ + unsigned int n_wrp; + struct stm32l4_wrp wrpxy[4]; + + ret = stm32l4_get_all_wrpxy(bank, use_bank2 ? STM32_BANK2 : STM32_BANK1, wrpxy, &n_wrp); + if (ret != ERROR_OK) + return ret; + + /* use bitmap and range helpers to optimize the WRP usage */ + DECLARE_BITMAP(pages, bank->num_sectors); + bitmap_zero(pages, bank->num_sectors); + + for (i = 0; i < n_wrp; i++) { + if (wrpxy[i].used) { + for (int p = wrpxy[i].first; p <= wrpxy[i].last; p++) + set_bit(p, pages); + } + } + + /* we have at most 'n_wrp' WRP areas + * add one range if the user is trying to protect a fifth range */ + struct range ranges[n_wrp + 1]; + unsigned int ranges_count = 0; + + bitmap_to_ranges(pages, bank->num_sectors, ranges, &ranges_count); + + /* pretty-print the currently protected ranges */ + if (ranges_count > 0) { + char *ranges_str = range_print_alloc(ranges, ranges_count); + LOG_DEBUG("current protected areas: %s", ranges_str); + free(ranges_str); + } else + LOG_DEBUG("current protected areas: none"); + + if (set) { /* flash protect */ + for (i = first; i <= last; i++) + set_bit(i, pages); + } else { /* flash unprotect */ + for (i = first; i <= last; i++) + clear_bit(i, pages); + } + + /* check the ranges_count after the user request */ + bitmap_to_ranges(pages, bank->num_sectors, ranges, &ranges_count); + + /* pretty-print the requested areas for protection */ + if (ranges_count > 0) { + char *ranges_str = range_print_alloc(ranges, ranges_count); + LOG_DEBUG("requested areas for protection: %s", ranges_str); + free(ranges_str); + } else + LOG_DEBUG("requested areas for protection: none"); + + if (ranges_count > n_wrp) { + LOG_ERROR("cannot set the requested protection " + "(only %u write protection areas are available)" , n_wrp); + return ERROR_FAIL; + } + + /* re-init all WRPxy as disabled (first > last)*/ + for (i = 0; i < n_wrp; i++) { + wrpxy[i].first = wrpxy[i].offset + 1; + wrpxy[i].last = wrpxy[i].offset; + } - ret = stm32l4_write_option(bank, stm32l4_info->flash_regs[STM32_FLASH_WRP1AR_INDEX], reg_value, 0xffffffff); + /* then configure WRPxy areas */ + for (i = 0; i < ranges_count; i++) { + wrpxy[i].first = ranges[i].start; + wrpxy[i].last = ranges[i].end; } - return ret; + /* finally write WRPxy registers */ + return stm32l4_write_all_wrpxy(bank, wrpxy, n_wrp); } /* Count is in double-words */ @@ -878,11 +1365,60 @@ static int stm32l4_write_block(struct flash_bank *bank, const uint8_t *buffer, return retval; } +/* Count is in double-words */ +static int stm32l4_write_block_without_loader(struct flash_bank *bank, const uint8_t *buffer, + uint32_t offset, uint32_t count) +{ + struct target *target = bank->target; + uint32_t address = bank->base + offset; + int retval = ERROR_OK; + + /* wait for BSY bit */ + retval = stm32l4_wait_status_busy(bank, FLASH_WRITE_TIMEOUT); + if (retval != ERROR_OK) + return retval; + + /* set PG in FLASH_CR */ + retval = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, FLASH_PG); + if (retval != ERROR_OK) + return retval; + + + /* write directly to flash memory */ + const uint8_t *src = buffer; + while (count--) { + retval = target_write_memory(target, address, 4, 2, src); + if (retval != ERROR_OK) + return retval; + + /* wait for BSY bit */ + retval = stm32l4_wait_status_busy(bank, FLASH_WRITE_TIMEOUT); + if (retval != ERROR_OK) + return retval; + + src += 8; + address += 8; + } + + /* reset PG in FLASH_CR */ + retval = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, 0); + if (retval != ERROR_OK) + return retval; + + return retval; +} + static int stm32l4_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t offset, uint32_t count) { + struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv; int retval = ERROR_OK, retval2; + if (stm32l4_is_otp(bank) && !stm32l4_otp_is_enabled(bank)) { + LOG_ERROR("OTP memory is disabled for write commands"); + return ERROR_FAIL; + } + if (bank->target->state != TARGET_HALTED) { LOG_ERROR("Target not halted"); return ERROR_TARGET_NOT_HALTED; @@ -930,15 +1466,47 @@ static int stm32l4_write(struct flash_bank *bank, const uint8_t *buffer, if (retval != ERROR_OK) return retval; + if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0)) { + /* set all FLASH pages as secure */ + retval = stm32l4_set_secbb(bank, FLASH_SECBB_SECURE); + if (retval != ERROR_OK) { + /* restore all FLASH pages as non-secure */ + stm32l4_set_secbb(bank, FLASH_SECBB_NON_SECURE); /* ignore the return value */ + return retval; + } + } + retval = stm32l4_unlock_reg(bank); if (retval != ERROR_OK) goto err_lock; - retval = stm32l4_write_block(bank, buffer, offset, count / 8); + if (stm32l4_info->use_flashloader) { + /* For TrustZone enabled devices, when TZEN is set and RDP level is 0.5, + * the debug is possible only in non-secure state. + * Thus means the flashloader will run in non-secure mode, + * and the workarea need to be in non-secure RAM */ + if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0_5)) + LOG_INFO("RDP level is 0.5, the work-area should reside in non-secure RAM"); + + retval = stm32l4_write_block(bank, buffer, offset, count / 8); + } + + if (!stm32l4_info->use_flashloader || retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) { + LOG_INFO("falling back to single memory accesses"); + retval = stm32l4_write_block_without_loader(bank, buffer, offset, count / 8); + } + err_lock: retval2 = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, FLASH_LOCK); + if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0)) { + /* restore all FLASH pages as non-secure */ + int retval3 = stm32l4_set_secbb(bank, FLASH_SECBB_NON_SECURE); + if (retval3 != ERROR_OK) + return retval3; + } + if (retval != ERROR_OK) { LOG_ERROR("block write failed"); return retval; @@ -951,10 +1519,10 @@ static int stm32l4_read_idcode(struct flash_bank *bank, uint32_t *id) int retval; /* try reading possible IDCODE registers, in the following order */ - uint32_t DBGMCU_IDCODE[] = {DBGMCU_IDCODE_L4_G4, DBGMCU_IDCODE_G0, DBGMCU_IDCODE_L5}; + uint32_t dbgmcu_idcode[] = {DBGMCU_IDCODE_L4_G4, DBGMCU_IDCODE_G0, DBGMCU_IDCODE_L5}; - for (unsigned int i = 0; i < ARRAY_SIZE(DBGMCU_IDCODE); i++) { - retval = target_read_u32(bank->target, DBGMCU_IDCODE[i], id); + for (unsigned int i = 0; i < ARRAY_SIZE(dbgmcu_idcode); i++) { + retval = target_read_u32(bank->target, dbgmcu_idcode[i], id); if ((retval == ERROR_OK) && ((*id & 0xfff) != 0) && ((*id & 0xfff) != 0xfff)) return ERROR_OK; } @@ -963,14 +1531,35 @@ static int stm32l4_read_idcode(struct flash_bank *bank, uint32_t *id) return (retval == ERROR_OK) ? ERROR_FAIL : retval; } +static const char *get_stm32l4_rev_str(struct flash_bank *bank) +{ + struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv; + const struct stm32l4_part_info *part_info = stm32l4_info->part_info; + assert(part_info); + + const uint16_t rev_id = stm32l4_info->idcode >> 16; + for (unsigned int i = 0; i < part_info->num_revs; i++) { + if (rev_id == part_info->revs[i].rev) + return part_info->revs[i].str; + } + return "'unknown'"; +} + +static const char *get_stm32l4_bank_type_str(struct flash_bank *bank) +{ + struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv; + assert(stm32l4_info->part_info); + return stm32l4_is_otp(bank) ? "OTP" : + stm32l4_info->dual_bank_mode ? "Flash dual" : + "Flash single"; +} + static int stm32l4_probe(struct flash_bank *bank) { struct target *target = bank->target; struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv; const struct stm32l4_part_info *part_info; uint16_t flash_size_kb = 0xffff; - uint32_t device_id; - uint32_t options; stm32l4_info->probed = false; @@ -979,11 +1568,13 @@ static int stm32l4_probe(struct flash_bank *bank) if (retval != ERROR_OK) return retval; - device_id = stm32l4_info->idcode & 0xFFF; + const uint32_t device_id = stm32l4_info->idcode & 0xFFF; for (unsigned int n = 0; n < ARRAY_SIZE(stm32l4_parts); n++) { - if (device_id == stm32l4_parts[n].id) + if (device_id == stm32l4_parts[n].id) { stm32l4_info->part_info = &stm32l4_parts[n]; + break; + } } if (!stm32l4_info->part_info) { @@ -992,14 +1583,52 @@ static int stm32l4_probe(struct flash_bank *bank) } part_info = stm32l4_info->part_info; + const char *rev_str = get_stm32l4_rev_str(bank); + const uint16_t rev_id = stm32l4_info->idcode >> 16; + + LOG_INFO("device idcode = 0x%08" PRIx32 " (%s - Rev %s : 0x%04x)", + stm32l4_info->idcode, part_info->device_str, rev_str, rev_id); + + stm32l4_info->flash_regs_base = stm32l4_info->part_info->flash_regs_base; stm32l4_info->flash_regs = stm32l4_info->part_info->default_flash_regs; - char device_info[1024]; - retval = bank->driver->info(bank, device_info, sizeof(device_info)); + /* read flash option register */ + retval = stm32l4_read_flash_reg_by_index(bank, STM32_FLASH_OPTR_INDEX, &stm32l4_info->optr); if (retval != ERROR_OK) return retval; - LOG_INFO("device idcode = 0x%08" PRIx32 " (%s)", stm32l4_info->idcode, device_info); + stm32l4_sync_rdp_tzen(bank); + + if (part_info->flags & F_HAS_TZ) + LOG_INFO("TZEN = %d : TrustZone %s by option bytes", + stm32l4_info->tzen, + stm32l4_info->tzen ? "enabled" : "disabled"); + + LOG_INFO("RDP level %s (0x%02X)", + stm32l4_info->rdp == RDP_LEVEL_0 ? "0" : stm32l4_info->rdp == RDP_LEVEL_0_5 ? "0.5" : "1", + stm32l4_info->rdp); + + if (stm32l4_is_otp(bank)) { + bank->size = part_info->otp_size; + + LOG_INFO("OTP size is %d bytes, base address is " TARGET_ADDR_FMT, bank->size, bank->base); + + /* OTP memory is considered as one sector */ + free(bank->sectors); + bank->num_sectors = 1; + bank->sectors = alloc_block_array(0, part_info->otp_size, 1); + + if (!bank->sectors) { + LOG_ERROR("failed to allocate bank sectors"); + return ERROR_FAIL; + } + + stm32l4_info->probed = true; + return ERROR_OK; + } else if (bank->base != STM32_FLASH_BANK_BASE && bank->base != STM32_FLASH_S_BANK_BASE) { + LOG_ERROR("invalid bank base address"); + return ERROR_FAIL; + } /* get flash size from target. */ retval = target_read_u16(target, part_info->fsize_addr, &flash_size_kb); @@ -1025,11 +1654,6 @@ static int stm32l4_probe(struct flash_bank *bank) /* did we assign a flash size? */ assert((flash_size_kb != 0xffff) && flash_size_kb); - /* read flash option register */ - retval = stm32l4_read_flash_reg_by_index(bank, STM32_FLASH_OPTR_INDEX, &options); - if (retval != ERROR_OK) - return retval; - stm32l4_info->bank1_sectors = 0; stm32l4_info->hole_sectors = 0; @@ -1055,7 +1679,7 @@ static int stm32l4_probe(struct flash_bank *bank) stm32l4_info->bank1_sectors = num_pages; /* check DUAL_BANK bit[21] if the flash is less than 1M */ - if (flash_size_kb == 1024 || (options & BIT(21))) { + if (flash_size_kb == 1024 || (stm32l4_info->optr & BIT(21))) { stm32l4_info->dual_bank_mode = true; stm32l4_info->bank1_sectors = num_pages / 2; } @@ -1081,7 +1705,7 @@ static int stm32l4_probe(struct flash_bank *bank) page_size_kb = 4; num_pages = flash_size_kb / page_size_kb; stm32l4_info->bank1_sectors = num_pages; - if (options & BIT(22)) { + if (stm32l4_info->optr & BIT(22)) { stm32l4_info->dual_bank_mode = true; page_size_kb = 2; num_pages = flash_size_kb / page_size_kb; @@ -1105,8 +1729,8 @@ static int stm32l4_probe(struct flash_bank *bank) num_pages = flash_size_kb / page_size_kb; stm32l4_info->bank1_sectors = num_pages; use_dbank_bit = flash_size_kb == part_info->max_flash_size_kb; - if ((use_dbank_bit && (options & BIT(22))) || - (!use_dbank_bit && (options & BIT(21)))) { + if ((use_dbank_bit && (stm32l4_info->optr & BIT(22))) || + (!use_dbank_bit && (stm32l4_info->optr & BIT(21)))) { stm32l4_info->dual_bank_mode = true; page_size_kb = 4; num_pages = flash_size_kb / page_size_kb; @@ -1122,13 +1746,22 @@ static int stm32l4_probe(struct flash_bank *bank) num_pages = flash_size_kb / page_size_kb; stm32l4_info->bank1_sectors = num_pages; use_dbank_bit = flash_size_kb == part_info->max_flash_size_kb; - if ((use_dbank_bit && (options & BIT(22))) || - (!use_dbank_bit && (options & BIT(21)))) { + if ((use_dbank_bit && (stm32l4_info->optr & BIT(22))) || + (!use_dbank_bit && (stm32l4_info->optr & BIT(21)))) { stm32l4_info->dual_bank_mode = true; page_size_kb = 2; num_pages = flash_size_kb / page_size_kb; stm32l4_info->bank1_sectors = num_pages / 2; } + + /** + * by default use the non-secure registers, + * switch secure registers if TZ is enabled and RDP is LEVEL_0 + */ + if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0)) { + stm32l4_info->flash_regs_base |= 0x10000000; + stm32l4_info->flash_regs = stm32l5_s_flash_regs; + } break; case 0x495: /* STM32WB5x */ case 0x496: /* STM32WB3x */ @@ -1165,7 +1798,7 @@ static int stm32l4_probe(struct flash_bank *bank) * max_flash_size is always power of two, so max_pages too */ uint32_t max_pages = stm32l4_info->part_info->max_flash_size_kb / page_size_kb; - assert((max_pages & (max_pages - 1)) == 0); + assert(IS_PWR_OF_2(max_pages)); /* in dual bank mode number of pages is doubled, but extra bit is bank selection */ stm32l4_info->wrpxxr_mask = ((max_pages >> (stm32l4_info->dual_bank_mode ? 1 : 0)) - 1); @@ -1175,10 +1808,9 @@ static int stm32l4_probe(struct flash_bank *bank) free(bank->sectors); bank->size = (flash_size_kb + gap_size_kb) * 1024; - bank->base = STM32_FLASH_BANK_BASE; bank->num_sectors = num_pages; bank->sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors); - if (bank->sectors == NULL) { + if (!bank->sectors) { LOG_ERROR("failed to allocate bank sectors"); return ERROR_FAIL; } @@ -1201,38 +1833,34 @@ static int stm32l4_probe(struct flash_bank *bank) static int stm32l4_auto_probe(struct flash_bank *bank) { struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv; - if (stm32l4_info->probed) - return ERROR_OK; + if (stm32l4_info->probed) { + uint32_t optr_cur; + + /* read flash option register and re-probe if optr value is changed */ + int retval = stm32l4_read_flash_reg_by_index(bank, STM32_FLASH_OPTR_INDEX, &optr_cur); + if (retval != ERROR_OK) + return retval; + + if (stm32l4_info->optr == optr_cur) + return ERROR_OK; + } return stm32l4_probe(bank); } -static int get_stm32l4_info(struct flash_bank *bank, char *buf, int buf_size) +static int get_stm32l4_info(struct flash_bank *bank, struct command_invocation *cmd) { struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv; const struct stm32l4_part_info *part_info = stm32l4_info->part_info; if (part_info) { - const char *rev_str = NULL; - uint16_t rev_id = stm32l4_info->idcode >> 16; - for (unsigned int i = 0; i < part_info->num_revs; i++) { - if (rev_id == part_info->revs[i].rev) { - rev_str = part_info->revs[i].str; - break; - } - } - - int buf_len = snprintf(buf, buf_size, "%s - Rev %s : 0x%04x", - part_info->device_str, rev_str ? rev_str : "'unknown'", rev_id); - + const uint16_t rev_id = stm32l4_info->idcode >> 16; + command_print_sameline(cmd, "%s - Rev %s : 0x%04x", part_info->device_str, + get_stm32l4_rev_str(bank), rev_id); if (stm32l4_info->probed) - snprintf(buf + buf_len, buf_size - buf_len, " - %s-bank", - stm32l4_info->dual_bank_mode ? "Flash dual" : "Flash single"); - - return ERROR_OK; + command_print_sameline(cmd, " - %s-bank", get_stm32l4_bank_type_str(bank)); } else { - snprintf(buf, buf_size, "Cannot identify target as an %s device", device_families); - return ERROR_FAIL; + command_print_sameline(cmd, "Cannot identify target as an %s device", device_families); } return ERROR_OK; @@ -1244,9 +1872,14 @@ static int stm32l4_mass_erase(struct flash_bank *bank) struct target *target = bank->target; struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv; + if (stm32l4_is_otp(bank)) { + LOG_ERROR("cannot erase OTP memory"); + return ERROR_FLASH_OPER_UNSUPPORTED; + } + uint32_t action = FLASH_MER1; - if (stm32l4_info->part_info->has_dual_bank) + if (stm32l4_info->part_info->flags & F_HAS_DUAL_BANK) action |= FLASH_MER2; if (target->state != TARGET_HALTED) { @@ -1254,6 +1887,16 @@ static int stm32l4_mass_erase(struct flash_bank *bank) return ERROR_TARGET_NOT_HALTED; } + if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0)) { + /* set all FLASH pages as secure */ + retval = stm32l4_set_secbb(bank, FLASH_SECBB_SECURE); + if (retval != ERROR_OK) { + /* restore all FLASH pages as non-secure */ + stm32l4_set_secbb(bank, FLASH_SECBB_NON_SECURE); /* ignore the return value */ + return retval; + } + } + retval = stm32l4_unlock_reg(bank); if (retval != ERROR_OK) goto err_lock; @@ -1276,6 +1919,13 @@ static int stm32l4_mass_erase(struct flash_bank *bank) err_lock: retval2 = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, FLASH_LOCK); + if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0)) { + /* restore all FLASH pages as non-secure */ + int retval3 = stm32l4_set_secbb(bank, FLASH_SECBB_NON_SECURE); + if (retval3 != ERROR_OK) + return retval3; + } + if (retval != ERROR_OK) return retval; @@ -1291,19 +1941,14 @@ COMMAND_HANDLER(stm32l4_handle_mass_erase_command) struct flash_bank *bank; int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; retval = stm32l4_mass_erase(bank); - if (retval == ERROR_OK) { - /* set all sectors as erased */ - for (unsigned int i = 0; i < bank->num_sectors; i++) - bank->sectors[i].is_erased = 1; - + if (retval == ERROR_OK) command_print(CMD, "stm32l4x mass erase complete"); - } else { + else command_print(CMD, "stm32l4x mass erase failed"); - } return retval; } @@ -1317,17 +1962,17 @@ COMMAND_HANDLER(stm32l4_handle_option_read_command) struct flash_bank *bank; int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; uint32_t reg_offset, reg_addr; uint32_t value = 0; - reg_offset = strtoul(CMD_ARGV[1], NULL, 16); + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], reg_offset); reg_addr = stm32l4_get_flash_reg(bank, reg_offset); retval = stm32l4_read_flash_reg(bank, reg_offset, &value); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; command_print(CMD, "Option Register: <0x%" PRIx32 "> = 0x%" PRIx32 "", reg_addr, value); @@ -1344,17 +1989,18 @@ COMMAND_HANDLER(stm32l4_handle_option_write_command) struct flash_bank *bank; int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; uint32_t reg_offset; uint32_t value = 0; uint32_t mask = 0xFFFFFFFF; - reg_offset = strtoul(CMD_ARGV[1], NULL, 16); - value = strtoul(CMD_ARGV[2], NULL, 16); + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], reg_offset); + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], value); + if (CMD_ARGC > 3) - mask = strtoul(CMD_ARGV[3], NULL, 16); + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[3], mask); command_print(CMD, "%s Option written.\n" "INFO: a reset or power cycle is required " @@ -1364,38 +2010,107 @@ COMMAND_HANDLER(stm32l4_handle_option_write_command) return retval; } -COMMAND_HANDLER(stm32l4_handle_option_load_command) +COMMAND_HANDLER(stm32l4_handle_trustzone_command) { - if (CMD_ARGC != 1) + if (CMD_ARGC < 1 || CMD_ARGC > 2) return ERROR_COMMAND_SYNTAX_ERROR; struct flash_bank *bank; int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; - retval = stm32l4_unlock_reg(bank); - if (ERROR_OK != retval) + struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv; + if (!(stm32l4_info->part_info->flags & F_HAS_TZ)) { + LOG_ERROR("This device does not have a TrustZone"); + return ERROR_FAIL; + } + + retval = stm32l4_read_flash_reg_by_index(bank, STM32_FLASH_OPTR_INDEX, &stm32l4_info->optr); + if (retval != ERROR_OK) return retval; - retval = stm32l4_unlock_option_reg(bank); - if (ERROR_OK != retval) + stm32l4_sync_rdp_tzen(bank); + + if (CMD_ARGC == 1) { + /* only display the TZEN value */ + LOG_INFO("Global TrustZone Security is %s", stm32l4_info->tzen ? "enabled" : "disabled"); + return ERROR_OK; + } + + bool new_tzen; + COMMAND_PARSE_ENABLE(CMD_ARGV[1], new_tzen); + + if (new_tzen == stm32l4_info->tzen) { + LOG_INFO("The requested TZEN is already programmed"); + return ERROR_OK; + } + + if (new_tzen) { + if (stm32l4_info->rdp != RDP_LEVEL_0) { + LOG_ERROR("TZEN can be set only when RDP level is 0"); + return ERROR_FAIL; + } + retval = stm32l4_write_option(bank, stm32l4_info->flash_regs[STM32_FLASH_OPTR_INDEX], + FLASH_TZEN, FLASH_TZEN); + } else { + /* Deactivation of TZEN (from 1 to 0) is only possible when the RDP is + * changing to level 0 (from level 1 to level 0 or from level 0.5 to level 0). */ + if (stm32l4_info->rdp != RDP_LEVEL_1 && stm32l4_info->rdp != RDP_LEVEL_0_5) { + LOG_ERROR("Deactivation of TZEN is only possible when the RDP is changing to level 0"); + return ERROR_FAIL; + } + + retval = stm32l4_write_option(bank, stm32l4_info->flash_regs[STM32_FLASH_OPTR_INDEX], + RDP_LEVEL_0, FLASH_RDP_MASK | FLASH_TZEN); + } + + if (retval != ERROR_OK) return retval; - /* Set OBL_LAUNCH bit in CR -> system reset and option bytes reload, - * but the RMs explicitly do *NOT* list this as power-on reset cause, and: - * "Note: If the read protection is set while the debugger is still - * connected through JTAG/SWD, apply a POR (power-on reset) instead of a system reset." - */ - retval = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, FLASH_OBL_LAUNCH); + return stm32l4_perform_obl_launch(bank); +} - command_print(CMD, "stm32l4x option load completed. Power-on reset might be required"); +COMMAND_HANDLER(stm32l4_handle_flashloader_command) +{ + if (CMD_ARGC < 1 || CMD_ARGC > 2) + return ERROR_COMMAND_SYNTAX_ERROR; + + struct flash_bank *bank; + int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); + if (retval != ERROR_OK) + return retval; - /* Need to re-probe after change */ struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv; - stm32l4_info->probed = false; - return retval; + if (CMD_ARGC == 2) + COMMAND_PARSE_ENABLE(CMD_ARGV[1], stm32l4_info->use_flashloader); + + command_print(CMD, "FlashLoader usage is %s", stm32l4_info->use_flashloader ? "enabled" : "disabled"); + + return ERROR_OK; +} + +COMMAND_HANDLER(stm32l4_handle_option_load_command) +{ + if (CMD_ARGC != 1) + return ERROR_COMMAND_SYNTAX_ERROR; + + struct flash_bank *bank; + int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); + if (retval != ERROR_OK) + return retval; + + retval = stm32l4_perform_obl_launch(bank); + if (retval != ERROR_OK) { + command_print(CMD, "stm32l4x option load failed"); + return retval; + } + + + command_print(CMD, "stm32l4x option load completed. Power-on reset might be required"); + + return ERROR_OK; } COMMAND_HANDLER(stm32l4_handle_lock_command) @@ -1407,9 +2122,14 @@ COMMAND_HANDLER(stm32l4_handle_lock_command) struct flash_bank *bank; int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; + if (stm32l4_is_otp(bank)) { + LOG_ERROR("cannot lock/unlock OTP memory"); + return ERROR_FLASH_OPER_UNSUPPORTED; + } + target = bank->target; if (target->state != TARGET_HALTED) { @@ -1419,7 +2139,8 @@ COMMAND_HANDLER(stm32l4_handle_lock_command) /* set readout protection level 1 by erasing the RDP option byte */ struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv; - if (stm32l4_write_option(bank, stm32l4_info->flash_regs[STM32_FLASH_OPTR_INDEX], 0, 0x000000FF) != ERROR_OK) { + if (stm32l4_write_option(bank, stm32l4_info->flash_regs[STM32_FLASH_OPTR_INDEX], + RDP_LEVEL_1, FLASH_RDP_MASK) != ERROR_OK) { command_print(CMD, "%s failed to lock device", bank->driver->name); return ERROR_OK; } @@ -1436,9 +2157,14 @@ COMMAND_HANDLER(stm32l4_handle_unlock_command) struct flash_bank *bank; int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; + if (stm32l4_is_otp(bank)) { + LOG_ERROR("cannot lock/unlock OTP memory"); + return ERROR_FLASH_OPER_UNSUPPORTED; + } + target = bank->target; if (target->state != TARGET_HALTED) { @@ -1448,7 +2174,7 @@ COMMAND_HANDLER(stm32l4_handle_unlock_command) struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv; if (stm32l4_write_option(bank, stm32l4_info->flash_regs[STM32_FLASH_OPTR_INDEX], - RDP_LEVEL_0, 0x000000FF) != ERROR_OK) { + RDP_LEVEL_0, FLASH_RDP_MASK) != ERROR_OK) { command_print(CMD, "%s failed to unlock device", bank->driver->name); return ERROR_OK; } @@ -1456,6 +2182,105 @@ COMMAND_HANDLER(stm32l4_handle_unlock_command) return ERROR_OK; } +COMMAND_HANDLER(stm32l4_handle_wrp_info_command) +{ + if (CMD_ARGC < 1 || CMD_ARGC > 2) + return ERROR_COMMAND_SYNTAX_ERROR; + + struct flash_bank *bank; + int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); + if (retval != ERROR_OK) + return retval; + + if (stm32l4_is_otp(bank)) { + LOG_ERROR("OTP memory does not have write protection areas"); + return ERROR_FLASH_OPER_UNSUPPORTED; + } + + struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv; + enum stm32_bank_id dev_bank_id = STM32_ALL_BANKS; + if (CMD_ARGC == 2) { + if (strcmp(CMD_ARGV[1], "bank1") == 0) + dev_bank_id = STM32_BANK1; + else if (strcmp(CMD_ARGV[1], "bank2") == 0) + dev_bank_id = STM32_BANK2; + else + return ERROR_COMMAND_ARGUMENT_INVALID; + } + + if (dev_bank_id == STM32_BANK2) { + if (!(stm32l4_info->part_info->flags & F_HAS_DUAL_BANK)) { + LOG_ERROR("this device has no second bank"); + return ERROR_FAIL; + } else if (!stm32l4_info->dual_bank_mode) { + LOG_ERROR("this device is configured in single bank mode"); + return ERROR_FAIL; + } + } + + int ret; + unsigned int n_wrp, i; + struct stm32l4_wrp wrpxy[4]; + + ret = stm32l4_get_all_wrpxy(bank, dev_bank_id, wrpxy, &n_wrp); + if (ret != ERROR_OK) + return ret; + + /* use bitmap and range helpers to better describe protected areas */ + DECLARE_BITMAP(pages, bank->num_sectors); + bitmap_zero(pages, bank->num_sectors); + + for (i = 0; i < n_wrp; i++) { + if (wrpxy[i].used) { + for (int p = wrpxy[i].first; p <= wrpxy[i].last; p++) + set_bit(p, pages); + } + } + + /* we have at most 'n_wrp' WRP areas */ + struct range ranges[n_wrp]; + unsigned int ranges_count = 0; + + bitmap_to_ranges(pages, bank->num_sectors, ranges, &ranges_count); + + if (ranges_count > 0) { + /* pretty-print the protected ranges */ + char *ranges_str = range_print_alloc(ranges, ranges_count); + command_print(CMD, "protected areas: %s", ranges_str); + free(ranges_str); + } else + command_print(CMD, "no protected areas"); + + return ERROR_OK; +} + +COMMAND_HANDLER(stm32l4_handle_otp_command) +{ + if (CMD_ARGC < 2) + return ERROR_COMMAND_SYNTAX_ERROR; + + struct flash_bank *bank; + int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); + if (retval != ERROR_OK) + return retval; + + if (!stm32l4_is_otp(bank)) { + command_print(CMD, "the specified bank is not an OTP memory"); + return ERROR_FAIL; + } + if (strcmp(CMD_ARGV[1], "enable") == 0) + stm32l4_otp_enable(bank, true); + else if (strcmp(CMD_ARGV[1], "disable") == 0) + stm32l4_otp_enable(bank, false); + else if (strcmp(CMD_ARGV[1], "show") == 0) + command_print(CMD, "OTP memory bank #%d is %s for write commands.", + bank->bank_number, stm32l4_otp_is_enabled(bank) ? "enabled" : "disabled"); + else + return ERROR_COMMAND_SYNTAX_ERROR; + + return ERROR_OK; +} + static const struct command_registration stm32l4_exec_command_handlers[] = { { .name = "lock", @@ -1471,6 +2296,13 @@ static const struct command_registration stm32l4_exec_command_handlers[] = { .usage = "bank_id", .help = "Unlock entire protected flash device.", }, + { + .name = "flashloader", + .handler = stm32l4_handle_flashloader_command, + .mode = COMMAND_EXEC, + .usage = " [enable|disable]", + .help = "Configure the flashloader usage", + }, { .name = "mass_erase", .handler = stm32l4_handle_mass_erase_command, @@ -1492,6 +2324,20 @@ static const struct command_registration stm32l4_exec_command_handlers[] = { .usage = "bank_id reg_offset value mask", .help = "Write device option bit fields with provided value.", }, + { + .name = "trustzone", + .handler = stm32l4_handle_trustzone_command, + .mode = COMMAND_EXEC, + .usage = " [enable|disable]", + .help = "Configure TrustZone security", + }, + { + .name = "wrp_info", + .handler = stm32l4_handle_wrp_info_command, + .mode = COMMAND_EXEC, + .usage = "bank_id [bank1|bank2]", + .help = "list the protected areas using WRP", + }, { .name = "option_load", .handler = stm32l4_handle_option_load_command, @@ -1499,6 +2345,13 @@ static const struct command_registration stm32l4_exec_command_handlers[] = { .usage = "bank_id", .help = "Force re-load of device options (will cause device reset).", }, + { + .name = "otp", + .handler = stm32l4_handle_otp_command, + .mode = COMMAND_EXEC, + .usage = " ", + .help = "OTP (One Time Programmable) memory write enable/disable", + }, COMMAND_REGISTRATION_DONE };