X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Fflash%2Fnor%2Fstm32l4x.c;h=ca8a3b81de6f5fcc889feb9e5e4e519dc7c2e0d2;hb=dc43ecce5a7ee5722ea851707ad3acd08a42b5aa;hp=b6f0d714d8ccc336a30375c7409eb369dcbccb2b;hpb=ba131f30a0798d97729f9517c136d32f58f57571;p=openocd.git diff --git a/src/flash/nor/stm32l4x.c b/src/flash/nor/stm32l4x.c index b6f0d714d8..ca8a3b81de 100644 --- a/src/flash/nor/stm32l4x.c +++ b/src/flash/nor/stm32l4x.c @@ -75,8 +75,13 @@ * http://www.st.com/resource/en/reference_manual/dm00622834.pdf */ -/* - * STM32G0xxx series for reference. +/* STM32WLxxx series for reference. + * + * RM0461 (STM32WLEx) + * http://www.st.com/resource/en/reference_manual/dm00530369.pdf + */ + +/* STM32G0xxx series for reference. * * RM0444 (STM32G0x1) * http://www.st.com/resource/en/reference_manual/dm00371828.pdf @@ -85,10 +90,9 @@ * http://www.st.com/resource/en/reference_manual/dm00463896.pdf */ -/* - * STM32G4xxx series for reference. +/* STM32G4xxx series for reference. * - * RM0440 (STM32G43x/44x/47x/48x) + * RM0440 (STM32G43x/44x/47x/48x/49x/4Ax) * http://www.st.com/resource/en/reference_manual/dm00355726.pdf * * Cat. 2 devices have single bank only, page size is 2kByte. @@ -98,12 +102,41 @@ * * Bank mode is controlled by bit 22 (DBANK) in option bytes register. * Both banks are treated as a single OpenOCD bank. + * + * Cat. 4 devices have single bank only, page size is 2kByte. */ /* Erase time can be as high as 25ms, 10x this and assume it's toast... */ #define FLASH_ERASE_TIMEOUT 250 +enum stm32l4_flash_reg_index { + STM32_FLASH_ACR_INDEX, + STM32_FLASH_KEYR_INDEX, + STM32_FLASH_OPTKEYR_INDEX, + STM32_FLASH_SR_INDEX, + STM32_FLASH_CR_INDEX, + STM32_FLASH_OPTR_INDEX, + STM32_FLASH_WRP1AR_INDEX, + STM32_FLASH_WRP1BR_INDEX, + STM32_FLASH_WRP2AR_INDEX, + STM32_FLASH_WRP2BR_INDEX, + STM32_FLASH_REG_INDEX_NUM, +}; + +static const uint32_t stm32l4_flash_regs[STM32_FLASH_REG_INDEX_NUM] = { + [STM32_FLASH_ACR_INDEX] = 0x000, + [STM32_FLASH_KEYR_INDEX] = 0x008, + [STM32_FLASH_OPTKEYR_INDEX] = 0x00C, + [STM32_FLASH_SR_INDEX] = 0x010, + [STM32_FLASH_CR_INDEX] = 0x014, + [STM32_FLASH_OPTR_INDEX] = 0x020, + [STM32_FLASH_WRP1AR_INDEX] = 0x02C, + [STM32_FLASH_WRP1BR_INDEX] = 0x030, + [STM32_FLASH_WRP2AR_INDEX] = 0x04C, + [STM32_FLASH_WRP2BR_INDEX] = 0x050, +}; + struct stm32l4_rev { const uint16_t rev; const char *str; @@ -117,22 +150,24 @@ struct stm32l4_part_info { const uint16_t max_flash_size_kb; const bool has_dual_bank; const uint32_t flash_regs_base; + const uint32_t *default_flash_regs; const uint32_t fsize_addr; }; struct stm32l4_flash_bank { bool probed; uint32_t idcode; - int bank1_sectors; + unsigned int bank1_sectors; bool dual_bank_mode; int hole_sectors; uint32_t user_bank_size; uint32_t wrpxxr_mask; const struct stm32l4_part_info *part_info; + const uint32_t *flash_regs; }; -/* human readable list of families this drivers supports */ -static const char *device_families = "STM32L4/L4+/WB/G4/G0"; +/* human readable list of families this drivers supports (sorted alphabetically) */ +static const char *device_families = "STM32G0/G4/L4/L4+/WB/WL"; static const struct stm32l4_rev stm32_415_revs[] = { { 0x1000, "1" }, { 0x1001, "2" }, { 0x1003, "3" }, { 0x1007, "4" } @@ -175,13 +210,25 @@ static const struct stm32l4_rev stm32_470_revs[] = { }; static const struct stm32l4_rev stm32_471_revs[] = { - { 0x1000, "1" }, + { 0x1001, "Z" }, +}; + +static const struct stm32l4_rev stm32_479_revs[] = { + { 0x1000, "A" }, }; static const struct stm32l4_rev stm32_495_revs[] = { { 0x2001, "2.1" }, }; +static const struct stm32l4_rev stm32_496_revs[] = { + { 0x1000, "A" }, +}; + +static const struct stm32l4_rev stm32_497_revs[] = { + { 0x1000, "1.0" }, +}; + static const struct stm32l4_part_info stm32l4_parts[] = { { .id = 0x415, @@ -191,6 +238,7 @@ static const struct stm32l4_part_info stm32l4_parts[] = { .max_flash_size_kb = 1024, .has_dual_bank = true, .flash_regs_base = 0x40022000, + .default_flash_regs = stm32l4_flash_regs, .fsize_addr = 0x1FFF75E0, }, { @@ -201,6 +249,7 @@ static const struct stm32l4_part_info stm32l4_parts[] = { .max_flash_size_kb = 256, .has_dual_bank = false, .flash_regs_base = 0x40022000, + .default_flash_regs = stm32l4_flash_regs, .fsize_addr = 0x1FFF75E0, }, { @@ -211,6 +260,7 @@ static const struct stm32l4_part_info stm32l4_parts[] = { .max_flash_size_kb = 128, .has_dual_bank = false, .flash_regs_base = 0x40022000, + .default_flash_regs = stm32l4_flash_regs, .fsize_addr = 0x1FFF75E0, }, { @@ -221,6 +271,7 @@ static const struct stm32l4_part_info stm32l4_parts[] = { .max_flash_size_kb = 1024, .has_dual_bank = true, .flash_regs_base = 0x40022000, + .default_flash_regs = stm32l4_flash_regs, .fsize_addr = 0x1FFF75E0, }, { @@ -231,6 +282,7 @@ static const struct stm32l4_part_info stm32l4_parts[] = { .max_flash_size_kb = 512, .has_dual_bank = false, .flash_regs_base = 0x40022000, + .default_flash_regs = stm32l4_flash_regs, .fsize_addr = 0x1FFF75E0, }, { @@ -241,6 +293,7 @@ static const struct stm32l4_part_info stm32l4_parts[] = { .max_flash_size_kb = 128, .has_dual_bank = false, .flash_regs_base = 0x40022000, + .default_flash_regs = stm32l4_flash_regs, .fsize_addr = 0x1FFF75E0, }, { @@ -251,6 +304,7 @@ static const struct stm32l4_part_info stm32l4_parts[] = { .max_flash_size_kb = 64, .has_dual_bank = false, .flash_regs_base = 0x40022000, + .default_flash_regs = stm32l4_flash_regs, .fsize_addr = 0x1FFF75E0, }, { @@ -261,6 +315,7 @@ static const struct stm32l4_part_info stm32l4_parts[] = { .max_flash_size_kb = 128, .has_dual_bank = false, .flash_regs_base = 0x40022000, + .default_flash_regs = stm32l4_flash_regs, .fsize_addr = 0x1FFF75E0, }, { @@ -271,6 +326,7 @@ static const struct stm32l4_part_info stm32l4_parts[] = { .max_flash_size_kb = 512, .has_dual_bank = true, .flash_regs_base = 0x40022000, + .default_flash_regs = stm32l4_flash_regs, .fsize_addr = 0x1FFF75E0, }, { @@ -281,6 +337,7 @@ static const struct stm32l4_part_info stm32l4_parts[] = { .max_flash_size_kb = 2048, .has_dual_bank = true, .flash_regs_base = 0x40022000, + .default_flash_regs = stm32l4_flash_regs, .fsize_addr = 0x1FFF75E0, }, { @@ -291,6 +348,18 @@ static const struct stm32l4_part_info stm32l4_parts[] = { .max_flash_size_kb = 1024, .has_dual_bank = true, .flash_regs_base = 0x40022000, + .default_flash_regs = stm32l4_flash_regs, + .fsize_addr = 0x1FFF75E0, + }, + { + .id = 0x479, + .revs = stm32_479_revs, + .num_revs = ARRAY_SIZE(stm32_479_revs), + .device_str = "STM32G49/G4Axx", + .max_flash_size_kb = 512, + .has_dual_bank = false, + .flash_regs_base = 0x40022000, + .default_flash_regs = stm32l4_flash_regs, .fsize_addr = 0x1FFF75E0, }, { @@ -301,6 +370,29 @@ static const struct stm32l4_part_info stm32l4_parts[] = { .max_flash_size_kb = 1024, .has_dual_bank = false, .flash_regs_base = 0x58004000, + .default_flash_regs = stm32l4_flash_regs, + .fsize_addr = 0x1FFF75E0, + }, + { + .id = 0x496, + .revs = stm32_496_revs, + .num_revs = ARRAY_SIZE(stm32_496_revs), + .device_str = "STM32WB3x", + .max_flash_size_kb = 512, + .has_dual_bank = false, + .flash_regs_base = 0x58004000, + .default_flash_regs = stm32l4_flash_regs, + .fsize_addr = 0x1FFF75E0, + }, + { + .id = 0x497, + .revs = stm32_497_revs, + .num_revs = ARRAY_SIZE(stm32_497_revs), + .device_str = "STM32WLEx", + .max_flash_size_kb = 256, + .has_dual_bank = false, + .flash_regs_base = 0x58004000, + .default_flash_regs = stm32l4_flash_regs, .fsize_addr = 0x1FFF75E0, }, }; @@ -334,16 +426,37 @@ static inline uint32_t stm32l4_get_flash_reg(struct flash_bank *bank, uint32_t r return stm32l4_info->part_info->flash_regs_base + reg_offset; } +static inline uint32_t stm32l4_get_flash_reg_by_index(struct flash_bank *bank, + enum stm32l4_flash_reg_index reg_index) +{ + struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv; + return stm32l4_get_flash_reg(bank, stm32l4_info->flash_regs[reg_index]); +} + static inline int stm32l4_read_flash_reg(struct flash_bank *bank, uint32_t reg_offset, uint32_t *value) { return target_read_u32(bank->target, stm32l4_get_flash_reg(bank, reg_offset), value); } +static inline int stm32l4_read_flash_reg_by_index(struct flash_bank *bank, + enum stm32l4_flash_reg_index reg_index, uint32_t *value) +{ + struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv; + return stm32l4_read_flash_reg(bank, stm32l4_info->flash_regs[reg_index], value); +} + static inline int stm32l4_write_flash_reg(struct flash_bank *bank, uint32_t reg_offset, uint32_t value) { return target_write_u32(bank->target, stm32l4_get_flash_reg(bank, reg_offset), value); } +static inline int stm32l4_write_flash_reg_by_index(struct flash_bank *bank, + enum stm32l4_flash_reg_index reg_index, uint32_t value) +{ + struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv; + return stm32l4_write_flash_reg(bank, stm32l4_info->flash_regs[reg_index], value); +} + static int stm32l4_wait_status_busy(struct flash_bank *bank, int timeout) { uint32_t status; @@ -351,7 +464,7 @@ static int stm32l4_wait_status_busy(struct flash_bank *bank, int timeout) /* wait for busy to clear */ for (;;) { - retval = stm32l4_read_flash_reg(bank, STM32_FLASH_SR, &status); + retval = stm32l4_read_flash_reg_by_index(bank, STM32_FLASH_SR_INDEX, &status); if (retval != ERROR_OK) return retval; LOG_DEBUG("status: 0x%" PRIx32 "", status); @@ -377,7 +490,7 @@ static int stm32l4_wait_status_busy(struct flash_bank *bank, int timeout) /* If this operation fails, we ignore it and report the original * retval */ - stm32l4_write_flash_reg(bank, STM32_FLASH_SR, status & FLASH_ERROR); + stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_SR_INDEX, status & FLASH_ERROR); } return retval; @@ -390,7 +503,7 @@ static int stm32l4_unlock_reg(struct flash_bank *bank) /* first check if not already unlocked * otherwise writing on STM32_FLASH_KEYR will fail */ - int retval = stm32l4_read_flash_reg(bank, STM32_FLASH_CR, &ctrl); + int retval = stm32l4_read_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, &ctrl); if (retval != ERROR_OK) return retval; @@ -398,15 +511,15 @@ static int stm32l4_unlock_reg(struct flash_bank *bank) return ERROR_OK; /* unlock flash registers */ - retval = stm32l4_write_flash_reg(bank, STM32_FLASH_KEYR, KEY1); + retval = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_KEYR_INDEX, KEY1); if (retval != ERROR_OK) return retval; - retval = stm32l4_write_flash_reg(bank, STM32_FLASH_KEYR, KEY2); + retval = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_KEYR_INDEX, KEY2); if (retval != ERROR_OK) return retval; - retval = stm32l4_read_flash_reg(bank, STM32_FLASH_CR, &ctrl); + retval = stm32l4_read_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, &ctrl); if (retval != ERROR_OK) return retval; @@ -422,7 +535,7 @@ static int stm32l4_unlock_option_reg(struct flash_bank *bank) { uint32_t ctrl; - int retval = stm32l4_read_flash_reg(bank, STM32_FLASH_CR, &ctrl); + int retval = stm32l4_read_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, &ctrl); if (retval != ERROR_OK) return retval; @@ -430,15 +543,15 @@ static int stm32l4_unlock_option_reg(struct flash_bank *bank) return ERROR_OK; /* unlock option registers */ - retval = stm32l4_write_flash_reg(bank, STM32_FLASH_OPTKEYR, OPTKEY1); + retval = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_OPTKEYR_INDEX, OPTKEY1); if (retval != ERROR_OK) return retval; - retval = stm32l4_write_flash_reg(bank, STM32_FLASH_OPTKEYR, OPTKEY2); + retval = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_OPTKEYR_INDEX, OPTKEY2); if (retval != ERROR_OK) return retval; - retval = stm32l4_read_flash_reg(bank, STM32_FLASH_CR, &ctrl); + retval = stm32l4_read_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, &ctrl); if (retval != ERROR_OK) return retval; @@ -474,14 +587,14 @@ static int stm32l4_write_option(struct flash_bank *bank, uint32_t reg_offset, if (retval != ERROR_OK) goto err_lock; - retval = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, FLASH_OPTSTRT); + retval = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, FLASH_OPTSTRT); if (retval != ERROR_OK) goto err_lock; retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT); err_lock: - retval2 = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, FLASH_LOCK | FLASH_OPTLOCK); + retval2 = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, FLASH_LOCK | FLASH_OPTLOCK); if (retval != ERROR_OK) return retval; @@ -494,13 +607,13 @@ static int stm32l4_protect_check(struct flash_bank *bank) struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv; uint32_t wrp1ar, wrp1br, wrp2ar, wrp2br; - stm32l4_read_flash_reg(bank, STM32_FLASH_WRP1AR, &wrp1ar); - stm32l4_read_flash_reg(bank, STM32_FLASH_WRP1BR, &wrp1br); + stm32l4_read_flash_reg_by_index(bank, STM32_FLASH_WRP1AR_INDEX, &wrp1ar); + stm32l4_read_flash_reg_by_index(bank, STM32_FLASH_WRP1BR_INDEX, &wrp1br); if (stm32l4_info->part_info->has_dual_bank) { - stm32l4_read_flash_reg(bank, STM32_FLASH_WRP2AR, &wrp2ar); - stm32l4_read_flash_reg(bank, STM32_FLASH_WRP2BR, &wrp2br); + stm32l4_read_flash_reg_by_index(bank, STM32_FLASH_WRP2AR_INDEX, &wrp2ar); + stm32l4_read_flash_reg_by_index(bank, STM32_FLASH_WRP2BR_INDEX, &wrp2br); } else { - /* prevent unintialized errors */ + /* prevent uninitialized errors */ wrp2ar = 0; wrp2br = 0; } @@ -514,7 +627,7 @@ static int stm32l4_protect_check(struct flash_bank *bank) const uint8_t wrp2b_start = wrp2br & stm32l4_info->wrpxxr_mask; const uint8_t wrp2b_end = (wrp2br >> 16) & stm32l4_info->wrpxxr_mask; - for (int i = 0; i < bank->num_sectors; i++) { + for (unsigned int i = 0; i < bank->num_sectors; i++) { if (i < stm32l4_info->bank1_sectors) { if (((i >= wrp1a_start) && (i <= wrp1a_end)) || @@ -539,13 +652,13 @@ static int stm32l4_protect_check(struct flash_bank *bank) return ERROR_OK; } -static int stm32l4_erase(struct flash_bank *bank, int first, int last) +static int stm32l4_erase(struct flash_bank *bank, unsigned int first, + unsigned int last) { struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv; - int i; int retval, retval2; - assert((0 <= first) && (first <= last) && (last < bank->num_sectors)); + assert((first <= last) && (last < bank->num_sectors)); if (bank->target->state != TARGET_HALTED) { LOG_ERROR("Target not halted"); @@ -567,7 +680,7 @@ static int stm32l4_erase(struct flash_bank *bank, int first, int last) 4. Wait for the BSY bit to be cleared */ - for (i = first; i <= last; i++) { + for (unsigned int i = first; i <= last; i++) { uint32_t erase_flags; erase_flags = FLASH_PER | FLASH_STRT; @@ -577,7 +690,7 @@ static int stm32l4_erase(struct flash_bank *bank, int first, int last) erase_flags |= snb << FLASH_PAGE_SHIFT | FLASH_CR_BKER; } else erase_flags |= i << FLASH_PAGE_SHIFT; - retval = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, erase_flags); + retval = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, erase_flags); if (retval != ERROR_OK) break; @@ -589,7 +702,7 @@ static int stm32l4_erase(struct flash_bank *bank, int first, int last) } err_lock: - retval2 = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, FLASH_LOCK); + retval2 = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, FLASH_LOCK); if (retval != ERROR_OK) return retval; @@ -597,7 +710,8 @@ err_lock: return retval2; } -static int stm32l4_protect(struct flash_bank *bank, int set, int first, int last) +static int stm32l4_protect(struct flash_bank *bank, int set, unsigned int first, + unsigned int last) { struct target *target = bank->target; struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv; @@ -616,7 +730,7 @@ static int stm32l4_protect(struct flash_bank *bank, int set, int first, int last reg_value = ((last & 0xFF) << 16) | begin; } - ret = stm32l4_write_option(bank, STM32_FLASH_WRP2AR, reg_value, 0xffffffff); + ret = stm32l4_write_option(bank, stm32l4_info->flash_regs[STM32_FLASH_WRP2AR_INDEX], reg_value, 0xffffffff); } /* Bank 1 */ reg_value = 0xFF; /* Default to bank un-protected */ @@ -626,7 +740,7 @@ static int stm32l4_protect(struct flash_bank *bank, int set, int first, int last reg_value = (end << 16) | (first & 0xFF); } - ret = stm32l4_write_option(bank, STM32_FLASH_WRP1AR, reg_value, 0xffffffff); + ret = stm32l4_write_option(bank, stm32l4_info->flash_regs[STM32_FLASH_WRP1AR_INDEX], reg_value, 0xffffffff); } return ret; @@ -637,7 +751,6 @@ static int stm32l4_write_block(struct flash_bank *bank, const uint8_t *buffer, uint32_t offset, uint32_t count) { struct target *target = bank->target; - struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv; uint32_t buffer_size; struct working_area *write_algorithm; struct working_area *source; @@ -693,8 +806,8 @@ static int stm32l4_write_block(struct flash_bank *bank, const uint8_t *buffer, buf_set_u32(reg_params[1].value, 0, 32, source->address + source->size); buf_set_u32(reg_params[2].value, 0, 32, address); buf_set_u32(reg_params[3].value, 0, 32, count); - buf_set_u32(reg_params[4].value, 0, 32, stm32l4_info->part_info->flash_regs_base + STM32_FLASH_SR); - buf_set_u32(reg_params[5].value, 0, 32, stm32l4_info->part_info->flash_regs_base + STM32_FLASH_CR); + buf_set_u32(reg_params[4].value, 0, 32, stm32l4_get_flash_reg_by_index(bank, STM32_FLASH_SR_INDEX)); + buf_set_u32(reg_params[5].value, 0, 32, stm32l4_get_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX)); retval = target_run_flash_async_algorithm(target, buffer, count, 8, 0, NULL, @@ -714,7 +827,7 @@ static int stm32l4_write_block(struct flash_bank *bank, const uint8_t *buffer, if (error != 0) { LOG_ERROR("flash write failed = %08" PRIx32, error); /* Clear but report errors */ - stm32l4_write_flash_reg(bank, STM32_FLASH_SR, error); + stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_SR_INDEX, error); retval = ERROR_FAIL; } } @@ -791,7 +904,7 @@ static int stm32l4_write(struct flash_bank *bank, const uint8_t *buffer, retval = stm32l4_write_block(bank, buffer, offset, count / 8); err_lock: - retval2 = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, FLASH_LOCK); + retval2 = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, FLASH_LOCK); if (retval != ERROR_OK) { LOG_ERROR("block write failed"); @@ -846,6 +959,7 @@ static int stm32l4_probe(struct flash_bank *bank) } part_info = stm32l4_info->part_info; + stm32l4_info->flash_regs = stm32l4_info->part_info->default_flash_regs; char device_info[1024]; retval = bank->driver->info(bank, device_info, sizeof(device_info)); @@ -879,7 +993,7 @@ static int stm32l4_probe(struct flash_bank *bank) assert((flash_size_kb != 0xffff) && flash_size_kb); /* read flash option register */ - retval = stm32l4_read_flash_reg(bank, STM32_FLASH_OPTR, &options); + retval = stm32l4_read_flash_reg_by_index(bank, STM32_FLASH_OPTR_INDEX, &options); if (retval != ERROR_OK) return retval; @@ -918,6 +1032,8 @@ static int stm32l4_probe(struct flash_bank *bank) case 0x464: /* STM32L41/L42xx */ case 0x466: /* STM32G03/G04xx */ case 0x468: /* STM32G43/G44xx */ + case 0x479: /* STM32G49/G4Axx */ + case 0x497: /* STM32WLEx */ /* single bank flash */ page_size_kb = 2; num_pages = flash_size_kb / page_size_kb; @@ -964,6 +1080,7 @@ static int stm32l4_probe(struct flash_bank *bank) } break; case 0x495: /* STM32WB5x */ + case 0x496: /* STM32WB3x */ /* single bank flash */ page_size_kb = 4; num_pages = flash_size_kb / page_size_kb; @@ -979,7 +1096,7 @@ static int stm32l4_probe(struct flash_bank *bank) const int gap_size_kb = stm32l4_info->hole_sectors * page_size_kb; if (gap_size_kb != 0) { - LOG_INFO("gap detected from 0x%08" PRIx32 " to 0x%08" PRIx32, + LOG_INFO("gap detected from 0x%08x to 0x%08x", STM32_FLASH_BANK_BASE + stm32l4_info->bank1_sectors * page_size_kb * 1024, STM32_FLASH_BANK_BASE + (stm32l4_info->bank1_sectors @@ -1002,12 +1119,9 @@ static int stm32l4_probe(struct flash_bank *bank) /* in dual bank mode number of pages is doubled, but extra bit is bank selection */ stm32l4_info->wrpxxr_mask = ((max_pages >> (stm32l4_info->dual_bank_mode ? 1 : 0)) - 1); assert((stm32l4_info->wrpxxr_mask & 0xFFFF0000) == 0); - LOG_DEBUG("WRPxxR mask 0x%04" PRIx16, stm32l4_info->wrpxxr_mask); + LOG_DEBUG("WRPxxR mask 0x%04" PRIx16, (uint16_t)stm32l4_info->wrpxxr_mask); - if (bank->sectors) { - free(bank->sectors); - bank->sectors = NULL; - } + free(bank->sectors); bank->size = (flash_size_kb + gap_size_kb) * 1024; bank->base = STM32_FLASH_BANK_BASE; @@ -1018,7 +1132,7 @@ static int stm32l4_probe(struct flash_bank *bank) return ERROR_FAIL; } - for (int i = 0; i < bank->num_sectors; i++) { + for (unsigned int i = 0; i < bank->num_sectors; i++) { bank->sectors[i].offset = i * page_size_kb * 1024; /* in dual bank configuration, if there is a gap between banks * we fix up the sector offset to consider this gap */ @@ -1100,18 +1214,18 @@ static int stm32l4_mass_erase(struct flash_bank *bank) if (retval != ERROR_OK) goto err_lock; - retval = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, action); + retval = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, action); if (retval != ERROR_OK) goto err_lock; - retval = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, action | FLASH_STRT); + retval = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, action | FLASH_STRT); if (retval != ERROR_OK) goto err_lock; - retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT); + retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT); err_lock: - retval2 = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, FLASH_LOCK); + retval2 = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, FLASH_LOCK); if (retval != ERROR_OK) return retval; @@ -1134,7 +1248,7 @@ COMMAND_HANDLER(stm32l4_handle_mass_erase_command) retval = stm32l4_mass_erase(bank); if (retval == ERROR_OK) { /* set all sectors as erased */ - for (int i = 0; i < bank->num_sectors; i++) + for (unsigned int i = 0; i < bank->num_sectors; i++) bank->sectors[i].is_erased = 1; command_print(CMD, "stm32l4x mass erase complete"); @@ -1203,7 +1317,7 @@ COMMAND_HANDLER(stm32l4_handle_option_write_command) COMMAND_HANDLER(stm32l4_handle_option_load_command) { - if (CMD_ARGC < 1) + if (CMD_ARGC != 1) return ERROR_COMMAND_SYNTAX_ERROR; struct flash_bank *bank; @@ -1224,7 +1338,7 @@ COMMAND_HANDLER(stm32l4_handle_option_load_command) * "Note: If the read protection is set while the debugger is still * connected through JTAG/SWD, apply a POR (power-on reset) instead of a system reset." */ - retval = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, FLASH_OBL_LAUNCH); + retval = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, FLASH_OBL_LAUNCH); command_print(CMD, "stm32l4x option load completed. Power-on reset might be required"); @@ -1255,7 +1369,8 @@ COMMAND_HANDLER(stm32l4_handle_lock_command) } /* set readout protection level 1 by erasing the RDP option byte */ - if (stm32l4_write_option(bank, STM32_FLASH_OPTR, 0, 0x000000FF) != ERROR_OK) { + struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv; + if (stm32l4_write_option(bank, stm32l4_info->flash_regs[STM32_FLASH_OPTR_INDEX], 0, 0x000000FF) != ERROR_OK) { command_print(CMD, "%s failed to lock device", bank->driver->name); return ERROR_OK; } @@ -1282,7 +1397,9 @@ COMMAND_HANDLER(stm32l4_handle_unlock_command) return ERROR_TARGET_NOT_HALTED; } - if (stm32l4_write_option(bank, STM32_FLASH_OPTR, RDP_LEVEL_0, 0x000000FF) != ERROR_OK) { + struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv; + if (stm32l4_write_option(bank, stm32l4_info->flash_regs[STM32_FLASH_OPTR_INDEX], + RDP_LEVEL_0, 0x000000FF) != ERROR_OK) { command_print(CMD, "%s failed to unlock device", bank->driver->name); return ERROR_OK; }