X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2FMakefile.am;h=49e882fe6c6a5e2c062525eb4fb75e0356b5796a;hb=0dcf95c7171b702d70ec326f8c1a63cbc9255b6f;hp=08a4b961f1f58bf23fda84ce764f4cb4b6ab7619;hpb=80f1a92bd7989bfdd8b7f00d947149b77407e15c;p=openocd.git diff --git a/src/target/Makefile.am b/src/target/Makefile.am index 08a4b961f1..49e882fe6c 100644 --- a/src/target/Makefile.am +++ b/src/target/Makefile.am @@ -1,12 +1,7 @@ -if OOCD_TRACE -OOCD_TRACE_FILES = %D%/oocd_trace.c -else -OOCD_TRACE_FILES = -endif - %C%_libtarget_la_LIBADD = %D%/openrisc/libopenrisc.la \ %D%/riscv/libriscv.la +%C%_libtarget_la_CPPFLAGS = $(AM_CPPFLAGS) STARTUP_TCL_SRCS += %D%/startup.tcl @@ -24,15 +19,18 @@ noinst_LTLIBRARIES += %D%/libtarget.la $(STM8_SRC) \ $(INTEL_IA32_SRC) \ $(ESIRISC_SRC) \ + $(ARC_SRC) \ %D%/avrt.c \ %D%/dsp563xx.c \ %D%/dsp563xx_once.c \ %D%/dsp5680xx.c \ - %D%/hla_target.c + %D%/hla_target.c \ + $(ARMV8_SRC) \ + $(MIPS64_SRC) -if TARGET64 -%C%_libtarget_la_SOURCES +=$(ARMV8_SRC) -%C%_libtarget_la_SOURCES +=$(MIPS64_SRC) +if HAVE_CAPSTONE +%C%_libtarget_la_CPPFLAGS += $(CAPSTONE_CFLAGS) +%C%_libtarget_la_LIBADD += $(CAPSTONE_LIBS) endif TARGET_CORE_SRC = \ @@ -44,7 +42,8 @@ TARGET_CORE_SRC = \ %D%/target_request.c \ %D%/testee.c \ %D%/semihosting_common.c \ - %D%/smp.c + %D%/smp.c \ + %D%/rtt.c ARMV4_5_SRC = \ %D%/armv4_5.c \ @@ -85,6 +84,7 @@ ARMV8_SRC = \ %D%/armv8_dpm.c \ %D%/armv8_opcodes.c \ %D%/aarch64.c \ + %D%/a64_disassembler.c \ %D%/armv8.c \ %D%/armv8_cache.c @@ -98,14 +98,15 @@ ARM_DEBUG_SRC = \ %D%/arm_dap.c \ %D%/armv7a_cache.c \ %D%/armv7a_cache_l2x.c \ + %D%/adi_v5_dapdirect.c \ %D%/adi_v5_jtag.c \ %D%/adi_v5_swd.c \ %D%/embeddedice.c \ %D%/trace.c \ %D%/etb.c \ %D%/etm.c \ - $(OOCD_TRACE_FILES) \ %D%/etm_dummy.c \ + %D%/arm_tpiu_swo.c \ %D%/arm_cti.c AVR32_SRC = \ @@ -155,9 +156,16 @@ ESIRISC_SRC = \ %D%/esirisc_jtag.c \ %D%/esirisc_trace.c +ARC_SRC = \ + %D%/arc.c \ + %D%/arc_cmd.c \ + %D%/arc_jtag.c \ + %D%/arc_mem.c + %C%_libtarget_la_SOURCES += \ %D%/algorithm.h \ %D%/arm.h \ + %D%/arm_coresight.h \ %D%/arm_dpm.h \ %D%/arm_jtag.h \ %D%/arm_adi_v5.h \ @@ -165,6 +173,7 @@ ESIRISC_SRC = \ %D%/armv7a_cache_l2x.h \ %D%/armv7a_mmu.h \ %D%/arm_disassembler.h \ + %D%/a64_disassembler.h \ %D%/arm_opcodes.h \ %D%/arm_simulator.h \ %D%/arm_semihosting.h \ @@ -200,6 +209,7 @@ ESIRISC_SRC = \ %D%/etb.h \ %D%/etm.h \ %D%/etm_dummy.h \ + %D%/arm_tpiu_swo.h \ %D%/image.h \ %D%/mips32.h \ %D%/mips64.h \ @@ -209,7 +219,6 @@ ESIRISC_SRC = \ %D%/mips32_pracc.h \ %D%/mips32_dmaacc.h \ %D%/mips64_pracc.h \ - %D%/oocd_trace.h \ %D%/register.h \ %D%/target.h \ %D%/target_type.h \ @@ -242,7 +251,12 @@ ESIRISC_SRC = \ %D%/esirisc.h \ %D%/esirisc_jtag.h \ %D%/esirisc_regs.h \ - %D%/esirisc_trace.h + %D%/esirisc_trace.h \ + %D%/arc.h \ + %D%/arc_cmd.h \ + %D%/arc_jtag.h \ + %D%/arc_mem.h \ + %D%/rtt.h include %D%/openrisc/Makefile.am include %D%/riscv/Makefile.am