X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Faarch64.c;h=ef73afd7e84f4c249f28fe7f1c0ae7a333500e31;hb=d8abda4bd828f40fc76613f4d809d86f4c6f1c97;hp=8ac64eb41df92d4124dc7e056c975469867c6bb2;hpb=d376f7f51831ca8816bb4aca00076b0668462775;p=openocd.git

diff --git a/src/target/aarch64.c b/src/target/aarch64.c
index 8ac64eb41d..ef73afd7e8 100644
--- a/src/target/aarch64.c
+++ b/src/target/aarch64.c
@@ -26,7 +26,7 @@
 #include "register.h"
 #include "target_request.h"
 #include "target_type.h"
-#include "arm_opcodes.h"
+#include "armv8_opcodes.h"
 #include <helper/time_support.h>
 
 static int aarch64_poll(struct target *target);
@@ -43,7 +43,7 @@ static int aarch64_unset_breakpoint(struct target *target,
 static int aarch64_mmu(struct target *target, int *enabled);
 static int aarch64_virt2phys(struct target *target,
 	target_addr_t virt, target_addr_t *phys);
-static int aarch64_read_apb_ab_memory(struct target *target,
+static int aarch64_read_apb_ap_memory(struct target *target,
 	uint64_t address, uint32_t size, uint32_t count, uint8_t *buffer);
 static int aarch64_instr_write_data_r0(struct arm_dpm *dpm,
 	uint32_t opcode, uint32_t data);
@@ -57,11 +57,41 @@ static int aarch64_restore_system_control_reg(struct target *target)
 
 	if (aarch64->system_control_reg != aarch64->system_control_reg_curr) {
 		aarch64->system_control_reg_curr = aarch64->system_control_reg;
-		retval = aarch64_instr_write_data_r0(armv8->arm.dpm,
-						     0xd5181000,
-						     aarch64->system_control_reg);
+		/* LOG_INFO("cp15_control_reg: %8.8" PRIx32, cortex_v8->cp15_control_reg); */
+
+		switch (armv8->arm.core_mode) {
+			case ARMV8_64_EL0T:
+			case ARMV8_64_EL1T:
+			case ARMV8_64_EL1H:
+				retval = armv8->arm.msr(target, 3, /*op 0*/
+						0, 1,	/* op1, op2 */
+						0, 0,	/* CRn, CRm */
+						aarch64->system_control_reg);
+				if (retval != ERROR_OK)
+					return retval;
+			break;
+			case ARMV8_64_EL2T:
+			case ARMV8_64_EL2H:
+				retval = armv8->arm.msr(target, 3, /*op 0*/
+						4, 1,	/* op1, op2 */
+						0, 0,	/* CRn, CRm */
+						aarch64->system_control_reg);
+				if (retval != ERROR_OK)
+					return retval;
+			break;
+			case ARMV8_64_EL3H:
+			case ARMV8_64_EL3T:
+				retval = armv8->arm.msr(target, 3, /*op 0*/
+						6, 1,	/* op1, op2 */
+						0, 0,	/* CRn, CRm */
+						aarch64->system_control_reg);
+				if (retval != ERROR_OK)
+					return retval;
+			break;
+			default:
+				LOG_DEBUG("unknow cpu state 0x%x" PRIx32, armv8->arm.core_state);
+			}
 	}
-
 	return retval;
 }
 
@@ -82,16 +112,45 @@ static int aarch64_mmu_modify(struct target *target, int enable)
 	int retval = ERROR_OK;
 
 	if (enable) {
-		/*  if mmu enabled at target stop and mmu not enable */
+		/*	if mmu enabled at target stop and mmu not enable */
 		if (!(aarch64->system_control_reg & 0x1U)) {
 			LOG_ERROR("trying to enable mmu on target stopped with mmu disable");
 			return ERROR_FAIL;
 		}
 		if (!(aarch64->system_control_reg_curr & 0x1U)) {
 			aarch64->system_control_reg_curr |= 0x1U;
-			retval = aarch64_instr_write_data_r0(armv8->arm.dpm,
-							     0xd5181000,
-							     aarch64->system_control_reg_curr);
+			switch (armv8->arm.core_mode) {
+				case ARMV8_64_EL0T:
+				case ARMV8_64_EL1T:
+				case ARMV8_64_EL1H:
+					retval = armv8->arm.msr(target, 3, /*op 0*/
+							0, 0,	/* op1, op2 */
+							1, 0,	/* CRn, CRm */
+							aarch64->system_control_reg_curr);
+					if (retval != ERROR_OK)
+						return retval;
+				break;
+				case ARMV8_64_EL2T:
+				case ARMV8_64_EL2H:
+					retval = armv8->arm.msr(target, 3, /*op 0*/
+							4, 0,	/* op1, op2 */
+							1, 0,	/* CRn, CRm */
+							aarch64->system_control_reg_curr);
+					if (retval != ERROR_OK)
+						return retval;
+				break;
+				case ARMV8_64_EL3H:
+				case ARMV8_64_EL3T:
+					retval = armv8->arm.msr(target, 3, /*op 0*/
+							6, 0,	/* op1, op2 */
+							1, 0,	/* CRn, CRm */
+							aarch64->system_control_reg_curr);
+					if (retval != ERROR_OK)
+						return retval;
+				break;
+				default:
+					LOG_DEBUG("unknow cpu state 0x%x" PRIx32, armv8->arm.core_state);
+			}
 		}
 	} else {
 		if (aarch64->system_control_reg_curr & 0x4U) {
@@ -103,9 +162,39 @@ static int aarch64_mmu_modify(struct target *target, int enable)
 		}
 		if ((aarch64->system_control_reg_curr & 0x1U)) {
 			aarch64->system_control_reg_curr &= ~0x1U;
-			retval = aarch64_instr_write_data_r0(armv8->arm.dpm,
-							     0xd5181000,
-							     aarch64->system_control_reg_curr);
+			switch (armv8->arm.core_mode) {
+				case ARMV8_64_EL0T:
+				case ARMV8_64_EL1T:
+				case ARMV8_64_EL1H:
+					retval = armv8->arm.msr(target, 3, /*op 0*/
+							0, 0,	/* op1, op2 */
+							1, 0,	/* CRn, CRm */
+							aarch64->system_control_reg_curr);
+					if (retval != ERROR_OK)
+						return retval;
+					break;
+				case ARMV8_64_EL2T:
+				case ARMV8_64_EL2H:
+					retval = armv8->arm.msr(target, 3, /*op 0*/
+							4, 0,	/* op1, op2 */
+							1, 0,	/* CRn, CRm */
+							aarch64->system_control_reg_curr);
+					if (retval != ERROR_OK)
+						return retval;
+					break;
+				case ARMV8_64_EL3H:
+				case ARMV8_64_EL3T:
+					retval = armv8->arm.msr(target, 3, /*op 0*/
+							6, 0,	/* op1, op2 */
+							1, 0,	/* CRn, CRm */
+							aarch64->system_control_reg_curr);
+					if (retval != ERROR_OK)
+						return retval;
+					break;
+				default:
+					LOG_DEBUG("unknow cpu state 0x%x" PRIx32, armv8->arm.core_state);
+					break;
+			}
 		}
 	}
 	return retval;
@@ -125,11 +214,11 @@ static int aarch64_init_debug_access(struct target *target)
 	/* Unlocking the debug registers for modification
 	 * The debugport might be uninitialised so try twice */
 	retval = mem_ap_write_atomic_u32(armv8->debug_ap,
-			     armv8->debug_base + CPUDBG_LOCKACCESS, 0xC5ACCE55);
+			     armv8->debug_base + CPUV8_DBG_LOCKACCESS, 0xC5ACCE55);
 	if (retval != ERROR_OK) {
 		/* try again */
 		retval = mem_ap_write_atomic_u32(armv8->debug_ap,
-			     armv8->debug_base + CPUDBG_LOCKACCESS, 0xC5ACCE55);
+			     armv8->debug_base + CPUV8_DBG_LOCKACCESS, 0xC5ACCE55);
 		if (retval == ERROR_OK)
 			LOG_USER("Locking debug access failed on first, but succeeded on second try.");
 	}
@@ -138,7 +227,7 @@ static int aarch64_init_debug_access(struct target *target)
 	/* Clear Sticky Power Down status Bit in PRSR to enable access to
 	   the registers in the Core Power Domain */
 	retval = mem_ap_read_atomic_u32(armv8->debug_ap,
-			armv8->debug_base + CPUDBG_PRSR, &dummy);
+			armv8->debug_base + CPUV8_DBG_PRSR, &dummy);
 	if (retval != ERROR_OK)
 		return retval;
 
@@ -152,7 +241,7 @@ static int aarch64_init_debug_access(struct target *target)
 
 /* To reduce needless round-trips, pass in a pointer to the current
  * DSCR value.  Initialize it to zero if you just need to know the
- * value on return from this function; or DSCR_INSTR_COMP if you
+ * value on return from this function; or DSCR_ITE if you
  * happen to know that no instruction is pending.
  */
 static int aarch64_exec_opcode(struct target *target,
@@ -167,9 +256,9 @@ static int aarch64_exec_opcode(struct target *target,
 
 	/* Wait for InstrCompl bit to be set */
 	long long then = timeval_ms();
-	while ((dscr & DSCR_INSTR_COMP) == 0) {
+	while ((dscr & DSCR_ITE) == 0) {
 		retval = mem_ap_read_atomic_u32(armv8->debug_ap,
-				armv8->debug_base + CPUDBG_DSCR, &dscr);
+				armv8->debug_base + CPUV8_DBG_DSCR, &dscr);
 		if (retval != ERROR_OK) {
 			LOG_ERROR("Could not read DSCR register, opcode = 0x%08" PRIx32, opcode);
 			return retval;
@@ -181,14 +270,14 @@ static int aarch64_exec_opcode(struct target *target,
 	}
 
 	retval = mem_ap_write_u32(armv8->debug_ap,
-			armv8->debug_base + CPUDBG_ITR, opcode);
+			armv8->debug_base + CPUV8_DBG_ITR, opcode);
 	if (retval != ERROR_OK)
 		return retval;
 
 	then = timeval_ms();
 	do {
 		retval = mem_ap_read_atomic_u32(armv8->debug_ap,
-				armv8->debug_base + CPUDBG_DSCR, &dscr);
+				armv8->debug_base + CPUV8_DBG_DSCR, &dscr);
 		if (retval != ERROR_OK) {
 			LOG_ERROR("Could not read DSCR register");
 			return retval;
@@ -197,7 +286,7 @@ static int aarch64_exec_opcode(struct target *target,
 			LOG_ERROR("Timeout waiting for aarch64_exec_opcode");
 			return ERROR_FAIL;
 		}
-	} while ((dscr & DSCR_INSTR_COMP) == 0);	/* Wait for InstrCompl bit to be set */
+	} while ((dscr & DSCR_ITE) == 0);	/* Wait for InstrCompl bit to be set */
 
 	if (dscr_p)
 		*dscr_p = dscr;
@@ -221,7 +310,7 @@ static int aarch64_dap_write_memap_register_u32(struct target *target,
 /*
  * AARCH64 implementation of Debug Programmer's Model
  *
- * NOTE the invariant:  these routines return with DSCR_INSTR_COMP set,
+ * NOTE the invariant:  these routines return with DSCR_ITE set,
  * so there's no need to poll for it before executing an instruction.
  *
  * NOTE that in several of these cases the "stall" mode might be useful.
@@ -234,29 +323,29 @@ static inline struct aarch64_common *dpm_to_a8(struct arm_dpm *dpm)
 	return container_of(dpm, struct aarch64_common, armv8_common.dpm);
 }
 
-static int aarch64_write_dcc(struct aarch64_common *a8, uint32_t data)
+static int aarch64_write_dcc(struct armv8_common *armv8, uint32_t data)
 {
 	LOG_DEBUG("write DCC 0x%08" PRIx32, data);
-	return mem_ap_write_u32(a8->armv8_common.debug_ap,
-				a8->armv8_common.debug_base + CPUDBG_DTRRX, data);
+	return mem_ap_write_u32(armv8->debug_ap,
+				armv8->debug_base + CPUV8_DBG_DTRRX, data);
 }
 
-static int aarch64_write_dcc_64(struct aarch64_common *a8, uint64_t data)
+static int aarch64_write_dcc_64(struct armv8_common *armv8, uint64_t data)
 {
 	int ret;
-	LOG_DEBUG("write DCC 0x%08" PRIx32, (unsigned)data);
-	LOG_DEBUG("write DCC 0x%08" PRIx32, (unsigned)(data >> 32));
-	ret = mem_ap_write_u32(a8->armv8_common.debug_ap,
-			       a8->armv8_common.debug_base + CPUDBG_DTRRX, data);
-	ret += mem_ap_write_u32(a8->armv8_common.debug_ap,
-				a8->armv8_common.debug_base + CPUDBG_DTRTX, data >> 32);
+	LOG_DEBUG("write DCC Low word0x%08" PRIx32, (unsigned)data);
+	LOG_DEBUG("write DCC High word 0x%08" PRIx32, (unsigned)(data >> 32));
+	ret = mem_ap_write_u32(armv8->debug_ap,
+			       armv8->debug_base + CPUV8_DBG_DTRRX, data);
+	ret += mem_ap_write_u32(armv8->debug_ap,
+				armv8->debug_base + CPUV8_DBG_DTRTX, data >> 32);
 	return ret;
 }
 
-static int aarch64_read_dcc(struct aarch64_common *a8, uint32_t *data,
+static int aarch64_read_dcc(struct armv8_common *armv8, uint32_t *data,
 	uint32_t *dscr_p)
 {
-	uint32_t dscr = DSCR_INSTR_COMP;
+	uint32_t dscr = DSCR_ITE;
 	int retval;
 
 	if (dscr_p)
@@ -265,8 +354,8 @@ static int aarch64_read_dcc(struct aarch64_common *a8, uint32_t *data,
 	/* Wait for DTRRXfull */
 	long long then = timeval_ms();
 	while ((dscr & DSCR_DTR_TX_FULL) == 0) {
-		retval = mem_ap_read_atomic_u32(a8->armv8_common.debug_ap,
-				a8->armv8_common.debug_base + CPUDBG_DSCR,
+		retval = mem_ap_read_atomic_u32(armv8->debug_ap,
+				armv8->debug_base + CPUV8_DBG_DSCR,
 				&dscr);
 		if (retval != ERROR_OK)
 			return retval;
@@ -276,8 +365,8 @@ static int aarch64_read_dcc(struct aarch64_common *a8, uint32_t *data,
 		}
 	}
 
-	retval = mem_ap_read_atomic_u32(a8->armv8_common.debug_ap,
-					    a8->armv8_common.debug_base + CPUDBG_DTRTX,
+	retval = mem_ap_read_atomic_u32(armv8->debug_ap,
+					    armv8->debug_base + CPUV8_DBG_DTRTX,
 					    data);
 	if (retval != ERROR_OK)
 		return retval;
@@ -288,10 +377,11 @@ static int aarch64_read_dcc(struct aarch64_common *a8, uint32_t *data,
 
 	return retval;
 }
-static int aarch64_read_dcc_64(struct aarch64_common *a8, uint64_t *data,
+
+static int aarch64_read_dcc_64(struct armv8_common *armv8, uint64_t *data,
 	uint32_t *dscr_p)
 {
-	uint32_t dscr = DSCR_INSTR_COMP;
+	uint32_t dscr = DSCR_ITE;
 	uint32_t higher;
 	int retval;
 
@@ -301,8 +391,8 @@ static int aarch64_read_dcc_64(struct aarch64_common *a8, uint64_t *data,
 	/* Wait for DTRRXfull */
 	long long then = timeval_ms();
 	while ((dscr & DSCR_DTR_TX_FULL) == 0) {
-		retval = mem_ap_read_atomic_u32(a8->armv8_common.debug_ap,
-				a8->armv8_common.debug_base + CPUDBG_DSCR,
+		retval = mem_ap_read_atomic_u32(armv8->debug_ap,
+				armv8->debug_base + CPUV8_DBG_DSCR,
 				&dscr);
 		if (retval != ERROR_OK)
 			return retval;
@@ -312,14 +402,14 @@ static int aarch64_read_dcc_64(struct aarch64_common *a8, uint64_t *data,
 		}
 	}
 
-	retval = mem_ap_read_atomic_u32(a8->armv8_common.debug_ap,
-					    a8->armv8_common.debug_base + CPUDBG_DTRTX,
+	retval = mem_ap_read_atomic_u32(armv8->debug_ap,
+					    armv8->debug_base + CPUV8_DBG_DTRTX,
 					    (uint32_t *)data);
 	if (retval != ERROR_OK)
 		return retval;
 
-	retval = mem_ap_read_atomic_u32(a8->armv8_common.debug_ap,
-					    a8->armv8_common.debug_base + CPUDBG_DTRRX,
+	retval = mem_ap_read_atomic_u32(armv8->debug_ap,
+					    armv8->debug_base + CPUV8_DBG_DTRRX,
 					    &higher);
 	if (retval != ERROR_OK)
 		return retval;
@@ -343,11 +433,11 @@ static int aarch64_dpm_prepare(struct arm_dpm *dpm)
 	long long then = timeval_ms();
 	for (;; ) {
 		retval = mem_ap_read_atomic_u32(a8->armv8_common.debug_ap,
-				a8->armv8_common.debug_base + CPUDBG_DSCR,
+				a8->armv8_common.debug_base + CPUV8_DBG_DSCR,
 				&dscr);
 		if (retval != ERROR_OK)
 			return retval;
-		if ((dscr & DSCR_INSTR_COMP) != 0)
+		if ((dscr & DSCR_ITE) != 0)
 			break;
 		if (timeval_ms() > then + 1000) {
 			LOG_ERROR("Timeout waiting for dpm prepare");
@@ -359,10 +449,14 @@ static int aarch64_dpm_prepare(struct arm_dpm *dpm)
 	if (dscr & DSCR_DTR_RX_FULL) {
 		LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32, dscr);
 		/* Clear DCCRX */
-		retval = aarch64_exec_opcode(
-				a8->armv8_common.arm.target,
-				0xd5130400,
-				&dscr);
+		retval = mem_ap_read_u32(a8->armv8_common.debug_ap,
+			a8->armv8_common.debug_base + CPUV8_DBG_DTRRX, &dscr);
+		if (retval != ERROR_OK)
+			return retval;
+
+		/* Clear sticky error */
+		retval = mem_ap_write_u32(a8->armv8_common.debug_ap,
+			a8->armv8_common.debug_base + CPUV8_DBG_DRCR, DRCR_CSE);
 		if (retval != ERROR_OK)
 			return retval;
 	}
@@ -376,14 +470,26 @@ static int aarch64_dpm_finish(struct arm_dpm *dpm)
 	return ERROR_OK;
 }
 
+static int aarch64_instr_execute(struct arm_dpm *dpm,
+	uint32_t opcode)
+{
+	struct aarch64_common *a8 = dpm_to_a8(dpm);
+	uint32_t dscr = DSCR_ITE;
+
+	return aarch64_exec_opcode(
+			a8->armv8_common.arm.target,
+			opcode,
+			&dscr);
+}
+
 static int aarch64_instr_write_data_dcc(struct arm_dpm *dpm,
 	uint32_t opcode, uint32_t data)
 {
 	struct aarch64_common *a8 = dpm_to_a8(dpm);
 	int retval;
-	uint32_t dscr = DSCR_INSTR_COMP;
+	uint32_t dscr = DSCR_ITE;
 
-	retval = aarch64_write_dcc(a8, data);
+	retval = aarch64_write_dcc(&a8->armv8_common, data);
 	if (retval != ERROR_OK)
 		return retval;
 
@@ -398,9 +504,9 @@ static int aarch64_instr_write_data_dcc_64(struct arm_dpm *dpm,
 {
 	struct aarch64_common *a8 = dpm_to_a8(dpm);
 	int retval;
-	uint32_t dscr = DSCR_INSTR_COMP;
+	uint32_t dscr = DSCR_ITE;
 
-	retval = aarch64_write_dcc_64(a8, data);
+	retval = aarch64_write_dcc_64(&a8->armv8_common, data);
 	if (retval != ERROR_OK)
 		return retval;
 
@@ -414,16 +520,16 @@ static int aarch64_instr_write_data_r0(struct arm_dpm *dpm,
 	uint32_t opcode, uint32_t data)
 {
 	struct aarch64_common *a8 = dpm_to_a8(dpm);
-	uint32_t dscr = DSCR_INSTR_COMP;
+	uint32_t dscr = DSCR_ITE;
 	int retval;
 
-	retval = aarch64_write_dcc(a8, data);
+	retval = aarch64_write_dcc(&a8->armv8_common, data);
 	if (retval != ERROR_OK)
 		return retval;
 
 	retval = aarch64_exec_opcode(
 			a8->armv8_common.arm.target,
-			0xd5330500,
+			ARMV8_MRS(SYSTEM_DBG_DTRRX_EL0, 0),
 			&dscr);
 	if (retval != ERROR_OK)
 		return retval;
@@ -441,16 +547,16 @@ static int aarch64_instr_write_data_r0_64(struct arm_dpm *dpm,
 	uint32_t opcode, uint64_t data)
 {
 	struct aarch64_common *a8 = dpm_to_a8(dpm);
-	uint32_t dscr = DSCR_INSTR_COMP;
+	uint32_t dscr = DSCR_ITE;
 	int retval;
 
-	retval = aarch64_write_dcc_64(a8, data);
+	retval = aarch64_write_dcc_64(&a8->armv8_common, data);
 	if (retval != ERROR_OK)
 		return retval;
 
 	retval = aarch64_exec_opcode(
 			a8->armv8_common.arm.target,
-			0xd5330400,
+			ARMV8_MRS(SYSTEM_DBG_DBGDTR_EL0, 0),
 			&dscr);
 	if (retval != ERROR_OK)
 		return retval;
@@ -467,11 +573,11 @@ static int aarch64_instr_write_data_r0_64(struct arm_dpm *dpm,
 static int aarch64_instr_cpsr_sync(struct arm_dpm *dpm)
 {
 	struct target *target = dpm->arm->target;
-	uint32_t dscr = DSCR_INSTR_COMP;
+	uint32_t dscr = DSCR_ITE;
 
 	/* "Prefetch flush" after modifying execution status in CPSR */
 	return aarch64_exec_opcode(target,
-			ARMV4_5_MCR(15, 0, 0, 7, 5, 4),
+			DSB_SY,
 			&dscr);
 }
 
@@ -480,7 +586,7 @@ static int aarch64_instr_read_data_dcc(struct arm_dpm *dpm,
 {
 	struct aarch64_common *a8 = dpm_to_a8(dpm);
 	int retval;
-	uint32_t dscr = DSCR_INSTR_COMP;
+	uint32_t dscr = DSCR_ITE;
 
 	/* the opcode, writing data to DCC */
 	retval = aarch64_exec_opcode(
@@ -490,7 +596,7 @@ static int aarch64_instr_read_data_dcc(struct arm_dpm *dpm,
 	if (retval != ERROR_OK)
 		return retval;
 
-	return aarch64_read_dcc(a8, data, &dscr);
+	return aarch64_read_dcc(&a8->armv8_common, data, &dscr);
 }
 
 static int aarch64_instr_read_data_dcc_64(struct arm_dpm *dpm,
@@ -498,7 +604,7 @@ static int aarch64_instr_read_data_dcc_64(struct arm_dpm *dpm,
 {
 	struct aarch64_common *a8 = dpm_to_a8(dpm);
 	int retval;
-	uint32_t dscr = DSCR_INSTR_COMP;
+	uint32_t dscr = DSCR_ITE;
 
 	/* the opcode, writing data to DCC */
 	retval = aarch64_exec_opcode(
@@ -508,14 +614,14 @@ static int aarch64_instr_read_data_dcc_64(struct arm_dpm *dpm,
 	if (retval != ERROR_OK)
 		return retval;
 
-	return aarch64_read_dcc_64(a8, data, &dscr);
+	return aarch64_read_dcc_64(&a8->armv8_common, data, &dscr);
 }
 
 static int aarch64_instr_read_data_r0(struct arm_dpm *dpm,
 	uint32_t opcode, uint32_t *data)
 {
 	struct aarch64_common *a8 = dpm_to_a8(dpm);
-	uint32_t dscr = DSCR_INSTR_COMP;
+	uint32_t dscr = DSCR_ITE;
 	int retval;
 
 	/* the opcode, writing data to R0 */
@@ -529,19 +635,19 @@ static int aarch64_instr_read_data_r0(struct arm_dpm *dpm,
 	/* write R0 to DCC */
 	retval = aarch64_exec_opcode(
 			a8->armv8_common.arm.target,
-			0xd5130400,  /* msr dbgdtr_el0, x0 */
+			ARMV8_MSR_GP(SYSTEM_DBG_DTRTX_EL0, 0),  /* msr dbgdtr_el0, x0 */
 			&dscr);
 	if (retval != ERROR_OK)
 		return retval;
 
-	return aarch64_read_dcc(a8, data, &dscr);
+	return aarch64_read_dcc(&a8->armv8_common, data, &dscr);
 }
 
 static int aarch64_instr_read_data_r0_64(struct arm_dpm *dpm,
 	uint32_t opcode, uint64_t *data)
 {
 	struct aarch64_common *a8 = dpm_to_a8(dpm);
-	uint32_t dscr = DSCR_INSTR_COMP;
+	uint32_t dscr = DSCR_ITE;
 	int retval;
 
 	/* the opcode, writing data to R0 */
@@ -555,12 +661,12 @@ static int aarch64_instr_read_data_r0_64(struct arm_dpm *dpm,
 	/* write R0 to DCC */
 	retval = aarch64_exec_opcode(
 			a8->armv8_common.arm.target,
-			0xd5130400,  /* msr dbgdtr_el0, x0 */
+			ARMV8_MSR_GP(SYSTEM_DBG_DBGDTR_EL0, 0),  /* msr dbgdtr_el0, x0 */
 			&dscr);
 	if (retval != ERROR_OK)
 		return retval;
 
-	return aarch64_read_dcc_64(a8, data, &dscr);
+	return aarch64_read_dcc_64(&a8->armv8_common, data, &dscr);
 }
 
 static int aarch64_bpwp_enable(struct arm_dpm *dpm, unsigned index_t,
@@ -573,12 +679,12 @@ static int aarch64_bpwp_enable(struct arm_dpm *dpm, unsigned index_t,
 
 	switch (index_t) {
 		case 0 ... 15:	/* breakpoints */
-			vr += CPUDBG_BVR_BASE;
-			cr += CPUDBG_BCR_BASE;
+			vr += CPUV8_DBG_BVR_BASE;
+			cr += CPUV8_DBG_BCR_BASE;
 			break;
 		case 16 ... 31:	/* watchpoints */
-			vr += CPUDBG_WVR_BASE;
-			cr += CPUDBG_WCR_BASE;
+			vr += CPUV8_DBG_WVR_BASE;
+			cr += CPUV8_DBG_WCR_BASE;
 			index_t -= 16;
 			break;
 		default:
@@ -604,15 +710,15 @@ static int aarch64_bpwp_disable(struct arm_dpm *dpm, unsigned index_t)
 	return ERROR_OK;
 
 #if 0
-	struct aarch64_common *a8 = dpm_to_a8(dpm);
+	struct aarch64_common *a = dpm_to_a8(dpm);
 	uint32_t cr;
 
 	switch (index_t) {
 		case 0 ... 15:
-			cr = a8->armv8_common.debug_base + CPUDBG_BCR_BASE;
+			cr = a->armv8_common.debug_base + CPUV8_DBG_BCR_BASE;
 			break;
 		case 16 ... 31:
-			cr = a8->armv8_common.debug_base + CPUDBG_WCR_BASE;
+			cr = a->armv8_common.debug_base + CPUV8_DBG_WCR_BASE;
 			index_t -= 16;
 			break;
 		default:
@@ -620,7 +726,7 @@ static int aarch64_bpwp_disable(struct arm_dpm *dpm, unsigned index_t)
 	}
 	cr += 4 * index_t;
 
-	LOG_DEBUG("A8: bpwp disable, cr %08x", (unsigned) cr);
+	LOG_DEBUG("A: bpwp disable, cr %08x", (unsigned) cr);
 
 	/* clear control register */
 	return aarch64_dap_write_memap_register_u32(dpm->arm->target, cr, 0);
@@ -638,6 +744,7 @@ static int aarch64_dpm_setup(struct aarch64_common *a8, uint32_t debug)
 	dpm->prepare = aarch64_dpm_prepare;
 	dpm->finish = aarch64_dpm_finish;
 
+	dpm->instr_execute = aarch64_instr_execute;
 	dpm->instr_write_data_dcc = aarch64_instr_write_data_dcc;
 	dpm->instr_write_data_dcc_64 = aarch64_instr_write_data_dcc_64;
 	dpm->instr_write_data_r0 = aarch64_instr_write_data_r0;
@@ -654,9 +761,9 @@ static int aarch64_dpm_setup(struct aarch64_common *a8, uint32_t debug)
 	dpm->bpwp_enable = aarch64_bpwp_enable;
 	dpm->bpwp_disable = aarch64_bpwp_disable;
 
-	retval = arm_dpm_setup(dpm);
+	retval = armv8_dpm_setup(dpm);
 	if (retval == ERROR_OK)
-		retval = arm_dpm_initialize(dpm);
+		retval = armv8_dpm_initialize(dpm);
 
 	return retval;
 }
@@ -726,7 +833,7 @@ static int aarch64_poll(struct target *target)
 		return retval;
 	}
 	retval = mem_ap_read_atomic_u32(armv8->debug_ap,
-			armv8->debug_base + CPUDBG_DSCR, &dscr);
+			armv8->debug_base + CPUV8_DBG_DSCR, &dscr);
 	if (retval != ERROR_OK)
 		return retval;
 	aarch64->cpudbg_dscr = dscr;
@@ -782,68 +889,58 @@ static int aarch64_halt(struct target *target)
 	uint32_t dscr;
 	struct armv8_common *armv8 = target_to_armv8(target);
 
-	retval = mem_ap_read_atomic_u32(armv8->debug_ap,
-			armv8->debug_base + 0x10000 + 0, &dscr);
-	retval = mem_ap_write_atomic_u32(armv8->debug_ap,
-			armv8->debug_base + 0x10000 + 0, 1);
-	retval = mem_ap_read_atomic_u32(armv8->debug_ap,
-			armv8->debug_base + 0x10000 + 0, &dscr);
-
-	retval = mem_ap_read_atomic_u32(armv8->debug_ap,
-			armv8->debug_base + 0x10000 + 0x140, &dscr);
+	/* enable CTI*/
 	retval = mem_ap_write_atomic_u32(armv8->debug_ap,
-			armv8->debug_base + 0x10000 + 0x140, 6);
-	retval = mem_ap_read_atomic_u32(armv8->debug_ap,
-			armv8->debug_base + 0x10000 + 0x140, &dscr);
+			armv8->cti_base + CTI_CTR, 1);
+	if (retval != ERROR_OK)
+		return retval;
 
-	retval = mem_ap_read_atomic_u32(armv8->debug_ap,
-			armv8->debug_base + 0x10000 + 0xa0, &dscr);
 	retval = mem_ap_write_atomic_u32(armv8->debug_ap,
-			armv8->debug_base + 0x10000 + 0xa0, 5);
-	retval = mem_ap_read_atomic_u32(armv8->debug_ap,
-			armv8->debug_base + 0x10000 + 0xa0, &dscr);
+			armv8->cti_base + CTI_GATE, 3);
+	if (retval != ERROR_OK)
+		return retval;
 
-	retval = mem_ap_read_atomic_u32(armv8->debug_ap,
-			armv8->debug_base + 0x10000 + 0xa4, &dscr);
 	retval = mem_ap_write_atomic_u32(armv8->debug_ap,
-			armv8->debug_base + 0x10000 + 0xa4, 2);
-	retval = mem_ap_read_atomic_u32(armv8->debug_ap,
-			armv8->debug_base + 0x10000 + 0xa4, &dscr);
+			armv8->cti_base + CTI_OUTEN0, 1);
+	if (retval != ERROR_OK)
+		return retval;
 
-	retval = mem_ap_read_atomic_u32(armv8->debug_ap,
-			armv8->debug_base + 0x10000 + 0x20, &dscr);
 	retval = mem_ap_write_atomic_u32(armv8->debug_ap,
-			armv8->debug_base + 0x10000 + 0x20, 4);
-	retval = mem_ap_read_atomic_u32(armv8->debug_ap,
-			armv8->debug_base + 0x10000 + 0x20, &dscr);
+			armv8->cti_base + CTI_OUTEN1, 2);
+	if (retval != ERROR_OK)
+		return retval;
 
 	/*
-	 * enter halting debug mode
+	 * add HDE in halting debug mode
 	 */
 	retval = mem_ap_read_atomic_u32(armv8->debug_ap,
-			armv8->debug_base + CPUDBG_DSCR, &dscr);
+			armv8->debug_base + CPUV8_DBG_DSCR, &dscr);
 	if (retval != ERROR_OK)
 		return retval;
 
-#	/* STATUS */
-	retval = mem_ap_read_atomic_u32(armv8->debug_ap,
-			armv8->debug_base + 0x10000 + 0x134, &dscr);
+	retval = mem_ap_write_atomic_u32(armv8->debug_ap,
+			armv8->debug_base + CPUV8_DBG_DSCR, dscr | DSCR_HDE);
+	if (retval != ERROR_OK)
+		return retval;
 
-	retval = mem_ap_read_atomic_u32(armv8->debug_ap,
-			armv8->debug_base + 0x10000 + 0x1c, &dscr);
 	retval = mem_ap_write_atomic_u32(armv8->debug_ap,
-			armv8->debug_base + 0x10000 + 0x1c, 1);
-	retval = mem_ap_read_atomic_u32(armv8->debug_ap,
-			armv8->debug_base + 0x10000 + 0x1c, &dscr);
+			armv8->cti_base + CTI_APPPULSE, 1);
+	if (retval != ERROR_OK)
+		return retval;
+
+	retval = mem_ap_write_atomic_u32(armv8->debug_ap,
+			armv8->cti_base + CTI_INACK, 1);
+	if (retval != ERROR_OK)
+		return retval;
 
 
 	long long then = timeval_ms();
 	for (;; ) {
 		retval = mem_ap_read_atomic_u32(armv8->debug_ap,
-				armv8->debug_base + CPUDBG_DSCR, &dscr);
+				armv8->debug_base + CPUV8_DBG_DSCR, &dscr);
 		if (retval != ERROR_OK)
 			return retval;
-		if ((dscr & DSCR_CORE_HALTED) != 0)
+		if ((dscr & DSCRV8_HALT_MASK) != 0)
 			break;
 		if (timeval_ms() > then + 1000) {
 			LOG_ERROR("Timeout waiting for halt");
@@ -879,6 +976,8 @@ static int aarch64_internal_restore(struct target *target, int current,
 	 */
 	switch (arm->core_state) {
 		case ARM_STATE_ARM:
+			resume_pc &= 0xFFFFFFFC;
+			break;
 		case ARM_STATE_AARCH64:
 			resume_pc &= 0xFFFFFFFFFFFFFFFC;
 			break;
@@ -897,10 +996,8 @@ static int aarch64_internal_restore(struct target *target, int current,
 	buf_set_u64(arm->pc->value, 0, 64, resume_pc);
 	arm->pc->dirty = 1;
 	arm->pc->valid = 1;
-#if 0
-	/* restore dpm_mode at system halt */
-	dpm_modeswitch(&armv8->dpm, ARM_MODE_ANY);
-#endif
+	dpmv8_modeswitch(&armv8->dpm, ARM_MODE_ANY);
+
 	/* called it now before restoring context because it uses cpu
 	 * register r0 for restoring system control register */
 	retval = aarch64_restore_system_control_reg(target);
@@ -947,41 +1044,25 @@ static int aarch64_internal_restart(struct target *target)
 	 */
 
 	retval = mem_ap_read_atomic_u32(armv8->debug_ap,
-			armv8->debug_base + CPUDBG_DSCR, &dscr);
+			armv8->debug_base + CPUV8_DBG_DSCR, &dscr);
 	if (retval != ERROR_OK)
 		return retval;
 
-	if ((dscr & DSCR_INSTR_COMP) == 0)
+	if ((dscr & DSCR_ITE) == 0)
 		LOG_ERROR("DSCR InstrCompl must be set before leaving debug!");
 
 	retval = mem_ap_write_atomic_u32(armv8->debug_ap,
-			armv8->debug_base + CPUDBG_DSCR, dscr & ~DSCR_ITR_EN);
-	if (retval != ERROR_OK)
-		return retval;
-
-	retval = mem_ap_write_atomic_u32(armv8->debug_ap,
-			armv8->debug_base + CPUDBG_DRCR, DRCR_RESTART |
-			DRCR_CLEAR_EXCEPTIONS);
-	if (retval != ERROR_OK)
-		return retval;
-
-	retval = mem_ap_write_atomic_u32(armv8->debug_ap,
-			armv8->debug_base + 0x10000 + 0x10, 1);
-	if (retval != ERROR_OK)
-		return retval;
-
-	retval = mem_ap_write_atomic_u32(armv8->debug_ap,
-			armv8->debug_base + 0x10000 + 0x1c, 2);
+			armv8->cti_base + CTI_APPPULSE, 2);
 	if (retval != ERROR_OK)
 		return retval;
 
 	long long then = timeval_ms();
 	for (;; ) {
 		retval = mem_ap_read_atomic_u32(armv8->debug_ap,
-				armv8->debug_base + CPUDBG_DSCR, &dscr);
+				armv8->debug_base + CPUV8_DBG_DSCR, &dscr);
 		if (retval != ERROR_OK)
 			return retval;
-		if ((dscr & DSCR_CORE_RESTARTED) != 0)
+		if ((dscr & DSCR_HDE) != 0)
 			break;
 		if (timeval_ms() > then + 1000) {
 			LOG_ERROR("Timeout waiting for resume");
@@ -1023,12 +1104,7 @@ static int aarch64_resume(struct target *target, int current,
 	target_addr_t address, int handle_breakpoints, int debug_execution)
 {
 	int retval = 0;
-	uint64_t resume_addr;
-
-	if (address) {
-		LOG_DEBUG("resuming with custom address not supported");
-		return ERROR_FAIL;
-	}
+	uint64_t addr = address;
 
 	/* dummy resume for smp toggle in order to reduce gdb impact  */
 	if ((target->smp) && (target->gdb_service->core[1] != -1)) {
@@ -1039,7 +1115,8 @@ static int aarch64_resume(struct target *target, int current,
 		target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
 		return 0;
 	}
-	aarch64_internal_restore(target, current, &resume_addr, handle_breakpoints, debug_execution);
+	aarch64_internal_restore(target, current, &addr, handle_breakpoints,
+				 debug_execution);
 	if (target->smp) {
 		target->gdb_service->core[0] = -1;
 		retval = aarch64_restore_smp(target, handle_breakpoints);
@@ -1051,11 +1128,11 @@ static int aarch64_resume(struct target *target, int current,
 	if (!debug_execution) {
 		target->state = TARGET_RUNNING;
 		target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
-		LOG_DEBUG("target resumed at 0x%" PRIx64, resume_addr);
+		LOG_DEBUG("target resumed at 0x%" PRIx64, addr);
 	} else {
 		target->state = TARGET_DEBUG_RUNNING;
 		target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
-		LOG_DEBUG("target debug resumed at 0x%" PRIx64, resume_addr);
+		LOG_DEBUG("target debug resumed at 0x%" PRIx64, addr);
 	}
 
 	return ERROR_OK;
@@ -1063,47 +1140,48 @@ static int aarch64_resume(struct target *target, int current,
 
 static int aarch64_debug_entry(struct target *target)
 {
-	uint32_t dscr;
 	int retval = ERROR_OK;
 	struct aarch64_common *aarch64 = target_to_aarch64(target);
 	struct armv8_common *armv8 = target_to_armv8(target);
 
 	LOG_DEBUG("dscr = 0x%08" PRIx32, aarch64->cpudbg_dscr);
 
-	/* REVISIT surely we should not re-read DSCR !! */
-	retval = mem_ap_read_atomic_u32(armv8->debug_ap,
-			armv8->debug_base + CPUDBG_DSCR, &dscr);
-	if (retval != ERROR_OK)
-		return retval;
-
 	/* REVISIT see A8 TRM 12.11.4 steps 2..3 -- make sure that any
 	 * imprecise data aborts get discarded by issuing a Data
 	 * Synchronization Barrier:  ARMV4_5_MCR(15, 0, 0, 7, 10, 4).
 	 */
 
-	/* Enable the ITR execution once we are in debug mode */
-	dscr |= DSCR_ITR_EN;
+	/* make sure to clear all sticky errors */
 	retval = mem_ap_write_atomic_u32(armv8->debug_ap,
-			armv8->debug_base + CPUDBG_DSCR, dscr);
+			armv8->debug_base + CPUV8_DBG_DRCR, DRCR_CSE);
 	if (retval != ERROR_OK)
 		return retval;
 
 	/* Examine debug reason */
-	arm_dpm_report_dscr(&armv8->dpm, aarch64->cpudbg_dscr);
+	armv8_dpm_report_dscr(&armv8->dpm, aarch64->cpudbg_dscr);
 
 	/* save address of instruction that triggered the watchpoint? */
 	if (target->debug_reason == DBG_REASON_WATCHPOINT) {
-		uint32_t wfar;
+		uint32_t tmp;
+		uint64_t wfar = 0;
 
 		retval = mem_ap_read_atomic_u32(armv8->debug_ap,
-				armv8->debug_base + CPUDBG_WFAR,
-				&wfar);
+				armv8->debug_base + CPUV8_DBG_WFAR1,
+				&tmp);
+		if (retval != ERROR_OK)
+			return retval;
+		wfar = tmp;
+		wfar = (wfar << 32);
+		retval = mem_ap_read_atomic_u32(armv8->debug_ap,
+				armv8->debug_base + CPUV8_DBG_WFAR0,
+				&tmp);
 		if (retval != ERROR_OK)
 			return retval;
-		arm_dpm_report_wfar(&armv8->dpm, wfar);
+		wfar |= tmp;
+		armv8_dpm_report_wfar(&armv8->dpm, wfar);
 	}
 
-	retval = arm_dpm_read_current_registers_64(&armv8->dpm);
+	retval = armv8_dpm_read_current_registers(&armv8->dpm);
 
 	if (armv8->post_debug_entry) {
 		retval = armv8->post_debug_entry(target);
@@ -1118,31 +1196,57 @@ static int aarch64_post_debug_entry(struct target *target)
 {
 	struct aarch64_common *aarch64 = target_to_aarch64(target);
 	struct armv8_common *armv8 = &aarch64->armv8_common;
-	struct armv8_mmu_common *armv8_mmu = &armv8->armv8_mmu;
-	uint32_t sctlr_el1 = 0;
 	int retval;
 
 	mem_ap_write_atomic_u32(armv8->debug_ap,
-				armv8->debug_base + CPUDBG_DRCR, 1<<2);
-	retval = aarch64_instr_read_data_r0(armv8->arm.dpm,
-					    0xd5381000, &sctlr_el1);
-	if (retval != ERROR_OK)
-		return retval;
-
-	LOG_DEBUG("sctlr_el1 = %#8.8x", sctlr_el1);
-	aarch64->system_control_reg = sctlr_el1;
-	aarch64->system_control_reg_curr = sctlr_el1;
-	aarch64->curr_mode = armv8->arm.core_mode;
-
-	armv8_mmu->mmu_enabled = sctlr_el1 & 0x1U ? 1 : 0;
-	armv8_mmu->armv8_cache.d_u_cache_enabled = sctlr_el1 & 0x4U ? 1 : 0;
-	armv8_mmu->armv8_cache.i_cache_enabled = sctlr_el1 & 0x1000U ? 1 : 0;
+				    armv8->debug_base + CPUV8_DBG_DRCR, 1<<2);
+	switch (armv8->arm.core_mode) {
+		case ARMV8_64_EL0T:
+		case ARMV8_64_EL1T:
+		case ARMV8_64_EL1H:
+			retval = armv8->arm.mrs(target, 3, /*op 0*/
+					0, 0,	/* op1, op2 */
+					1, 0,	/* CRn, CRm */
+					&aarch64->system_control_reg);
+			if (retval != ERROR_OK)
+				return retval;
+		break;
+		case ARMV8_64_EL2T:
+		case ARMV8_64_EL2H:
+			retval = armv8->arm.mrs(target, 3, /*op 0*/
+					4, 0,	/* op1, op2 */
+					1, 0,	/* CRn, CRm */
+					&aarch64->system_control_reg);
+			if (retval != ERROR_OK)
+				return retval;
+		break;
+		case ARMV8_64_EL3H:
+		case ARMV8_64_EL3T:
+			retval = armv8->arm.mrs(target, 3, /*op 0*/
+					6, 0,	/* op1, op2 */
+					1, 0,	/* CRn, CRm */
+					&aarch64->system_control_reg);
+			if (retval != ERROR_OK)
+				return retval;
+		break;
+		default:
+			LOG_DEBUG("unknow cpu state 0x%x" PRIx32, armv8->arm.core_state);
+	}
+	LOG_DEBUG("System_register: %8.8" PRIx32, aarch64->system_control_reg);
+	aarch64->system_control_reg_curr = aarch64->system_control_reg;
 
 #if 0
 	if (armv8->armv8_mmu.armv8_cache.ctype == -1)
 		armv8_identify_cache(target);
 #endif
 
+	armv8->armv8_mmu.mmu_enabled =
+			(aarch64->system_control_reg & 0x1U) ? 1 : 0;
+	armv8->armv8_mmu.armv8_cache.d_u_cache_enabled =
+		(aarch64->system_control_reg & 0x4U) ? 1 : 0;
+	armv8->armv8_mmu.armv8_cache.i_cache_enabled =
+		(aarch64->system_control_reg & 0x1000U) ? 1 : 0;
+	aarch64->curr_mode = armv8->arm.core_mode;
 	return ERROR_OK;
 }
 
@@ -1150,52 +1254,34 @@ static int aarch64_step(struct target *target, int current, target_addr_t addres
 	int handle_breakpoints)
 {
 	struct armv8_common *armv8 = target_to_armv8(target);
-	struct arm *arm = &armv8->arm;
-	struct breakpoint *breakpoint = NULL;
-	struct breakpoint stepbreakpoint;
-	struct reg *r;
 	int retval;
+	uint32_t tmp;
 
 	if (target->state != TARGET_HALTED) {
 		LOG_WARNING("target not halted");
 		return ERROR_TARGET_NOT_HALTED;
 	}
 
-	/* current = 1: continue on current pc, otherwise continue at <address> */
-	r = arm->pc;
-	if (!current)
-		buf_set_u64(r->value, 0, 64, address);
-	else
-		address = buf_get_u64(r->value, 0, 64);
-
-	/* The front-end may request us not to handle breakpoints.
-	 * But since Cortex-A8 uses breakpoint for single step,
-	 * we MUST handle breakpoints.
-	 */
-	handle_breakpoints = 1;
-	if (handle_breakpoints) {
-		breakpoint = breakpoint_find(target, address);
-		if (breakpoint)
-			aarch64_unset_breakpoint(target, breakpoint);
-	}
-
-	/* Setup single step breakpoint */
-	stepbreakpoint.address = address;
-	stepbreakpoint.length = 4;
-	stepbreakpoint.type = BKPT_HARD;
-	stepbreakpoint.set = 0;
+	retval = mem_ap_read_atomic_u32(armv8->debug_ap,
+			armv8->debug_base + CPUV8_DBG_EDECR, &tmp);
+	if (retval != ERROR_OK)
+		return retval;
 
-	/* Break on IVA mismatch */
-	aarch64_set_breakpoint(target, &stepbreakpoint, 0x04);
+	retval = mem_ap_write_atomic_u32(armv8->debug_ap,
+			armv8->debug_base + CPUV8_DBG_EDECR, (tmp|0x4));
+	if (retval != ERROR_OK)
+		return retval;
 
 	target->debug_reason = DBG_REASON_SINGLESTEP;
-
 	retval = aarch64_resume(target, 1, address, 0, 0);
 	if (retval != ERROR_OK)
 		return retval;
 
 	long long then = timeval_ms();
 	while (target->state != TARGET_HALTED) {
+		mem_ap_read_atomic_u32(armv8->debug_ap,
+			armv8->debug_base + CPUV8_DBG_EDESR, &tmp);
+		LOG_DEBUG("DESR = %#x", tmp);
 		retval = aarch64_poll(target);
 		if (retval != ERROR_OK)
 			return retval;
@@ -1205,14 +1291,13 @@ static int aarch64_step(struct target *target, int current, target_addr_t addres
 		}
 	}
 
-	aarch64_unset_breakpoint(target, &stepbreakpoint);
-
-	target->debug_reason = DBG_REASON_BREAKPOINT;
-
-	if (breakpoint)
-		aarch64_set_breakpoint(target, breakpoint, 0);
+	retval = mem_ap_write_atomic_u32(armv8->debug_ap,
+			armv8->debug_base + CPUV8_DBG_EDECR, (tmp&(~0x4)));
+	if (retval != ERROR_OK)
+		return retval;
 
-	if (target->state != TARGET_HALTED)
+	target_call_event_callbacks(target, TARGET_EVENT_HALTED);
+	if (target->state == TARGET_HALTED)
 		LOG_DEBUG("target stepped");
 
 	return ERROR_OK;
@@ -1227,9 +1312,8 @@ static int aarch64_restore_context(struct target *target, bool bpwp)
 	if (armv8->pre_restore_context)
 		armv8->pre_restore_context(target);
 
-	return arm_dpm_write_dirty_registers(&armv8->dpm, bpwp);
+	return armv8_dpm_write_dirty_registers(&armv8->dpm, bpwp);
 
-	return ERROR_OK;
 }
 
 /*
@@ -1247,6 +1331,7 @@ static int aarch64_set_breakpoint(struct target *target,
 	struct aarch64_common *aarch64 = target_to_aarch64(target);
 	struct armv8_common *armv8 = &aarch64->armv8_common;
 	struct aarch64_brp *brp_list = aarch64->brp_list;
+	uint32_t dscr;
 
 	if (breakpoint->set) {
 		LOG_WARNING("breakpoint already set");
@@ -1254,6 +1339,7 @@ static int aarch64_set_breakpoint(struct target *target,
 	}
 
 	if (breakpoint->type == BKPT_HARD) {
+		int64_t bpt_value;
 		while (brp_list[brp_i].used && (brp_i < aarch64->brp_num))
 			brp_i++;
 		if (brp_i >= aarch64->brp_num) {
@@ -1264,44 +1350,62 @@ static int aarch64_set_breakpoint(struct target *target,
 		if (breakpoint->length == 2)
 			byte_addr_select = (3 << (breakpoint->address & 0x02));
 		control = ((matchmode & 0x7) << 20)
+			| (1 << 13)
 			| (byte_addr_select << 5)
 			| (3 << 1) | 1;
 		brp_list[brp_i].used = 1;
-		brp_list[brp_i].value = (breakpoint->address & 0xFFFFFFFC);
+		brp_list[brp_i].value = breakpoint->address & 0xFFFFFFFFFFFFFFFC;
 		brp_list[brp_i].control = control;
+		bpt_value = brp_list[brp_i].value;
+
 		retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
-				+ CPUDBG_BVR_BASE + 4 * brp_list[brp_i].BRPn,
-				brp_list[brp_i].value);
+				+ CPUV8_DBG_BVR_BASE + 16 * brp_list[brp_i].BRPn,
+				(uint32_t)(bpt_value & 0xFFFFFFFF));
 		if (retval != ERROR_OK)
 			return retval;
 		retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
-				+ CPUDBG_BCR_BASE + 4 * brp_list[brp_i].BRPn,
+				+ CPUV8_DBG_BVR_BASE + 4 + 16 * brp_list[brp_i].BRPn,
+				(uint32_t)(bpt_value >> 32));
+		if (retval != ERROR_OK)
+			return retval;
+
+		retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
+				+ CPUV8_DBG_BCR_BASE + 16 * brp_list[brp_i].BRPn,
 				brp_list[brp_i].control);
 		if (retval != ERROR_OK)
 			return retval;
 		LOG_DEBUG("brp %i control 0x%0" PRIx32 " value 0x%" TARGET_PRIxADDR, brp_i,
 			brp_list[brp_i].control,
 			brp_list[brp_i].value);
+
 	} else if (breakpoint->type == BKPT_SOFT) {
 		uint8_t code[4];
-		if (breakpoint->length == 2)
-			buf_set_u32(code, 0, 32, ARMV5_T_BKPT(0x11));
-		else
-			buf_set_u32(code, 0, 32, ARMV5_BKPT(0x11));
+		buf_set_u32(code, 0, 32, ARMV8_BKPT(0x11));
 		retval = target_read_memory(target,
-				breakpoint->address & 0xFFFFFFFE,
+				breakpoint->address & 0xFFFFFFFFFFFFFFFE,
 				breakpoint->length, 1,
 				breakpoint->orig_instr);
 		if (retval != ERROR_OK)
 			return retval;
 		retval = target_write_memory(target,
-				breakpoint->address & 0xFFFFFFFE,
+				breakpoint->address & 0xFFFFFFFFFFFFFFFE,
 				breakpoint->length, 1, code);
 		if (retval != ERROR_OK)
 			return retval;
 		breakpoint->set = 0x11;	/* Any nice value but 0 */
 	}
 
+	retval = mem_ap_read_atomic_u32(armv8->debug_ap,
+					armv8->debug_base + CPUV8_DBG_DSCR, &dscr);
+	/* Ensure that halting debug mode is enable */
+	dscr = dscr | DSCR_HDE;
+	retval = mem_ap_write_atomic_u32(armv8->debug_ap,
+					 armv8->debug_base + CPUV8_DBG_DSCR, dscr);
+	if (retval != ERROR_OK) {
+		LOG_DEBUG("Failed to set DSCR.HDE");
+		return retval;
+	}
+
 	return ERROR_OK;
 }
 
@@ -1332,18 +1436,19 @@ static int aarch64_set_context_breakpoint(struct target *target,
 
 	breakpoint->set = brp_i + 1;
 	control = ((matchmode & 0x7) << 20)
+		| (1 << 13)
 		| (byte_addr_select << 5)
 		| (3 << 1) | 1;
 	brp_list[brp_i].used = 1;
 	brp_list[brp_i].value = (breakpoint->asid);
 	brp_list[brp_i].control = control;
 	retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
-			+ CPUDBG_BVR_BASE + 4 * brp_list[brp_i].BRPn,
+			+ CPUV8_DBG_BVR_BASE + 16 * brp_list[brp_i].BRPn,
 			brp_list[brp_i].value);
 	if (retval != ERROR_OK)
 		return retval;
 	retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
-			+ CPUDBG_BCR_BASE + 4 * brp_list[brp_i].BRPn,
+			+ CPUV8_DBG_BCR_BASE + 16 * brp_list[brp_i].BRPn,
 			brp_list[brp_i].control);
 	if (retval != ERROR_OK)
 		return retval;
@@ -1404,30 +1509,36 @@ static int aarch64_set_hybrid_breakpoint(struct target *target, struct breakpoin
 	brp_list[brp_1].value = (breakpoint->asid);
 	brp_list[brp_1].control = control_CTX;
 	retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
-			+ CPUDBG_BVR_BASE + 4 * brp_list[brp_1].BRPn,
+			+ CPUV8_DBG_BVR_BASE + 16 * brp_list[brp_1].BRPn,
 			brp_list[brp_1].value);
 	if (retval != ERROR_OK)
 		return retval;
 	retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
-			+ CPUDBG_BCR_BASE + 4 * brp_list[brp_1].BRPn,
+			+ CPUV8_DBG_BCR_BASE + 16 * brp_list[brp_1].BRPn,
 			brp_list[brp_1].control);
 	if (retval != ERROR_OK)
 		return retval;
 
 	control_IVA = ((IVA_machmode & 0x7) << 20)
 		| (brp_1 << 16)
+		| (1 << 13)
 		| (IVA_byte_addr_select << 5)
 		| (3 << 1) | 1;
 	brp_list[brp_2].used = 1;
-	brp_list[brp_2].value = (breakpoint->address & 0xFFFFFFFC);
+	brp_list[brp_2].value = breakpoint->address & 0xFFFFFFFFFFFFFFFC;
 	brp_list[brp_2].control = control_IVA;
 	retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
-			+ CPUDBG_BVR_BASE + 4 * brp_list[brp_2].BRPn,
-			brp_list[brp_2].value);
+			+ CPUV8_DBG_BVR_BASE + 16 * brp_list[brp_2].BRPn,
+			brp_list[brp_2].value & 0xFFFFFFFF);
 	if (retval != ERROR_OK)
 		return retval;
 	retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
-			+ CPUDBG_BCR_BASE + 4 * brp_list[brp_2].BRPn,
+			+ CPUV8_DBG_BVR_BASE + 4 + 16 * brp_list[brp_2].BRPn,
+			brp_list[brp_2].value >> 32);
+	if (retval != ERROR_OK)
+		return retval;
+	retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
+			+ CPUV8_DBG_BCR_BASE + 16 * brp_list[brp_2].BRPn,
 			brp_list[brp_2].control);
 	if (retval != ERROR_OK)
 		return retval;
@@ -1461,15 +1572,10 @@ static int aarch64_unset_breakpoint(struct target *target, struct breakpoint *br
 			brp_list[brp_i].value = 0;
 			brp_list[brp_i].control = 0;
 			retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
-					+ CPUDBG_BCR_BASE + 16 * brp_list[brp_i].BRPn,
+					+ CPUV8_DBG_BCR_BASE + 16 * brp_list[brp_i].BRPn,
 					brp_list[brp_i].control);
 			if (retval != ERROR_OK)
 				return retval;
-			retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
-					+ CPUDBG_BVR_BASE + 16 * brp_list[brp_i].BRPn,
-					brp_list[brp_i].value);
-			if (retval != ERROR_OK)
-				return retval;
 			if ((brp_j < 0) || (brp_j >= aarch64->brp_num)) {
 				LOG_DEBUG("Invalid BRP number in breakpoint");
 				return ERROR_OK;
@@ -1480,15 +1586,10 @@ static int aarch64_unset_breakpoint(struct target *target, struct breakpoint *br
 			brp_list[brp_j].value = 0;
 			brp_list[brp_j].control = 0;
 			retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
-					+ CPUDBG_BCR_BASE + 16 * brp_list[brp_j].BRPn,
+					+ CPUV8_DBG_BCR_BASE + 16 * brp_list[brp_j].BRPn,
 					brp_list[brp_j].control);
 			if (retval != ERROR_OK)
 				return retval;
-			retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
-					+ CPUDBG_BVR_BASE + 16 * brp_list[brp_j].BRPn,
-					brp_list[brp_j].value);
-			if (retval != ERROR_OK)
-				return retval;
 			breakpoint->linked_BRP = 0;
 			breakpoint->set = 0;
 			return ERROR_OK;
@@ -1505,12 +1606,12 @@ static int aarch64_unset_breakpoint(struct target *target, struct breakpoint *br
 			brp_list[brp_i].value = 0;
 			brp_list[brp_i].control = 0;
 			retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
-					+ CPUDBG_BCR_BASE + 4 * brp_list[brp_i].BRPn,
+					+ CPUV8_DBG_BCR_BASE + 16 * brp_list[brp_i].BRPn,
 					brp_list[brp_i].control);
 			if (retval != ERROR_OK)
 				return retval;
 			retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
-					+ CPUDBG_BVR_BASE + 4 * brp_list[brp_i].BRPn,
+					+ CPUV8_DBG_BVR_BASE + 16 * brp_list[brp_i].BRPn,
 					brp_list[brp_i].value);
 			if (retval != ERROR_OK)
 				return retval;
@@ -1667,7 +1768,7 @@ static int aarch64_deassert_reset(struct target *target)
 	return ERROR_OK;
 }
 
-static int aarch64_write_apb_ab_memory(struct target *target,
+static int aarch64_write_apb_ap_memory(struct target *target,
 	uint64_t address, uint32_t size,
 	uint32_t count, const uint8_t *buffer)
 {
@@ -1682,7 +1783,6 @@ static int aarch64_write_apb_ab_memory(struct target *target,
 	struct reg *reg;
 	uint32_t dscr;
 	uint8_t *tmp_buff = NULL;
-	uint32_t i = 0;
 
 	LOG_DEBUG("Writing APB-AP memory address 0x%" PRIx64 " size %"  PRIu32 " count%"  PRIu32,
 			  address, size, count);
@@ -1705,15 +1805,13 @@ static int aarch64_write_apb_ab_memory(struct target *target,
 	reg->dirty = true;
 
 	/*  clear any abort  */
-	retval = mem_ap_write_atomic_u32(armv8->debug_ap, armv8->debug_base + CPUDBG_DRCR, 1<<2);
+	retval = mem_ap_write_atomic_u32(armv8->debug_ap,
+			armv8->debug_base + CPUV8_DBG_DRCR, DRCR_CSE);
 	if (retval != ERROR_OK)
 		return retval;
 
-	/* This algorithm comes from either :
-	 * Cortex-A8 TRM Example 12-25
-	 * Cortex-R4 TRM Example 11-26
-	 * (slight differences)
-	 */
+
+	/* This algorithm comes from DDI0487A.g, chapter J9.1 */
 
 	/* The algorithm only copies 32 bit words, so the buffer
 	 * should be expanded to include the words at either end.
@@ -1726,7 +1824,7 @@ static int aarch64_write_apb_ab_memory(struct target *target,
 		/* First bytes not aligned - read the 32 bit word to avoid corrupting
 		 * the other bytes in the word.
 		 */
-		retval = aarch64_read_apb_ab_memory(target, (address & ~0x3), 4, 1, tmp_buff);
+		retval = aarch64_read_apb_ap_memory(target, (address & ~0x3), 4, 1, tmp_buff);
 		if (retval != ERROR_OK)
 			goto error_free_buff_w;
 	}
@@ -1737,7 +1835,7 @@ static int aarch64_write_apb_ab_memory(struct target *target,
 
 		/* Read the last word to avoid corruption during 32 bit write */
 		int mem_offset = (total_u32-1) * 4;
-		retval = aarch64_read_apb_ab_memory(target, (address & ~0x3) + mem_offset, 4, 1, &tmp_buff[mem_offset]);
+		retval = aarch64_read_apb_ap_memory(target, (address & ~0x3) + mem_offset, 4, 1, &tmp_buff[mem_offset]);
 		if (retval != ERROR_OK)
 			goto error_free_buff_w;
 	}
@@ -1749,56 +1847,62 @@ static int aarch64_write_apb_ab_memory(struct target *target,
 
 	/* Read DSCR */
 	retval = mem_ap_read_atomic_u32(armv8->debug_ap,
-			armv8->debug_base + CPUDBG_DSCR, &dscr);
+			armv8->debug_base + CPUV8_DBG_DSCR, &dscr);
 	if (retval != ERROR_OK)
 		goto error_free_buff_w;
 
-	/* Set DTR mode to Normal*/
-	dscr = (dscr & ~DSCR_EXT_DCC_MASK) | DSCR_EXT_DCC_NON_BLOCKING;
+	/* Set Normal access mode  */
+	dscr = (dscr & ~DSCR_MA);
 	retval = mem_ap_write_atomic_u32(armv8->debug_ap,
-			armv8->debug_base + CPUDBG_DSCR, dscr);
+			armv8->debug_base + CPUV8_DBG_DSCR, dscr);
+
+	if (arm->core_state == ARM_STATE_AARCH64) {
+		/* Write X0 with value 'address' using write procedure */
+		/* Step 1.a+b - Write the address for read access into DBGDTR_EL0 */
+		retval += aarch64_write_dcc_64(armv8, address & ~0x3ULL);
+		/* Step 1.c   - Copy value from DTR to R0 using instruction mrs DBGDTR_EL0, x0 */
+		retval += aarch64_exec_opcode(target,
+				ARMV8_MRS(SYSTEM_DBG_DBGDTR_EL0, 0), &dscr);
+	} else {
+		/* Write R0 with value 'address' using write procedure */
+		/* Step 1.a+b - Write the address for read access into DBGDTRRX */
+		retval += aarch64_write_dcc(armv8, address & ~0x3ULL);
+		/* Step 1.c   - Copy value from DTR to R0 using instruction mrc DBGDTRTXint, r0 */
+		retval += aarch64_exec_opcode(target,
+				T32_FMTITR(ARMV4_5_MRC(14, 0, 0, 0, 5, 0)), &dscr);
+
+	}
+	/* Step 1.d   - Change DCC to memory mode */
+	dscr = dscr | DSCR_MA;
+	retval +=  mem_ap_write_atomic_u32(armv8->debug_ap,
+			armv8->debug_base + CPUV8_DBG_DSCR, dscr);
 	if (retval != ERROR_OK)
-		goto error_free_buff_w;
-
-	if (size > 4) {
-		LOG_WARNING("reading size >4 bytes not yet supported");
 		goto error_unset_dtr_w;
-	}
 
-	retval = aarch64_instr_write_data_dcc_64(arm->dpm, 0xd5330401, address+4);
+
+	/* Step 2.a   - Do the write */
+	retval = mem_ap_write_buf_noincr(armv8->debug_ap,
+					tmp_buff, 4, total_u32, armv8->debug_base + CPUV8_DBG_DTRRX);
 	if (retval != ERROR_OK)
 		goto error_unset_dtr_w;
 
-	dscr = DSCR_INSTR_COMP;
-	while (i < count * size) {
-		uint32_t val;
-
-		memcpy(&val, &buffer[i], size);
-		retval = aarch64_instr_write_data_dcc(arm->dpm, 0xd5330500, val);
-		if (retval != ERROR_OK)
-			goto error_unset_dtr_w;
-
-		retval = aarch64_exec_opcode(target, 0xb81fc020, &dscr);
-		if (retval != ERROR_OK)
-			goto error_unset_dtr_w;
-
-		retval = aarch64_exec_opcode(target, 0x91001021, &dscr);
-		if (retval != ERROR_OK)
-			goto error_unset_dtr_w;
-
-		i += 4;
-	}
+	/* Step 3.a   - Switch DTR mode back to Normal mode */
+	dscr = (dscr & ~DSCR_MA);
+	retval = mem_ap_write_atomic_u32(armv8->debug_ap,
+				armv8->debug_base + CPUV8_DBG_DSCR, dscr);
+	if (retval != ERROR_OK)
+		goto error_unset_dtr_w;
 
 	/* Check for sticky abort flags in the DSCR */
 	retval = mem_ap_read_atomic_u32(armv8->debug_ap,
-				armv8->debug_base + CPUDBG_DSCR, &dscr);
+				armv8->debug_base + CPUV8_DBG_DSCR, &dscr);
 	if (retval != ERROR_OK)
 		goto error_free_buff_w;
-	if (dscr & (DSCR_STICKY_ABORT_PRECISE | DSCR_STICKY_ABORT_IMPRECISE)) {
+	if (dscr & (DSCR_ERR | DSCR_SYS_ERROR_PEND)) {
 		/* Abort occurred - clear it and exit */
 		LOG_ERROR("abort occurred - dscr = 0x%08" PRIx32, dscr);
 		mem_ap_write_atomic_u32(armv8->debug_ap,
-					armv8->debug_base + CPUDBG_DRCR, 1<<2);
+					armv8->debug_base + CPUV8_DBG_DRCR, 1<<2);
 		goto error_free_buff_w;
 	}
 
@@ -1809,29 +1913,33 @@ static int aarch64_write_apb_ab_memory(struct target *target,
 error_unset_dtr_w:
 	/* Unset DTR mode */
 	mem_ap_read_atomic_u32(armv8->debug_ap,
-				armv8->debug_base + CPUDBG_DSCR, &dscr);
-	dscr = (dscr & ~DSCR_EXT_DCC_MASK) | DSCR_EXT_DCC_NON_BLOCKING;
+				armv8->debug_base + CPUV8_DBG_DSCR, &dscr);
+	dscr = (dscr & ~DSCR_MA);
 	mem_ap_write_atomic_u32(armv8->debug_ap,
-				armv8->debug_base + CPUDBG_DSCR, dscr);
+				armv8->debug_base + CPUV8_DBG_DSCR, dscr);
 error_free_buff_w:
 	LOG_ERROR("error");
 	free(tmp_buff);
 	return ERROR_FAIL;
 }
 
-static int aarch64_read_apb_ab_memory(struct target *target,
+static int aarch64_read_apb_ap_memory(struct target *target,
 	target_addr_t address, uint32_t size,
 	uint32_t count, uint8_t *buffer)
 {
 	/* read memory through APB-AP */
-
 	int retval = ERROR_COMMAND_SYNTAX_ERROR;
 	struct armv8_common *armv8 = target_to_armv8(target);
 	struct arm *arm = &armv8->arm;
+	int total_bytes = count * size;
+	int total_u32;
+	int start_byte = address & 0x3;
+	int end_byte   = (address + total_bytes) & 0x3;
 	struct reg *reg;
-	uint32_t dscr, val;
+	uint32_t dscr;
 	uint8_t *tmp_buff = NULL;
-	uint32_t i = 0;
+	uint8_t *u8buf_ptr;
+	uint32_t value;
 
 	LOG_DEBUG("Reading APB-AP memory address 0x%" TARGET_PRIxADDR " size %"	PRIu32 " count%"  PRIu32,
 			  address, size, count);
@@ -1840,72 +1948,146 @@ static int aarch64_read_apb_ab_memory(struct target *target,
 		return ERROR_TARGET_NOT_HALTED;
 	}
 
-	/* Mark register R0 as dirty, as it will be used
+	total_u32 = DIV_ROUND_UP((address & 3) + total_bytes, 4);
+	/* Mark register X0, X1 as dirty, as it will be used
 	 * for transferring the data.
 	 * It will be restored automatically when exiting
 	 * debug mode
 	 */
+	reg = armv8_reg_current(arm, 1);
+	reg->dirty = true;
+
 	reg = armv8_reg_current(arm, 0);
 	reg->dirty = true;
 
-	/*  clear any abort  */
+	/*	clear any abort  */
 	retval = mem_ap_write_atomic_u32(armv8->debug_ap,
-		armv8->debug_base + CPUDBG_DRCR, 1<<2);
+				armv8->debug_base + CPUV8_DBG_DRCR, DRCR_CSE);
 	if (retval != ERROR_OK)
 		goto error_free_buff_r;
 
+	/* Read DSCR */
 	retval = mem_ap_read_atomic_u32(armv8->debug_ap,
-			armv8->debug_base + CPUDBG_DSCR, &dscr);
+				armv8->debug_base + CPUV8_DBG_DSCR, &dscr);
+
+	/* This algorithm comes from DDI0487A.g, chapter J9.1 */
+
+	/* Set Normal access mode  */
+	dscr = (dscr & ~DSCR_MA);
+	retval +=  mem_ap_write_atomic_u32(armv8->debug_ap,
+			armv8->debug_base + CPUV8_DBG_DSCR, dscr);
+
+	if (arm->core_state == ARM_STATE_AARCH64) {
+		/* Write X0 with value 'address' using write procedure */
+		/* Step 1.a+b - Write the address for read access into DBGDTR_EL0 */
+		retval += aarch64_write_dcc_64(armv8, address & ~0x3ULL);
+		/* Step 1.c   - Copy value from DTR to R0 using instruction mrs DBGDTR_EL0, x0 */
+		retval += aarch64_exec_opcode(target, ARMV8_MRS(SYSTEM_DBG_DBGDTR_EL0, 0), &dscr);
+		/* Step 1.d - Dummy operation to ensure EDSCR.Txfull == 1 */
+		retval += aarch64_exec_opcode(target, ARMV8_MSR_GP(SYSTEM_DBG_DBGDTR_EL0, 0), &dscr);
+		/* Step 1.e - Change DCC to memory mode */
+		dscr = dscr | DSCR_MA;
+		retval +=  mem_ap_write_atomic_u32(armv8->debug_ap,
+				armv8->debug_base + CPUV8_DBG_DSCR, dscr);
+		/* Step 1.f - read DBGDTRTX and discard the value */
+		retval += mem_ap_read_atomic_u32(armv8->debug_ap,
+				armv8->debug_base + CPUV8_DBG_DTRTX, &value);
+	} else {
+		/* Write R0 with value 'address' using write procedure */
+		/* Step 1.a+b - Write the address for read access into DBGDTRRXint */
+		retval += aarch64_write_dcc(armv8, address & ~0x3ULL);
+		/* Step 1.c   - Copy value from DTR to R0 using instruction mrc DBGDTRTXint, r0 */
+		retval += aarch64_exec_opcode(target,
+				T32_FMTITR(ARMV4_5_MRC(14, 0, 0, 0, 5, 0)), &dscr);
+		/* Step 1.d - Dummy operation to ensure EDSCR.Txfull == 1 */
+		retval += aarch64_exec_opcode(target,
+				T32_FMTITR(ARMV4_5_MCR(14, 0, 0, 0, 5, 0)), &dscr);
+		/* Step 1.e - Change DCC to memory mode */
+		dscr = dscr | DSCR_MA;
+		retval +=  mem_ap_write_atomic_u32(armv8->debug_ap,
+				armv8->debug_base + CPUV8_DBG_DSCR, dscr);
+		/* Step 1.f - read DBGDTRTX and discard the value */
+		retval += mem_ap_read_atomic_u32(armv8->debug_ap,
+				armv8->debug_base + CPUV8_DBG_DTRTX, &value);
+
+	}
 	if (retval != ERROR_OK)
 		goto error_unset_dtr_r;
 
-	if (size > 4) {
-		LOG_WARNING("reading size >4 bytes not yet supported");
-		goto error_unset_dtr_r;
-	}
+	/* Optimize the read as much as we can, either way we read in a single pass  */
+	if ((start_byte) || (end_byte)) {
+		/* The algorithm only copies 32 bit words, so the buffer
+		 * should be expanded to include the words at either end.
+		 * The first and last words will be read into a temp buffer
+		 * to avoid corruption
+		 */
+		tmp_buff = malloc(total_u32 * 4);
+		if (!tmp_buff)
+			goto error_unset_dtr_r;
 
-	while (i < count * size) {
+		/* use the tmp buffer to read the entire data */
+		u8buf_ptr = tmp_buff;
+	} else
+		/* address and read length are aligned so read directly into the passed buffer */
+		u8buf_ptr = buffer;
 
-		retval = aarch64_instr_write_data_dcc_64(arm->dpm, 0xd5330400, address+4);
-		if (retval != ERROR_OK)
-			goto error_unset_dtr_r;
-		retval = mem_ap_read_atomic_u32(armv8->debug_ap,
-			armv8->debug_base + CPUDBG_DSCR, &dscr);
+	/* Read the data - Each read of the DTRTX register causes the instruction to be reissued
+	 * Abort flags are sticky, so can be read at end of transactions
+	 *
+	 * This data is read in aligned to 32 bit boundary.
+	 */
 
-		dscr = DSCR_INSTR_COMP;
-		retval = aarch64_exec_opcode(target, 0xb85fc000, &dscr);
-		if (retval != ERROR_OK)
+	/* Step 2.a - Loop n-1 times, each read of DBGDTRTX reads the data from [X0] and
+	 * increments X0 by 4. */
+	retval = mem_ap_read_buf_noincr(armv8->debug_ap, u8buf_ptr, 4, total_u32-1,
+									armv8->debug_base + CPUV8_DBG_DTRTX);
+	if (retval != ERROR_OK)
 			goto error_unset_dtr_r;
-		retval = mem_ap_read_atomic_u32(armv8->debug_ap,
-			armv8->debug_base + CPUDBG_DSCR, &dscr);
 
-		retval = aarch64_instr_read_data_dcc(arm->dpm, 0xd5130400, &val);
-		if (retval != ERROR_OK)
-			goto error_unset_dtr_r;
-		memcpy(&buffer[i], &val, size);
-		i += 4;
-		address += 4;
+	/* Step 3.a - set DTR access mode back to Normal mode	*/
+	dscr = (dscr & ~DSCR_MA);
+	retval =  mem_ap_write_atomic_u32(armv8->debug_ap,
+					armv8->debug_base + CPUV8_DBG_DSCR, dscr);
+	if (retval != ERROR_OK)
+		goto error_free_buff_r;
+
+	/* Step 3.b - read DBGDTRTX for the final value */
+	retval = mem_ap_read_atomic_u32(armv8->debug_ap,
+			armv8->debug_base + CPUV8_DBG_DTRTX, &value);
+	memcpy(u8buf_ptr + (total_u32-1) * 4, &value, 4);
+
+	/* Check for sticky abort flags in the DSCR */
+	retval = mem_ap_read_atomic_u32(armv8->debug_ap,
+				armv8->debug_base + CPUV8_DBG_DSCR, &dscr);
+	if (retval != ERROR_OK)
+		goto error_free_buff_r;
+	if (dscr & (DSCR_ERR | DSCR_SYS_ERROR_PEND)) {
+		/* Abort occurred - clear it and exit */
+		LOG_ERROR("abort occurred - dscr = 0x%08" PRIx32, dscr);
+		mem_ap_write_atomic_u32(armv8->debug_ap,
+					armv8->debug_base + CPUV8_DBG_DRCR, DRCR_CSE);
+		goto error_free_buff_r;
 	}
 
-	/* Clear any sticky error */
-	mem_ap_write_atomic_u32(armv8->debug_ap,
-		armv8->debug_base + CPUDBG_DRCR, 1<<2);
+	/* check if we need to copy aligned data by applying any shift necessary */
+	if (tmp_buff) {
+		memcpy(buffer, tmp_buff + start_byte, total_bytes);
+		free(tmp_buff);
+	}
 
 	/* Done */
 	return ERROR_OK;
 
 error_unset_dtr_r:
-	LOG_WARNING("DSCR = 0x%" PRIx32, dscr);
-	/* Todo: Unset DTR mode */
-
+	/* Unset DTR mode */
+	mem_ap_read_atomic_u32(armv8->debug_ap,
+				armv8->debug_base + CPUV8_DBG_DSCR, &dscr);
+	dscr = (dscr & ~DSCR_MA);
+	mem_ap_write_atomic_u32(armv8->debug_ap,
+				armv8->debug_base + CPUV8_DBG_DSCR, dscr);
 error_free_buff_r:
 	LOG_ERROR("error");
 	free(tmp_buff);
-
-	/* Clear any sticky error */
-	mem_ap_write_atomic_u32(armv8->debug_ap,
-		armv8->debug_base + CPUDBG_DRCR, 1<<2);
-
 	return ERROR_FAIL;
 }
 
@@ -1931,7 +2113,7 @@ static int aarch64_read_phys_memory(struct target *target,
 			retval = aarch64_mmu_modify(target, 0);
 			if (retval != ERROR_OK)
 				return retval;
-			retval = aarch64_read_apb_ab_memory(target, address, size, count, buffer);
+			retval = aarch64_read_apb_ap_memory(target, address, size, count, buffer);
 		}
 	}
 	return retval;
@@ -1982,7 +2164,7 @@ static int aarch64_read_memory(struct target *target, target_addr_t address,
 			if (retval != ERROR_OK)
 				return retval;
 		}
-		retval = aarch64_read_apb_ab_memory(target, address, size,
+		retval = aarch64_read_apb_ap_memory(target, address, size,
 						    count, buffer);
 	}
 	return retval;
@@ -2014,7 +2196,7 @@ static int aarch64_write_phys_memory(struct target *target,
 				if (retval != ERROR_OK)
 					return retval;
 			}
-			return aarch64_write_apb_ab_memory(target, address, size, count, buffer);
+			return aarch64_write_apb_ap_memory(target, address, size, count, buffer);
 		}
 	}
 
@@ -2122,7 +2304,7 @@ static int aarch64_write_memory(struct target *target, target_addr_t address,
 			if (retval != ERROR_OK)
 				return retval;
 		}
-		retval = aarch64_write_apb_ab_memory(target, address, size, count, buffer);
+		retval = aarch64_write_apb_ap_memory(target, address, size, count, buffer);
 	}
 	return retval;
 }
@@ -2142,16 +2324,16 @@ static int aarch64_handle_target_request(void *priv)
 		uint32_t request;
 		uint32_t dscr;
 		retval = mem_ap_read_atomic_u32(armv8->debug_ap,
-				armv8->debug_base + CPUDBG_DSCR, &dscr);
+				armv8->debug_base + CPUV8_DBG_DSCR, &dscr);
 
 		/* check if we have data */
 		while ((dscr & DSCR_DTR_TX_FULL) && (retval == ERROR_OK)) {
 			retval = mem_ap_read_atomic_u32(armv8->debug_ap,
-					armv8->debug_base + CPUDBG_DTRTX, &request);
+					armv8->debug_base + CPUV8_DBG_DTRTX, &request);
 			if (retval == ERROR_OK) {
 				target_request(target, request);
 				retval = mem_ap_read_atomic_u32(armv8->debug_ap,
-						armv8->debug_base + CPUDBG_DSCR, &dscr);
+						armv8->debug_base + CPUV8_DBG_DSCR, &dscr);
 			}
 		}
 	}
@@ -2222,8 +2404,14 @@ static int aarch64_examine_first(struct target *target)
 	} else
 		armv8->debug_base = target->dbgbase;
 
+	LOG_DEBUG("Target ctibase is 0x%x", target->ctibase);
+	if (target->ctibase == 0)
+		armv8->cti_base = target->ctibase = armv8->debug_base + 0x1000;
+	else
+		armv8->cti_base = target->ctibase;
+
 	retval = mem_ap_write_atomic_u32(armv8->debug_ap,
-			armv8->debug_base + 0x300, 0);
+			armv8->debug_base + CPUV8_DBG_LOCKACCESS, 0xC5ACCE55);
 	if (retval != ERROR_OK) {
 		LOG_DEBUG("Examine %s failed", "oslock");
 		return retval;