X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Farm11.c;h=0cb1d8c83fbd982f61270036330f31472af618b9;hb=889b246d939bf8572094cf4bfe56f58f44e8ff62;hp=26e8116f64ee400e141c7d0b96504bf6fe6ad13f;hpb=4315142ea0d7035fe117b9e344beaf98c91ee35c;p=openocd.git

diff --git a/src/target/arm11.c b/src/target/arm11.c
index 26e8116f64..0cb1d8c83f 100644
--- a/src/target/arm11.c
+++ b/src/target/arm11.c
@@ -21,7 +21,7 @@
  *   You should have received a copy of the GNU General Public License     *
  *   along with this program; if not, write to the                         *
  *   Free Software Foundation, Inc.,                                       *
- *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
+ *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
  ***************************************************************************/
 
 #ifdef HAVE_CONFIG_H
@@ -363,15 +363,6 @@ static int arm11_arch_state(struct target *target)
 	return retval;
 }
 
-/* target request support */
-static int arm11_target_request_data(struct target *target,
-	uint32_t size, uint8_t *buffer)
-{
-	LOG_WARNING("Not implemented: %s", __func__);
-
-	return ERROR_FAIL;
-}
-
 /* target execution control */
 static int arm11_halt(struct target *target)
 {
@@ -771,13 +762,6 @@ static int arm11_deassert_reset(struct target *target)
 	return ERROR_OK;
 }
 
-static int arm11_soft_reset_halt(struct target *target)
-{
-	LOG_WARNING("Not implemented: %s", __func__);
-
-	return ERROR_FAIL;
-}
-
 /* target memory access
  * size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)
  * count: number of items of <size>
@@ -1094,6 +1078,7 @@ static int arm11_target_create(struct target *target, Jim_Interp *interp)
 	if (!arm11)
 		return ERROR_FAIL;
 
+	arm11->arm.core_type = ARM_MODE_ANY;
 	arm_init_arch_info(target, &arm11->arm);
 
 	arm11->jtag_info.tap = target->tap;
@@ -1192,6 +1177,12 @@ static int arm11_examine(struct target *target)
 	LOG_DEBUG("IDCODE %08" PRIx32 " IMPLEMENTOR %02x DIDR %08" PRIx32,
 		device_id, implementor, didr);
 
+	/* Build register cache "late", after target_init(), since we
+	 * want to know if this core supports Secure Monitor mode.
+	 */
+	if (!target_was_examined(target))
+		CHECK_RETVAL(arm11_dpm_init(arm11, didr));
+
 	/* as a side-effect this reads DSCR and thus
 	 * clears the ARM11_DSCR_STICKY_PRECISE_DATA_ABORT / Sticky Precise Data Abort Flag
 	 * as suggested by the spec.
@@ -1201,12 +1192,6 @@ static int arm11_examine(struct target *target)
 	if (retval != ERROR_OK)
 		return retval;
 
-	/* Build register cache "late", after target_init(), since we
-	 * want to know if this core supports Secure Monitor mode.
-	 */
-	if (!target_was_examined(target))
-		CHECK_RETVAL(arm11_dpm_init(arm11, didr));
-
 	/* ETM on ARM11 still uses original scanchain 6 access mode */
 	if (arm11->arm.etm && !target_was_examined(target)) {
 		*register_get_last_cache_p(&target->reg_cache) =
@@ -1339,15 +1324,12 @@ struct target_type arm11_target = {
 	.poll = arm11_poll,
 	.arch_state = arm11_arch_state,
 
-	.target_request_data = arm11_target_request_data,
-
 	.halt = arm11_halt,
 	.resume = arm11_resume,
 	.step = arm11_step,
 
 	.assert_reset = arm11_assert_reset,
 	.deassert_reset = arm11_deassert_reset,
-	.soft_reset_halt = arm11_soft_reset_halt,
 
 	.get_gdb_reg_list = arm_get_gdb_reg_list,