X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Farm11.c;h=20ad22d50235dba2f23e5a670b6d0e720ed87749;hb=1527272fb21beee7839335ea5587e879163d2ed1;hp=44c9ad300e9d0219324e993fe4a990b8fc04f637;hpb=d5e4e23f9a5b1074cd298d5386e638a9fa78b1ad;p=openocd.git diff --git a/src/target/arm11.c b/src/target/arm11.c index 44c9ad300e..20ad22d502 100644 --- a/src/target/arm11.c +++ b/src/target/arm11.c @@ -30,7 +30,7 @@ #include "breakpoints.h" #include "arm11_dbgtap.h" #include "arm_simulator.h" -#include "time_support.h" +#include #include "target_type.h" #include "algorithm.h" #include "register.h" @@ -40,6 +40,10 @@ #define _DEBUG_INSTRUCTION_EXECUTION_ #endif + +/* FIXME none of these flags should be global to all ARM11 cores! + * Most of them shouldn't exist at all, once the code works... + */ static bool arm11_config_memwrite_burst = true; static bool arm11_config_memwrite_error_fatal = true; static uint32_t arm11_vcr = 0; @@ -59,18 +63,18 @@ static int arm11_check_init(struct arm11_common *arm11) CHECK_RETVAL(arm11_read_DSCR(arm11)); LOG_DEBUG("DSCR %08x", (unsigned) arm11->dscr); - if (!(arm11->dscr & ARM11_DSCR_MODE_SELECT)) + if (!(arm11->dscr & DSCR_HALT_DBG_MODE)) { LOG_DEBUG("Bringing target into debug mode"); - arm11->dscr |= ARM11_DSCR_MODE_SELECT; /* Halt debug-mode */ + arm11->dscr |= DSCR_HALT_DBG_MODE; arm11_write_DSCR(arm11, arm11->dscr); /* add further reset initialization here */ arm11->simulate_reset_on_next_halt = true; - if (arm11->dscr & ARM11_DSCR_CORE_HALTED) + if (arm11->dscr & DSCR_CORE_HALTED) { /** \todo TODO: this needs further scrutiny because * arm11_debug_entry() never gets called. (WHY NOT?) @@ -79,8 +83,7 @@ static int arm11_check_init(struct arm11_common *arm11) */ arm11->arm.target->state = TARGET_HALTED; - arm11->arm.target->debug_reason = - arm11_get_DSCR_debug_reason(arm11->dscr); + arm_dpm_report_dscr(arm11->arm.dpm, arm11->dscr); } else { @@ -104,8 +107,7 @@ static int arm11_debug_entry(struct arm11_common *arm11) int retval; arm11->arm.target->state = TARGET_HALTED; - arm11->arm.target->debug_reason = - arm11_get_DSCR_debug_reason(arm11->dscr); + arm_dpm_report_dscr(arm11->arm.dpm, arm11->dscr); /* REVISIT entire cache should already be invalid !!! */ register_cache_invalidate(arm11->arm.core_cache); @@ -113,7 +115,7 @@ static int arm11_debug_entry(struct arm11_common *arm11) /* See e.g. ARM1136 TRM, "14.8.4 Entering Debug state" */ /* maybe save wDTR (pending DCC write to debug SW, e.g. libdcc) */ - arm11->is_wdtr_saved = !!(arm11->dscr & ARM11_DSCR_WDTR_FULL); + arm11->is_wdtr_saved = !!(arm11->dscr & DSCR_DTR_TX_FULL); if (arm11->is_wdtr_saved) { arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT); @@ -131,15 +133,13 @@ static int arm11_debug_entry(struct arm11_common *arm11) } - /* DSCR: set ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE + /* DSCR: set the Execute ARM instruction enable bit. * * ARM1176 spec says this is needed only for wDTR/rDTR's "ITR mode", - * but not to issue ITRs. ARM1136 seems to require this to issue - * ITR's as well... + * but not to issue ITRs(?). The ARMv7 arch spec says it's required + * for executing instructions via ITR. */ - - arm11_write_DSCR(arm11, ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE - | arm11->dscr); + arm11_write_DSCR(arm11, DSCR_ITR_EN | arm11->dscr); /* From the spec: @@ -188,7 +188,7 @@ static int arm11_debug_entry(struct arm11_common *arm11) return retval; /* maybe save rDTR (pending DCC read from debug SW, e.g. libdcc) */ - arm11->is_rdtr_saved = !!(arm11->dscr & ARM11_DSCR_RDTR_FULL); + arm11->is_rdtr_saved = !!(arm11->dscr & DSCR_DTR_RX_FULL); if (arm11->is_rdtr_saved) { /* MRC p14,0,R0,c0,c5,0 (move rDTR -> r0 (-> wDTR -> local var)) */ @@ -248,7 +248,7 @@ static int arm11_leave_debug_state(struct arm11_common *arm11, bool bpwp) { CHECK_RETVAL(arm11_read_DSCR(arm11)); - if (arm11->dscr & (ARM11_DSCR_RDTR_FULL | ARM11_DSCR_WDTR_FULL)) + if (arm11->dscr & (DSCR_DTR_RX_FULL | DSCR_DTR_TX_FULL)) { /* The wDTR/rDTR two registers that are used to send/receive data to/from @@ -324,7 +324,7 @@ static int arm11_poll(struct target *target) CHECK_RETVAL(arm11_check_init(arm11)); - if (arm11->dscr & ARM11_DSCR_CORE_HALTED) + if (arm11->dscr & DSCR_CORE_HALTED) { if (target->state != TARGET_HALTED) { @@ -401,7 +401,7 @@ static int arm11_halt(struct target *target) { CHECK_RETVAL(arm11_read_DSCR(arm11)); - if (arm11->dscr & ARM11_DSCR_CORE_HALTED) + if (arm11->dscr & DSCR_CORE_HALTED) break; @@ -529,7 +529,7 @@ static int arm11_resume(struct target *target, int current, LOG_DEBUG("DSCR %08x", (unsigned) arm11->dscr); - if (arm11->dscr & ARM11_DSCR_CORE_RESTARTED) + if (arm11->dscr & DSCR_CORE_RESTARTED) break; @@ -549,20 +549,12 @@ static int arm11_resume(struct target *target, int current, i++; } + target->debug_reason = DBG_REASON_NOTHALTED; if (!debug_execution) - { - target->state = TARGET_RUNNING; - target->debug_reason = DBG_REASON_NOTHALTED; - - CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED)); - } + target->state = TARGET_RUNNING; else - { - target->state = TARGET_DEBUG_RUNNING; - target->debug_reason = DBG_REASON_NOTHALTED; - - CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED)); - } + target->state = TARGET_DEBUG_RUNNING; + CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED)); return ERROR_OK; } @@ -674,9 +666,9 @@ static int arm11_step(struct target *target, int current, if (arm11_config_step_irq_enable) /* this disable should be redundant ... */ - arm11->dscr &= ~ARM11_DSCR_INTERRUPTS_DISABLE; + arm11->dscr &= ~DSCR_INT_DIS; else - arm11->dscr |= ARM11_DSCR_INTERRUPTS_DISABLE; + arm11->dscr |= DSCR_INT_DIS; CHECK_RETVAL(arm11_leave_debug_state(arm11, handle_breakpoints)); @@ -690,8 +682,8 @@ static int arm11_step(struct target *target, int current, while (1) { - const uint32_t mask = ARM11_DSCR_CORE_RESTARTED - | ARM11_DSCR_CORE_HALTED; + const uint32_t mask = DSCR_CORE_RESTARTED + | DSCR_CORE_HALTED; CHECK_RETVAL(arm11_read_DSCR(arm11)); LOG_DEBUG("DSCR %08x e", (unsigned) arm11->dscr); @@ -722,11 +714,11 @@ static int arm11_step(struct target *target, int current, CHECK_RETVAL(arm11_debug_entry(arm11)); /* restore default state */ - arm11->dscr &= ~ARM11_DSCR_INTERRUPTS_DISABLE; + arm11->dscr &= ~DSCR_INT_DIS; } - target->debug_reason = DBG_REASON_SINGLESTEP; + target->debug_reason = DBG_REASON_SINGLESTEP; CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_HALTED));