X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Farm11.h;h=77cc2236d7a6f815e3f965f98ca91570b934df91;hb=f7836bbc75586666d639edd1cf39a871c434d980;hp=cde6c787d014504c69f8c8737acf12b20d10d315;hpb=7e18d96d03e39ef55c0b1d420b53247a29fef24b;p=openocd.git

diff --git a/src/target/arm11.h b/src/target/arm11.h
index cde6c787d0..77cc2236d7 100644
--- a/src/target/arm11.h
+++ b/src/target/arm11.h
@@ -15,77 +15,74 @@
  *   GNU General Public License for more details.                          *
  *                                                                         *
  *   You should have received a copy of the GNU General Public License     *
- *   along with this program; if not, write to the                         *
- *   Free Software Foundation, Inc.,                                       *
- *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
+ *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  ***************************************************************************/
 
-#ifndef ARM11_H
-#define ARM11_H
+#ifndef OPENOCD_TARGET_ARM11_H
+#define OPENOCD_TARGET_ARM11_H
 
-#include "armv4_5.h"
+#include "arm.h"
 #include "arm_dpm.h"
 
-#define ARM11_REGCACHE_COUNT		2
-
-#define ARM11_TAP_DEFAULT			TAP_INVALID
+#define ARM11_TAP_DEFAULT                       TAP_INVALID
 
 #define CHECK_RETVAL(action)			\
 	do {					\
 		int __retval = (action);	\
 		if (__retval != ERROR_OK) {	\
 			LOG_DEBUG("error while calling \"%s\"",	\
-				# action );	\
+				# action);     \
 			return __retval;	\
 		}				\
 	} while (0)
 
-enum arm11_debug_version
-{
-	ARM11_DEBUG_V6			= 0x01,
-	ARM11_DEBUG_V61			= 0x02,
-	ARM11_DEBUG_V7			= 0x03,
-	ARM11_DEBUG_V7_CP14		= 0x04,
+/* bits from ARMv7 DIDR */
+enum arm11_debug_version {
+	ARM11_DEBUG_V6                  = 0x01,
+	ARM11_DEBUG_V61                 = 0x02,
+	ARM11_DEBUG_V7                  = 0x03,
+	ARM11_DEBUG_V7_CP14             = 0x04,
 };
 
-struct arm11_common
-{
-	struct arm	arm;
+struct arm11_common {
+	struct arm arm;
 
 	/** Debug module state. */
 	struct arm_dpm dpm;
+	struct arm11_sc7_action *bpwp_actions;
+	unsigned bpwp_n;
 
-	size_t	brp;			/**< Number of Breakpoint Register Pairs from DIDR	*/
-	size_t	wrp;			/**< Number of Watchpoint Register Pairs from DIDR	*/
-	size_t	free_brps;		/**< Number of breakpoints allocated */
+	size_t brp;			/**< Number of Breakpoint Register Pairs from DIDR	*/
+	size_t free_brps;		/**< Number of breakpoints allocated */
 
-	uint32_t		last_dscr;		/**< Last retrieved DSCR value;
-							     Use only for debug message generation		*/
+	uint32_t dscr;			/**< Last retrieved DSCR value. */
 
 	uint32_t saved_rdtr;
+	uint32_t saved_wdtr;
 
 	bool is_rdtr_saved;
-	bool	simulate_reset_on_next_halt;	/**< Perform cleanups of the ARM state on next halt */
-
-	/** \name Shadow registers to save debug state */
-	/*@{*/
+	bool is_wdtr_saved;
 
-	struct reg *	reg_list;							/**< target register list */
-	uint32_t		reg_values[ARM11_REGCACHE_COUNT];	/**< data for registers */
+	bool simulate_reset_on_next_halt;	/**< Perform cleanups of the ARM state on next halt **/
 
-	/*@}*/
+	/* Per-core configurable options.
+	 * NOTE that several of these boolean options should not exist
+	 * once the relevant code is known to work correctly.
+	 */
+	bool memwrite_burst;
+	bool memwrite_error_fatal;
+	bool step_irq_enable;
+	bool hardware_step;
 
-
-	// GA
-	struct reg_cache *core_cache;
+	/** Configured Vector Catch Register settings. */
+	uint32_t vcr;
 
 	struct arm_jtag jtag_info;
 };
 
 static inline struct arm11_common *target_to_arm11(struct target *target)
 {
-	return container_of(target->arch_info, struct arm11_common,
-			arm);
+	return container_of(target->arch_info, struct arm11_common, arm);
 }
 
 /**
@@ -93,61 +90,25 @@ static inline struct arm11_common *target_to_arm11(struct target *target)
  *
  * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0301f/I1006229.html
  */
-enum arm11_instructions
-{
+enum arm11_instructions {
 	ARM11_EXTEST    = 0x00,
 	ARM11_SCAN_N    = 0x02,
 	ARM11_RESTART   = 0x04,
-	ARM11_HALT	    = 0x08,
+	ARM11_HALT          = 0x08,
 	ARM11_INTEST    = 0x0C,
 	ARM11_ITRSEL    = 0x1D,
 	ARM11_IDCODE    = 0x1E,
 	ARM11_BYPASS    = 0x1F,
 };
 
-enum arm11_dscr
-{
-	ARM11_DSCR_CORE_HALTED									= 1 << 0,
-	ARM11_DSCR_CORE_RESTARTED								= 1 << 1,
-
-	ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_MASK					= 0x0F << 2,
-	ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_HALT					= 0x00 << 2,
-	ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BREAKPOINT				= 0x01 << 2,
-	ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_WATCHPOINT				= 0x02 << 2,
-	ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BKPT_INSTRUCTION		= 0x03 << 2,
-	ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_EDBGRQ					= 0x04 << 2,
-	ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_VECTOR_CATCH			= 0x05 << 2,
-
-	ARM11_DSCR_STICKY_PRECISE_DATA_ABORT					= 1 << 6,
-	ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT					= 1 << 7,
-	ARM11_DSCR_INTERRUPTS_DISABLE							= 1 << 11,
-	ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE				= 1 << 13,
-	ARM11_DSCR_MODE_SELECT									= 1 << 14,
-	ARM11_DSCR_WDTR_FULL									= 1 << 29,
-	ARM11_DSCR_RDTR_FULL									= 1 << 30,
-};
-
-enum arm11_cpsr
-{
-	ARM11_CPSR_T				= 1 << 5,
-	ARM11_CPSR_J				= 1 << 24,
-};
-
-enum arm11_sc7
-{
-	ARM11_SC7_NULL				= 0,
-	ARM11_SC7_VCR				= 7,
-	ARM11_SC7_PC				= 8,
-	ARM11_SC7_BVR0				= 64,
-	ARM11_SC7_BCR0				= 80,
-	ARM11_SC7_WVR0				= 96,
-	ARM11_SC7_WCR0				= 112,
-};
-
-struct arm11_reg_state
-{
-	uint32_t				def_index;
-	struct target *			target;
+enum arm11_sc7 {
+	ARM11_SC7_NULL                          = 0,
+	ARM11_SC7_VCR                           = 7,
+	ARM11_SC7_PC                            = 8,
+	ARM11_SC7_BVR0                          = 64,
+	ARM11_SC7_BCR0                          = 80,
+	ARM11_SC7_WVR0                          = 96,
+	ARM11_SC7_WCR0                          = 112,
 };
 
-#endif /* ARM11_H */
+#endif /* OPENOCD_TARGET_ARM11_H */