X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Farm11_dbgtap.c;h=fc7a55c5ebf5e192da1f3ff13f545bdf3089cca0;hb=5eb638c71e95048b090b8a19640d7d4902c07902;hp=0e1160f8a7a105d25e560e666f3706614dcf62c3;hpb=da3196bf5e52a6d01f27cf228f87e395523cf901;p=openocd.git

diff --git a/src/target/arm11_dbgtap.c b/src/target/arm11_dbgtap.c
index 0e1160f8a7..fc7a55c5eb 100644
--- a/src/target/arm11_dbgtap.c
+++ b/src/target/arm11_dbgtap.c
@@ -940,3 +940,79 @@ int arm11_read_memory_word(arm11_common_t * arm11, uint32_t address, uint32_t *
 }
 
 
+/** Write Embedded Trace Macrocell (ETM) via Scan chain 6
+ *
+ * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0318e/Bcfddjeh.html#Bcfggcbe
+ *
+ * \param arm11		Target state variable.
+ * \param address	7 bit ETM register address
+ * \param value		Value to be written
+ *					
+ * \return			Error status
+ *
+ * \remarks			This is a stand-alone function that executes the JTAG command queue.
+ */
+int arm11_write_etm(arm11_common_t * arm11, uint8_t address, uint32_t value)
+{
+	CHECK_RETVAL(arm11_add_debug_SCAN_N(arm11, 0x06, ARM11_TAP_DEFAULT));
+
+	/* Uses INTEST for read and write */
+	arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
+
+	scan_field_t		chain6_fields[3];
+
+	uint8_t				nRW			= 1;
+
+	arm11_setup_field(arm11, 32, &value,		NULL,		chain6_fields + 0);
+	arm11_setup_field(arm11,  7, &address,		NULL,		chain6_fields + 1);
+	arm11_setup_field(arm11,  1, &nRW,			NULL,		chain6_fields + 2);
+
+	arm11_add_dr_scan_vc(asizeof(chain6_fields), chain6_fields, TAP_IDLE);
+
+	CHECK_RETVAL(jtag_execute_queue());
+
+	return ERROR_OK;
+}
+
+/** Read Embedded Trace Macrocell (ETM) via Scan chain 6
+ *
+ * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0318e/Bcfddjeh.html#Bcfggcbe
+ *
+ * \param arm11		Target state variable.
+ * \param address	7 bit ETM register address
+ * \param value		Pointer that receives value that was read
+ *					
+ * \return			Error status
+ *
+ * \remarks			This is a stand-alone function that executes the JTAG command queue.
+ */
+int arm11_read_etm(arm11_common_t * arm11, uint8_t address, uint32_t * value)
+{
+	CHECK_RETVAL(arm11_add_debug_SCAN_N(arm11, 0x06, ARM11_TAP_DEFAULT));
+
+	/* Uses INTEST for read and write */
+	arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
+
+	scan_field_t		chain6_fields[3];
+
+	uint8_t				nRW			= 0;
+
+	arm11_setup_field(arm11, 32, NULL,			NULL,		chain6_fields + 0);
+	arm11_setup_field(arm11,  7, &address,		NULL,		chain6_fields + 1);
+	arm11_setup_field(arm11,  1, &nRW,			NULL,		chain6_fields + 2);
+
+	arm11_add_dr_scan_vc(asizeof(chain6_fields), chain6_fields, TAP_IDLE);
+
+	/* Data is made available in Capture-DR and shifted out on the next access */
+
+	arm11_setup_field(arm11, 32, NULL,			value,		chain6_fields + 0);
+	arm11_setup_field(arm11,  7, &address,		NULL,		chain6_fields + 1);
+	arm11_setup_field(arm11,  1, &nRW,			NULL,		chain6_fields + 2);
+
+	arm11_add_dr_scan_vc(asizeof(chain6_fields), chain6_fields, TAP_IDLE);
+
+	CHECK_RETVAL(jtag_execute_queue());
+
+	return ERROR_OK;
+}
+