X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Farm11_dbgtap.c;h=fc7a55c5ebf5e192da1f3ff13f545bdf3089cca0;hb=a585bdf7269ce5c861c83ee3294ba1f074e9c877;hp=025c69e8ad4228263d7f8531e8379c595c7d1376;hpb=f499341558dce8a41086f5439ca0458f4ea1fbfd;p=openocd.git
diff --git a/src/target/arm11_dbgtap.c b/src/target/arm11_dbgtap.c
index 025c69e8ad..fc7a55c5eb 100644
--- a/src/target/arm11_dbgtap.c
+++ b/src/target/arm11_dbgtap.c
@@ -2,7 +2,7 @@
* Copyright (C) 2008 digenius technology GmbH. *
* Michael Bruck *
* *
- * Copyright (C) 2008 Oyvind Harboe oyvind.harboe@zylin.com *
+ * Copyright (C) 2008,2009 Oyvind Harboe oyvind.harboe@zylin.com *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
@@ -24,13 +24,14 @@
#include "config.h"
#endif
-#include "arm11.h"
+#include "arm11_dbgtap.h"
+#include "time_support.h"
#if 0
#define JTAG_DEBUG(expr ...) DEBUG(expr)
#else
-#define JTAG_DEBUG(expr ...) do {} while(0)
+#define JTAG_DEBUG(expr ...) do {} while (0)
#endif
/*
@@ -40,7 +41,7 @@ behavior of the FTDI driver IIRC was to go via RTI.
Conversely there may be other places in this code where the ARM11 code relies
on the driver to hit through RTI when coming from Update-?R.
*/
-tap_state_t arm11_move_pi_to_si_via_ci[] =
+static const tap_state_t arm11_move_pi_to_si_via_ci[] =
{
TAP_IREXIT2, TAP_IRUPDATE, TAP_DRSELECT, TAP_IRSELECT, TAP_IRCAPTURE, TAP_IRSHIFT
};
@@ -55,7 +56,7 @@ int arm11_add_ir_scan_vc(int num_fields, scan_field_t *fields, tap_state_t state
return ERROR_OK;
}
-tap_state_t arm11_move_pd_to_sd_via_cd[] =
+static const tap_state_t arm11_move_pd_to_sd_via_cd[] =
{
TAP_DREXIT2, TAP_DRUPDATE, TAP_DRSELECT, TAP_DRCAPTURE, TAP_DRSHIFT
};
@@ -75,9 +76,9 @@ int arm11_add_dr_scan_vc(int num_fields, scan_field_t *fields, tap_state_t state
* \param arm11 Target state variable.
* \param num_bits Length of the data field
* \param out_data pointer to the data that will be sent out
- * (data is read when it is added to the JTAG queue)
+ * (data is read when it is added to the JTAG queue)
* \param in_data pointer to the memory that will receive data that was clocked in
- * (data is written when the JTAG queue is executed)
+ * (data is written when the JTAG queue is executed)
* \param field target data structure that will be initialized
*/
void arm11_setup_field(arm11_common_t * arm11, int num_bits, void * out_data, void * in_data, scan_field_t * field)
@@ -97,7 +98,7 @@ void arm11_setup_field(arm11_common_t * arm11, int num_bits, void * out_data, vo
*
* \remarks This adds to the JTAG command queue but does \em not execute it.
*/
-void arm11_add_IR(arm11_common_t * arm11, u8 instr, tap_state_t state)
+void arm11_add_IR(arm11_common_t * arm11, uint8_t instr, tap_state_t state)
{
jtag_tap_t *tap;
tap = arm11->target->tap;
@@ -122,10 +123,10 @@ void arm11_add_IR(arm11_common_t * arm11, u8 instr, tap_state_t state)
* arm11_add_debug_SCAN_N().
*
*/
-static void arm11_in_handler_SCAN_N(u8 *in_value)
+static void arm11_in_handler_SCAN_N(uint8_t *in_value)
{
- /** \todo TODO: clarify why this isnt properly masked in jtag.c jtag_read_buffer() */
- u8 v = *in_value & 0x1F;
+ /** \todo TODO: clarify why this isnt properly masked in core.c jtag_read_buffer() */
+ uint8_t v = *in_value & 0x1F;
if (v != 0x10)
{
@@ -160,7 +161,7 @@ static void arm11_in_handler_SCAN_N(u8 *in_value)
* \remarks This adds to the JTAG command queue but does \em not execute it.
*/
-void arm11_add_debug_SCAN_N(arm11_common_t * arm11, u8 chain, tap_state_t state)
+int arm11_add_debug_SCAN_N(arm11_common_t * arm11, uint8_t chain, tap_state_t state)
{
JTAG_DEBUG("SCREG <= 0x%02x", chain);
@@ -168,7 +169,7 @@ void arm11_add_debug_SCAN_N(arm11_common_t * arm11, u8 chain, tap_state_t state)
scan_field_t field;
- u8 tmp[1];
+ uint8_t tmp[1];
arm11_setup_field(arm11, 5, &chain, &tmp, &field);
arm11_add_dr_scan_vc(1, &field, state == ARM11_TAP_DEFAULT ? TAP_DRPAUSE : state);
@@ -176,6 +177,8 @@ void arm11_add_debug_SCAN_N(arm11_common_t * arm11, u8 chain, tap_state_t state)
jtag_execute_queue_noclear();
arm11_in_handler_SCAN_N(tmp);
+
+ return jtag_execute_queue();
}
/** Write an instruction into the ITR register
@@ -195,7 +198,7 @@ void arm11_add_debug_SCAN_N(arm11_common_t * arm11, u8 chain, tap_state_t state)
*
* \remarks This adds to the JTAG command queue but does \em not execute it.
*/
-void arm11_add_debug_INST(arm11_common_t * arm11, u32 inst, u8 * flag, tap_state_t state)
+void arm11_add_debug_INST(arm11_common_t * arm11, uint32_t inst, uint8_t * flag, tap_state_t state)
{
JTAG_DEBUG("INST <= 0x%08x", inst);
@@ -217,13 +220,16 @@ void arm11_add_debug_INST(arm11_common_t * arm11, u32 inst, u8 * flag, tap_state
*
* \remarks This is a stand-alone function that executes the JTAG command queue.
*/
-int arm11_read_DSCR(arm11_common_t * arm11, u32 *value)
+int arm11_read_DSCR(arm11_common_t * arm11, uint32_t *value)
{
- arm11_add_debug_SCAN_N(arm11, 0x01, ARM11_TAP_DEFAULT);
+ int retval;
+ retval = arm11_add_debug_SCAN_N(arm11, 0x01, ARM11_TAP_DEFAULT);
+ if (retval != ERROR_OK)
+ return retval;
arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
- u32 dscr;
+ uint32_t dscr;
scan_field_t chain1_field;
arm11_setup_field(arm11, 32, NULL, &dscr, &chain1_field);
@@ -237,7 +243,7 @@ int arm11_read_DSCR(arm11_common_t * arm11, u32 *value)
arm11->last_dscr = dscr;
- *value=dscr;
+ *value = dscr;
return ERROR_OK;
}
@@ -251,9 +257,12 @@ int arm11_read_DSCR(arm11_common_t * arm11, u32 *value)
*
* \remarks This is a stand-alone function that executes the JTAG command queue.
*/
-int arm11_write_DSCR(arm11_common_t * arm11, u32 dscr)
+int arm11_write_DSCR(arm11_common_t * arm11, uint32_t dscr)
{
- arm11_add_debug_SCAN_N(arm11, 0x01, ARM11_TAP_DEFAULT);
+ int retval;
+ retval = arm11_add_debug_SCAN_N(arm11, 0x01, ARM11_TAP_DEFAULT);
+ if (retval != ERROR_OK)
+ return retval;
arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT);
@@ -280,7 +289,7 @@ int arm11_write_DSCR(arm11_common_t * arm11, u32 dscr)
* \return Debug reason
*
*/
-enum target_debug_reason arm11_get_DSCR_debug_reason(u32 dscr)
+enum target_debug_reason arm11_get_DSCR_debug_reason(uint32_t dscr)
{
switch (dscr & ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_MASK)
{
@@ -330,9 +339,9 @@ enum target_debug_reason arm11_get_DSCR_debug_reason(u32 dscr)
* \param arm11 Target state variable.
*
*/
-void arm11_run_instr_data_prepare(arm11_common_t * arm11)
+int arm11_run_instr_data_prepare(arm11_common_t * arm11)
{
- arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
+ return arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
}
/** Cleanup after ITR/DTR operations
@@ -349,12 +358,13 @@ void arm11_run_instr_data_prepare(arm11_common_t * arm11)
* \param arm11 Target state variable.
*
*/
-void arm11_run_instr_data_finish(arm11_common_t * arm11)
+int arm11_run_instr_data_finish(arm11_common_t * arm11)
{
- arm11_add_debug_SCAN_N(arm11, 0x00, ARM11_TAP_DEFAULT);
+ return arm11_add_debug_SCAN_N(arm11, 0x00, ARM11_TAP_DEFAULT);
}
+
/** Execute one or multiple instructions via ITR
*
* \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
@@ -364,7 +374,7 @@ void arm11_run_instr_data_finish(arm11_common_t * arm11)
* \param count Number of opcodes to execute
*
*/
-int arm11_run_instr_no_data(arm11_common_t * arm11, u32 * opcode, size_t count)
+int arm11_run_instr_no_data(arm11_common_t * arm11, uint32_t * opcode, size_t count)
{
arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT);
@@ -372,9 +382,10 @@ int arm11_run_instr_no_data(arm11_common_t * arm11, u32 * opcode, size_t count)
{
arm11_add_debug_INST(arm11, *opcode++, NULL, TAP_IDLE);
+ int i = 0;
while (1)
{
- u8 flag;
+ uint8_t flag;
arm11_add_debug_INST(arm11, 0, &flag, count ? TAP_IDLE : TAP_DRPAUSE);
@@ -382,6 +393,23 @@ int arm11_run_instr_no_data(arm11_common_t * arm11, u32 * opcode, size_t count)
if (flag)
break;
+
+ long long then = 0;
+
+ if (i == 1000)
+ {
+ then = timeval_ms();
+ }
+ if (i >= 1000)
+ {
+ if ((timeval_ms()-then) > 1000)
+ {
+ LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
+ return ERROR_FAIL;
+ }
+ }
+
+ i++;
}
}
@@ -396,9 +424,9 @@ int arm11_run_instr_no_data(arm11_common_t * arm11, u32 * opcode, size_t count)
* \param opcode ARM opcode
*
*/
-void arm11_run_instr_no_data1(arm11_common_t * arm11, u32 opcode)
+int arm11_run_instr_no_data1(arm11_common_t * arm11, uint32_t opcode)
{
- arm11_run_instr_no_data(arm11, &opcode, 1);
+ return arm11_run_instr_no_data(arm11, &opcode, 1);
}
@@ -415,7 +443,7 @@ void arm11_run_instr_no_data1(arm11_common_t * arm11, u32 opcode)
* \param count Number of data words and instruction repetitions
*
*/
-int arm11_run_instr_data_to_core(arm11_common_t * arm11, u32 opcode, u32 * data, size_t count)
+int arm11_run_instr_data_to_core(arm11_common_t * arm11, uint32_t opcode, uint32_t * data, size_t count)
{
arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT);
@@ -425,9 +453,9 @@ int arm11_run_instr_data_to_core(arm11_common_t * arm11, u32 opcode, u32 * data,
scan_field_t chain5_fields[3];
- u32 Data;
- u8 Ready;
- u8 nRetry;
+ uint32_t Data;
+ uint8_t Ready;
+ uint8_t nRetry;
arm11_setup_field(arm11, 32, &Data, NULL, chain5_fields + 0);
arm11_setup_field(arm11, 1, NULL, &Ready, chain5_fields + 1);
@@ -435,15 +463,33 @@ int arm11_run_instr_data_to_core(arm11_common_t * arm11, u32 opcode, u32 * data,
while (count--)
{
+ int i = 0;
do
{
Data = *data;
- arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, jtag_add_end_state(TAP_IDLE));
+ arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, jtag_set_end_state(TAP_IDLE));
CHECK_RETVAL(jtag_execute_queue());
JTAG_DEBUG("DTR Ready %d nRetry %d", Ready, nRetry);
+
+ long long then = 0;
+
+ if (i == 1000)
+ {
+ then = timeval_ms();
+ }
+ if (i >= 1000)
+ {
+ if ((timeval_ms()-then) > 1000)
+ {
+ LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
+ return ERROR_FAIL;
+ }
+ }
+
+ i++;
}
while (!Ready);
@@ -452,6 +498,7 @@ int arm11_run_instr_data_to_core(arm11_common_t * arm11, u32 opcode, u32 * data,
arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
+ int i = 0;
do
{
Data = 0;
@@ -461,6 +508,23 @@ int arm11_run_instr_data_to_core(arm11_common_t * arm11, u32 opcode, u32 * data,
CHECK_RETVAL(jtag_execute_queue());
JTAG_DEBUG("DTR Data %08x Ready %d nRetry %d", Data, Ready, nRetry);
+
+ long long then = 0;
+
+ if (i == 1000)
+ {
+ then = timeval_ms();
+ }
+ if (i >= 1000)
+ {
+ if ((timeval_ms()-then) > 1000)
+ {
+ LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
+ return ERROR_FAIL;
+ }
+ }
+
+ i++;
}
while (!Ready);
@@ -479,8 +543,12 @@ int arm11_run_instr_data_to_core(arm11_common_t * arm11, u32 opcode, u32 * data,
*
* To disable this code, try "memwrite burst false"
*
+ * FIX!!! should we use multiple TAP_IDLE here or not???
+ *
+ * https://lists.berlios.de/pipermail/openocd-development/2009-July/009698.html
+ * https://lists.berlios.de/pipermail/openocd-development/2009-August/009865.html
*/
-tap_state_t arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay[] =
+static const tap_state_t arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay[] =
{
TAP_DREXIT2, TAP_DRUPDATE, TAP_IDLE, TAP_IDLE, TAP_IDLE, TAP_DRSELECT, TAP_DRCAPTURE, TAP_DRSHIFT
};
@@ -502,7 +570,7 @@ tap_state_t arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay[] =
* \param count Number of data words and instruction repetitions
*
*/
-int arm11_run_instr_data_to_core_noack(arm11_common_t * arm11, u32 opcode, u32 * data, size_t count)
+int arm11_run_instr_data_to_core_noack(arm11_common_t * arm11, uint32_t opcode, uint32_t * data, size_t count)
{
arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT);
@@ -516,8 +584,17 @@ int arm11_run_instr_data_to_core_noack(arm11_common_t * arm11, u32 opcode, u32 *
arm11_setup_field(arm11, 1, NULL, NULL /*&Ready*/, chain5_fields + 1);
arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 2);
- u8 Readies[count + 1];
- u8 * ReadyPos = Readies;
+ uint8_t *Readies;
+ size_t readiesNum = (count + 1);
+ size_t bytes = sizeof(*Readies)*readiesNum;
+ Readies = (uint8_t *) malloc(bytes);
+ if (Readies == NULL)
+ {
+ LOG_ERROR("Out of memory allocating " ZU " bytes", bytes);
+ return ERROR_FAIL;
+ }
+
+ uint8_t * ReadyPos = Readies;
while (count--)
{
@@ -526,13 +603,13 @@ int arm11_run_instr_data_to_core_noack(arm11_common_t * arm11, u32 opcode, u32 *
if (count)
{
- jtag_add_dr_scan(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
+ jtag_add_dr_scan(asizeof(chain5_fields), chain5_fields, jtag_set_end_state(TAP_DRPAUSE));
jtag_add_pathmove(asizeof(arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay),
arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay);
}
else
{
- jtag_add_dr_scan(asizeof(chain5_fields), chain5_fields, jtag_add_end_state(TAP_IDLE));
+ jtag_add_dr_scan(asizeof(chain5_fields), chain5_fields, jtag_set_end_state(TAP_IDLE));
}
}
@@ -543,22 +620,27 @@ int arm11_run_instr_data_to_core_noack(arm11_common_t * arm11, u32 opcode, u32 *
arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
- CHECK_RETVAL(jtag_execute_queue());
-
- size_t error_count = 0;
-
- for (size_t i = 0; i < asizeof(Readies); i++)
+ int retval = jtag_execute_queue();
+ if (retval == ERROR_OK)
{
- if (Readies[i] != 1)
+ size_t error_count = 0;
+
+ for (size_t i = 0; i < readiesNum; i++)
{
- error_count++;
+ if (Readies[i] != 1)
+ {
+ error_count++;
+ }
}
+
+ if (error_count > 0 )
+ LOG_ERROR(ZU " words out of " ZU " not transferred", error_count, readiesNum);
+
}
- if (error_count)
- LOG_ERROR("Transfer errors " ZU, error_count);
+ free(Readies);
- return ERROR_OK;
+ return retval;
}
@@ -573,7 +655,7 @@ int arm11_run_instr_data_to_core_noack(arm11_common_t * arm11, u32 opcode, u32 *
* \param data Data word to be passed to the core via DTR
*
*/
-int arm11_run_instr_data_to_core1(arm11_common_t * arm11, u32 opcode, u32 data)
+int arm11_run_instr_data_to_core1(arm11_common_t * arm11, uint32_t opcode, uint32_t data)
{
return arm11_run_instr_data_to_core(arm11, opcode, &data, 1);
}
@@ -592,7 +674,7 @@ int arm11_run_instr_data_to_core1(arm11_common_t * arm11, u32 opcode, u32 data)
* \param count Number of data words and instruction repetitions
*
*/
-int arm11_run_instr_data_from_core(arm11_common_t * arm11, u32 opcode, u32 * data, size_t count)
+int arm11_run_instr_data_from_core(arm11_common_t * arm11, uint32_t opcode, uint32_t * data, size_t count)
{
arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT);
@@ -602,9 +684,9 @@ int arm11_run_instr_data_from_core(arm11_common_t * arm11, u32 opcode, u32 * dat
scan_field_t chain5_fields[3];
- u32 Data;
- u8 Ready;
- u8 nRetry;
+ uint32_t Data;
+ uint8_t Ready;
+ uint8_t nRetry;
arm11_setup_field(arm11, 32, NULL, &Data, chain5_fields + 0);
arm11_setup_field(arm11, 1, NULL, &Ready, chain5_fields + 1);
@@ -612,6 +694,7 @@ int arm11_run_instr_data_from_core(arm11_common_t * arm11, u32 opcode, u32 * dat
while (count--)
{
+ int i = 0;
do
{
arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, count ? TAP_IDLE : TAP_DRPAUSE);
@@ -619,6 +702,23 @@ int arm11_run_instr_data_from_core(arm11_common_t * arm11, u32 opcode, u32 * dat
CHECK_RETVAL(jtag_execute_queue());
JTAG_DEBUG("DTR Data %08x Ready %d nRetry %d", Data, Ready, nRetry);
+
+ long long then = 0;
+
+ if (i == 1000)
+ {
+ then = timeval_ms();
+ }
+ if (i >= 1000)
+ {
+ if ((timeval_ms()-then) > 1000)
+ {
+ LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
+ return ERROR_FAIL;
+ }
+ }
+
+ i++;
}
while (!Ready);
@@ -640,12 +740,17 @@ int arm11_run_instr_data_from_core(arm11_common_t * arm11, u32 opcode, u32 * dat
* \param data Pointer to a data word that receives the value from r0 after \p opcode was executed.
*
*/
-void arm11_run_instr_data_from_core_via_r0(arm11_common_t * arm11, u32 opcode, u32 * data)
+int arm11_run_instr_data_from_core_via_r0(arm11_common_t * arm11, uint32_t opcode, uint32_t * data)
{
- arm11_run_instr_no_data1(arm11, opcode);
+ int retval;
+ retval = arm11_run_instr_no_data1(arm11, opcode);
+ if (retval != ERROR_OK)
+ return retval;
/* MCR p14,0,R0,c0,c5,0 (move r0 -> wDTR -> local var) */
arm11_run_instr_data_from_core(arm11, 0xEE000E15, data, 1);
+
+ return ERROR_OK;
}
/** Load data into core via DTR then move it to r0 then
@@ -660,12 +765,19 @@ void arm11_run_instr_data_from_core_via_r0(arm11_common_t * arm11, u32 opcode, u
* \param data Data word that will be written to r0 before \p opcode is executed
*
*/
-void arm11_run_instr_data_to_core_via_r0(arm11_common_t * arm11, u32 opcode, u32 data)
+int arm11_run_instr_data_to_core_via_r0(arm11_common_t * arm11, uint32_t opcode, uint32_t data)
{
+ int retval;
/* MRC p14,0,r0,c0,c5,0 */
- arm11_run_instr_data_to_core1(arm11, 0xEE100E15, data);
+ retval = arm11_run_instr_data_to_core1(arm11, 0xEE100E15, data);
+ if (retval != ERROR_OK)
+ return retval;
- arm11_run_instr_no_data1(arm11, opcode);
+ retval = arm11_run_instr_no_data1(arm11, opcode);
+ if (retval != ERROR_OK)
+ return retval;
+
+ return ERROR_OK;
}
/** Apply reads and writes to scan chain 7
@@ -679,18 +791,22 @@ void arm11_run_instr_data_to_core_via_r0(arm11_common_t * arm11, u32 opcode, u32
*/
int arm11_sc7_run(arm11_common_t * arm11, arm11_sc7_action_t * actions, size_t count)
{
- arm11_add_debug_SCAN_N(arm11, 0x07, ARM11_TAP_DEFAULT);
+ int retval;
+
+ retval = arm11_add_debug_SCAN_N(arm11, 0x07, ARM11_TAP_DEFAULT);
+ if (retval != ERROR_OK)
+ return retval;
arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT);
scan_field_t chain7_fields[3];
- u8 nRW;
- u32 DataOut;
- u8 AddressOut;
- u8 Ready;
- u32 DataIn;
- u8 AddressIn;
+ uint8_t nRW;
+ uint32_t DataOut;
+ uint8_t AddressOut;
+ uint8_t Ready;
+ uint32_t DataIn;
+ uint8_t AddressIn;
arm11_setup_field(arm11, 1, &nRW, &Ready, chain7_fields + 0);
arm11_setup_field(arm11, 32, &DataOut, &DataIn, chain7_fields + 1);
@@ -786,7 +902,7 @@ void arm11_sc7_clear_vbw(arm11_common_t * arm11)
* \param arm11 Target state variable.
* \param value Value to be written
*/
-void arm11_sc7_set_vcr(arm11_common_t * arm11, u32 value)
+void arm11_sc7_set_vcr(arm11_common_t * arm11, uint32_t value)
{
arm11_sc7_action_t set_vcr;
@@ -807,9 +923,12 @@ void arm11_sc7_set_vcr(arm11_common_t * arm11, u32 value)
* \param result Pointer where to store result
*
*/
-int arm11_read_memory_word(arm11_common_t * arm11, u32 address, u32 * result)
+int arm11_read_memory_word(arm11_common_t * arm11, uint32_t address, uint32_t * result)
{
- arm11_run_instr_data_prepare(arm11);
+ int retval;
+ retval = arm11_run_instr_data_prepare(arm11);
+ if (retval != ERROR_OK)
+ return retval;
/* MRC p14,0,r0,c0,c5,0 (r0 = address) */
CHECK_RETVAL(arm11_run_instr_data_to_core1(arm11, 0xee100e15, address));
@@ -817,9 +936,83 @@ int arm11_read_memory_word(arm11_common_t * arm11, u32 address, u32 * result)
/* LDC p14,c5,[R0],#4 (DTR = [r0]) */
CHECK_RETVAL(arm11_run_instr_data_from_core(arm11, 0xecb05e01, result, 1));
- arm11_run_instr_data_finish(arm11);
+ return arm11_run_instr_data_finish(arm11);
+}
+
+
+/** Write Embedded Trace Macrocell (ETM) via Scan chain 6
+ *
+ * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0318e/Bcfddjeh.html#Bcfggcbe
+ *
+ * \param arm11 Target state variable.
+ * \param address 7 bit ETM register address
+ * \param value Value to be written
+ *
+ * \return Error status
+ *
+ * \remarks This is a stand-alone function that executes the JTAG command queue.
+ */
+int arm11_write_etm(arm11_common_t * arm11, uint8_t address, uint32_t value)
+{
+ CHECK_RETVAL(arm11_add_debug_SCAN_N(arm11, 0x06, ARM11_TAP_DEFAULT));
+
+ /* Uses INTEST for read and write */
+ arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
+
+ scan_field_t chain6_fields[3];
+
+ uint8_t nRW = 1;
+
+ arm11_setup_field(arm11, 32, &value, NULL, chain6_fields + 0);
+ arm11_setup_field(arm11, 7, &address, NULL, chain6_fields + 1);
+ arm11_setup_field(arm11, 1, &nRW, NULL, chain6_fields + 2);
+
+ arm11_add_dr_scan_vc(asizeof(chain6_fields), chain6_fields, TAP_IDLE);
+
+ CHECK_RETVAL(jtag_execute_queue());
return ERROR_OK;
}
+/** Read Embedded Trace Macrocell (ETM) via Scan chain 6
+ *
+ * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0318e/Bcfddjeh.html#Bcfggcbe
+ *
+ * \param arm11 Target state variable.
+ * \param address 7 bit ETM register address
+ * \param value Pointer that receives value that was read
+ *
+ * \return Error status
+ *
+ * \remarks This is a stand-alone function that executes the JTAG command queue.
+ */
+int arm11_read_etm(arm11_common_t * arm11, uint8_t address, uint32_t * value)
+{
+ CHECK_RETVAL(arm11_add_debug_SCAN_N(arm11, 0x06, ARM11_TAP_DEFAULT));
+
+ /* Uses INTEST for read and write */
+ arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
+
+ scan_field_t chain6_fields[3];
+
+ uint8_t nRW = 0;
+
+ arm11_setup_field(arm11, 32, NULL, NULL, chain6_fields + 0);
+ arm11_setup_field(arm11, 7, &address, NULL, chain6_fields + 1);
+ arm11_setup_field(arm11, 1, &nRW, NULL, chain6_fields + 2);
+
+ arm11_add_dr_scan_vc(asizeof(chain6_fields), chain6_fields, TAP_IDLE);
+
+ /* Data is made available in Capture-DR and shifted out on the next access */
+
+ arm11_setup_field(arm11, 32, NULL, value, chain6_fields + 0);
+ arm11_setup_field(arm11, 7, &address, NULL, chain6_fields + 1);
+ arm11_setup_field(arm11, 1, &nRW, NULL, chain6_fields + 2);
+
+ arm11_add_dr_scan_vc(asizeof(chain6_fields), chain6_fields, TAP_IDLE);
+
+ CHECK_RETVAL(jtag_execute_queue());
+
+ return ERROR_OK;
+}