X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Farm720t.c;h=b41fbeccc5598b0d033e8d125b76264d09d3bad5;hb=8f76ca05d998ad8bcebb3d634a09386ea8c54e5e;hp=71d4a0172bd1fb5513767b9dd4f7f4be6206c5b0;hpb=36df240cea04990e8c18aa0b90bd63374f22dbd3;p=openocd.git

diff --git a/src/target/arm720t.c b/src/target/arm720t.c
index 71d4a0172b..b41fbeccc5 100644
--- a/src/target/arm720t.c
+++ b/src/target/arm720t.c
@@ -41,7 +41,7 @@
 #endif
 
 static int arm720t_scan_cp15(struct target *target,
-		uint32_t out, uint32_t *in, int instruction, int clock)
+		uint32_t out, uint32_t *in, int instruction, int clock_arg)
 {
 	int retval;
 	struct arm720t_common *arm720t = target_to_arm720(target);
@@ -54,12 +54,11 @@ static int arm720t_scan_cp15(struct target *target,
 
 	buf_set_u32(out_buf, 0, 32, flip_u32(out, 32));
 
-	jtag_set_end_state(TAP_DRPAUSE);
-	if ((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK)
+	if ((retval = arm_jtag_scann(jtag_info, 0xf, TAP_DRPAUSE)) != ERROR_OK)
 	{
 		return retval;
 	}
-	if ((retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL)) != ERROR_OK)
+	if ((retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_DRPAUSE)) != ERROR_OK)
 	{
 		return retval;
 	}
@@ -82,7 +81,7 @@ static int arm720t_scan_cp15(struct target *target,
 		jtag_add_dr_scan(jtag_info->tap, 2, fields, TAP_DRPAUSE);
 	}
 
-	if (clock)
+	if (clock_arg)
 		jtag_add_runtest(0, TAP_DRPAUSE);
 
 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
@@ -94,9 +93,9 @@ static int arm720t_scan_cp15(struct target *target,
 	if (in)
 		LOG_DEBUG("out: %8.8x, in: %8.8x, instruction: %i, clock: %i", out, *in, instruction, clock);
 	else
-		LOG_DEBUG("out: %8.8x, instruction: %i, clock: %i", out, instruction, clock);
+		LOG_DEBUG("out: %8.8x, instruction: %i, clock: %i", out, instruction, clock_arg);
 #else
-		LOG_DEBUG("out: %8.8" PRIx32 ", instruction: %i, clock: %i", out, instruction, clock);
+		LOG_DEBUG("out: %8.8" PRIx32 ", instruction: %i, clock: %i", out, instruction, clock_arg);
 #endif
 
 	return ERROR_OK;
@@ -135,26 +134,39 @@ static int arm720t_write_cp15(struct target *target, uint32_t opcode, uint32_t v
 	return ERROR_OK;
 }
 
-static uint32_t arm720t_get_ttb(struct target *target)
+static int arm720t_get_ttb(struct target *target, uint32_t *result)
 {
 	uint32_t ttb = 0x0;
 
-	arm720t_read_cp15(target, 0xee120f10, &ttb);
-	jtag_execute_queue();
+	int retval;
+
+	retval = arm720t_read_cp15(target, 0xee120f10, &ttb);
+	if (retval != ERROR_OK)
+		return retval;
+	retval = jtag_execute_queue();
+	if (retval != ERROR_OK)
+		return retval;
 
 	ttb &= 0xffffc000;
 
-	return ttb;
+	*result = ttb;
+
+	return ERROR_OK;
 }
 
-static void arm720t_disable_mmu_caches(struct target *target,
+static int arm720t_disable_mmu_caches(struct target *target,
 		int mmu, int d_u_cache, int i_cache)
 {
 	uint32_t cp15_control;
+	int retval;
 
 	/* read cp15 control register */
-	arm720t_read_cp15(target, 0xee110f10, &cp15_control);
-	jtag_execute_queue();
+	retval = arm720t_read_cp15(target, 0xee110f10, &cp15_control);
+	if (retval != ERROR_OK)
+		return retval;
+	retval = jtag_execute_queue();
+	if (retval != ERROR_OK)
+		return retval;
 
 	if (mmu)
 		cp15_control &= ~0x1U;
@@ -162,17 +174,23 @@ static void arm720t_disable_mmu_caches(struct target *target,
 	if (d_u_cache || i_cache)
 		cp15_control &= ~0x4U;
 
-	arm720t_write_cp15(target, 0xee010f10, cp15_control);
+	retval = arm720t_write_cp15(target, 0xee010f10, cp15_control);
+	return retval;
 }
 
-static void arm720t_enable_mmu_caches(struct target *target,
+static int arm720t_enable_mmu_caches(struct target *target,
 		int mmu, int d_u_cache, int i_cache)
 {
 	uint32_t cp15_control;
+	int retval;
 
 	/* read cp15 control register */
-	arm720t_read_cp15(target, 0xee110f10, &cp15_control);
-	jtag_execute_queue();
+	retval = arm720t_read_cp15(target, 0xee110f10, &cp15_control);
+	if (retval != ERROR_OK)
+		return retval;
+	retval = jtag_execute_queue();
+	if (retval != ERROR_OK)
+		return retval;
 
 	if (mmu)
 		cp15_control |= 0x1U;
@@ -180,16 +198,22 @@ static void arm720t_enable_mmu_caches(struct target *target,
 	if (d_u_cache || i_cache)
 		cp15_control |= 0x4U;
 
-	arm720t_write_cp15(target, 0xee010f10, cp15_control);
+	retval = arm720t_write_cp15(target, 0xee010f10, cp15_control);
+	return retval;
 }
 
-static void arm720t_post_debug_entry(struct target *target)
+static int arm720t_post_debug_entry(struct target *target)
 {
 	struct arm720t_common *arm720t = target_to_arm720(target);
+	int retval;
 
 	/* examine cp15 control reg */
-	arm720t_read_cp15(target, 0xee110f10, &arm720t->cp15_control_reg);
-	jtag_execute_queue();
+	retval = arm720t_read_cp15(target, 0xee110f10, &arm720t->cp15_control_reg);
+	if (retval != ERROR_OK)
+		return retval;
+	retval = jtag_execute_queue();
+	if (retval != ERROR_OK)
+		return retval;
 	LOG_DEBUG("cp15_control_reg: %8.8" PRIx32 "", arm720t->cp15_control_reg);
 
 	arm720t->armv4_5_mmu.mmu_enabled = (arm720t->cp15_control_reg & 0x1U) ? 1 : 0;
@@ -197,9 +221,14 @@ static void arm720t_post_debug_entry(struct target *target)
 	arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
 
 	/* save i/d fault status and address register */
-	arm720t_read_cp15(target, 0xee150f10, &arm720t->fsr_reg);
-	arm720t_read_cp15(target, 0xee160f10, &arm720t->far_reg);
-	jtag_execute_queue();
+	retval = arm720t_read_cp15(target, 0xee150f10, &arm720t->fsr_reg);
+	if (retval != ERROR_OK)
+		return retval;
+	retval = arm720t_read_cp15(target, 0xee160f10, &arm720t->far_reg);
+	if (retval != ERROR_OK)
+		return retval;
+	retval = jtag_execute_queue();
+	return retval;
 }
 
 static void arm720t_pre_restore_context(struct target *target)
@@ -224,15 +253,12 @@ static int arm720t_verify_pointer(struct command_context *cmd_ctx,
 static int arm720t_arch_state(struct target *target)
 {
 	struct arm720t_common *arm720t = target_to_arm720(target);
-	struct arm *armv4_5;
 
 	static const char *state[] =
 	{
 		"disabled", "enabled"
 	};
 
-	armv4_5 = &arm720t->arm7_9_common.armv4_5_common;
-
 	arm_arch_state(target);
 	LOG_USER("MMU: %s, Cache: %s",
 			 state[arm720t->armv4_5_mmu.mmu_enabled],
@@ -255,17 +281,14 @@ static int arm720_mmu(struct target *target, int *enabled)
 static int arm720_virt2phys(struct target *target,
 		uint32_t virtual, uint32_t *physical)
 {
-	int type;
 	uint32_t cb;
-	int domain;
-	uint32_t ap;
 	struct arm720t_common *arm720t = target_to_arm720(target);
 
-	uint32_t ret = armv4_5_mmu_translate_va(target, &arm720t->armv4_5_mmu, virtual, &type, &cb, &domain, &ap);
-	if (type == -1)
-	{
-		return ret;
-	}
+	uint32_t ret;
+	int retval = armv4_5_mmu_translate_va(target,
+			&arm720t->armv4_5_mmu, virtual, &cb, &ret);
+	if (retval != ERROR_OK)
+		return retval;
 	*physical = ret;
 	return ERROR_OK;
 }
@@ -278,12 +301,19 @@ static int arm720t_read_memory(struct target *target,
 
 	/* disable cache, but leave MMU enabled */
 	if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
-		arm720t_disable_mmu_caches(target, 0, 1, 0);
-
+	{
+		retval = arm720t_disable_mmu_caches(target, 0, 1, 0);
+		if (retval != ERROR_OK)
+			return retval;
+	}
 	retval = arm7_9_read_memory(target, address, size, count, buffer);
 
 	if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
-		arm720t_enable_mmu_caches(target, 0, 1, 0);
+	{
+		retval = arm720t_enable_mmu_caches(target, 0, 1, 0);
+		if (retval != ERROR_OK)
+			return retval;
+	}
 
 	return retval;
 }
@@ -297,7 +327,7 @@ static int arm720t_read_phys_memory(struct target *target,
 }
 
 static int arm720t_write_phys_memory(struct target *target,
-		uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
+		uint32_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
 {
 	struct arm720t_common *arm720t = target_to_arm720(target);
 
@@ -363,7 +393,9 @@ static int arm720t_soft_reset_halt(struct target *target)
 	armv4_5->pc->dirty = 1;
 	armv4_5->pc->valid = 1;
 
-	arm720t_disable_mmu_caches(target, 1, 1, 1);
+	retval = arm720t_disable_mmu_caches(target, 1, 1, 1);
+	if (retval != ERROR_OK)
+		return retval;
 	arm720t->armv4_5_mmu.mmu_enabled = 0;
 	arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
 	arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
@@ -431,13 +463,11 @@ COMMAND_HANDLER(arm720t_handle_cp15_command)
 	int retval;
 	struct target *target = get_current_target(CMD_CTX);
 	struct arm720t_common *arm720t = target_to_arm720(target);
-	struct arm_jtag *jtag_info;
 
 	retval = arm720t_verify_pointer(CMD_CTX, arm720t);
 	if (retval != ERROR_OK)
 		return retval;
 
-	jtag_info = &arm720t->arm7_9_common.jtag_info;
 
 	if (target->state != TARGET_HALTED)
 	{