X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Farm7_9_common.c;h=106b95db1c599d9cf8de25eb03eab6a61ed501a7;hb=a0647227439434c4a71470e336ec8715d43d0501;hp=5c91e9c3711a41b1e1e08a950713e33198e1c0c3;hpb=408e1d86a035d9f3694e0c9c5b86a30c85fd0249;p=openocd.git

diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index 5c91e9c371..106b95db1c 100644
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -733,8 +733,18 @@ int arm7_9_poll(target_t *target)
 	return ERROR_OK;
 }
 
+/*
+  Some -S targets (ARM966E-S in the STR912 isn't affected, ARM926EJ-S
+  in the LPC3180 and AT91SAM9260 is affected) completely stop the JTAG clock
+  while the core is held in reset(SRST). It isn't possible to program the halt
+  condition once reset was asserted, hence a hook that allows the target to set
+  up its reset-halt condition prior to asserting reset.
+*/
+
 int arm7_9_assert_reset(target_t *target)
 {
+	armv4_5_common_t *armv4_5 = target->arch_info;
+	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 	LOG_DEBUG("target->state: %s", target_state_strings[target->state]);
 	
 	if (!(jtag_reset_config & RESET_HAS_SRST))
@@ -742,20 +752,40 @@ int arm7_9_assert_reset(target_t *target)
 		LOG_ERROR("Can't assert SRST");
 		return ERROR_FAIL;
 	}
-	
-	if (target->state == TARGET_HALTED || target->state == TARGET_UNKNOWN)
+
+	if ((target->reset_mode == RESET_HALT) || (target->reset_mode == RESET_INIT))
 	{
-		/* if the target wasn't running, there might be working areas allocated */
-		target_free_all_working_areas(target);
-		
-		/* assert SRST and TRST */
-		/* system would get ouf sync if we didn't reset test-logic, too */
-		jtag_add_reset(1, 1);
-		
-		jtag_add_sleep(5000);
+		reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
 		
+		/* program EmbeddedICE Debug Control Register to deassert DBGRQ
+		 * i.e. resume.
+		 */
+		buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);	
+		embeddedice_store_reg(dbg_ctrl);
+
+		/*
+		 * Some targets do not support communication while SRST is asserted. We need to
+		 * set up the reset vector catch here.
+		 * 
+		 * If TRST is asserted, then these settings will be reset anyway, so setting them
+		 * here is harmless.  
+		 */
+		if (arm7_9->has_vector_catch)
+		{
+			/* program vector catch register to catch reset vector */
+			embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH], 0x1);
+		}
+		else
+		{
+			/* program watchpoint unit to match on reset vector address */
+			embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0x3);
+			embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0x0);
+			embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x100);
+			embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xf7);
+		}
 	}
-	
+
+	/* here we should issue a srst only, but we may have to assert trst as well */
 	if (jtag_reset_config & RESET_SRST_PULLS_TRST)
 	{
 		jtag_add_reset(1, 1);
@@ -764,9 +794,10 @@ int arm7_9_assert_reset(target_t *target)
 		jtag_add_reset(0, 1);
 	}
 	
+
 	target->state = TARGET_RESET;
 	jtag_add_sleep(50000);
-	
+
 	armv4_5_invalidate_core_regs(target);
 
 	return ERROR_OK;
@@ -906,35 +937,6 @@ int arm7_9_soft_reset_halt(struct target_s *target)
 	return ERROR_OK;
 }
 
-int arm7_9_prepare_reset_halt(target_t *target)
-{
-	armv4_5_common_t *armv4_5 = target->arch_info;
-	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
-	
-	/* poll the target, and resume if it was currently halted */
-	arm7_9_poll(target);
-	if (target->state == TARGET_HALTED)
-	{
-		arm7_9_resume(target, 1, 0x0, 0, 1);
-	}
-	
-	if (arm7_9->has_vector_catch)
-	{
-		/* program vector catch register to catch reset vector */
-		embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH], 0x1);
-	}
-	else
-	{
-		/* program watchpoint unit to match on reset vector address */
-		embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0x3);
-		embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0x0);
-		embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x100);
-		embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xf7);
-	}
-	
-	return ERROR_OK;
-}
-
 int arm7_9_halt(target_t *target)
 {
 	armv4_5_common_t *armv4_5 = target->arch_info;
@@ -945,7 +947,7 @@ int arm7_9_halt(target_t *target)
 	
 	if (target->state == TARGET_HALTED)
 	{
-		LOG_WARNING("target was already halted");
+		LOG_DEBUG("target was already halted");
 		return ERROR_OK;
 	}