X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Farm7_9_common.c;h=12ee62f94d887f88763dbf047893b0d6183628f8;hb=ebd3f88798902be229d00f95ece5ba250db8efba;hp=72c67490a19836235adef73413f429d841144c8b;hpb=da34c09128842dda70b5076bfc927b783cf126d5;p=openocd.git diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c index 72c67490a1..12ee62f94d 100644 --- a/src/target/arm7_9_common.c +++ b/src/target/arm7_9_common.c @@ -50,6 +50,12 @@ int handle_arm7_9_fast_memory_access_command(struct command_context_s *cmd_ctx, int handle_arm7_9_dcc_downloads_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); int handle_arm7_9_etm_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); +/** + * Clear watchpoints for an ARM7/9 target. + * + * @param arm7_9 Pointer to the common struct for an ARM7/9 target + * @return JTAG error status after executing queue + */ static int arm7_9_clear_watchpoints(arm7_9_common_t *arm7_9) { embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0); @@ -62,6 +68,13 @@ static int arm7_9_clear_watchpoints(arm7_9_common_t *arm7_9) return jtag_execute_queue(); } +/** + * Assign a watchpoint to one of the two available hardware comparators in an + * ARM7 or ARM9 target. + * + * @param arm7_9 Pointer to the common struct for an ARM7/9 target + * @param breakpoint Pointer to the breakpoint to be used as a watchpoint + */ static void arm7_9_assign_wp(arm7_9_common_t *arm7_9, breakpoint_t *breakpoint) { if (!arm7_9->wp0_used) @@ -82,7 +95,13 @@ static void arm7_9_assign_wp(arm7_9_common_t *arm7_9, breakpoint_t *breakpoint) } } -/* set up embedded ice registers */ +/** + * Setup an ARM7/9 target's embedded ICE registers for software breakpoints. + * + * @param arm7_9 Pointer to common struct for ARM7/9 targets + * @return Error codes if there is a problem finding a watchpoint or the result + * of executing the JTAG queue + */ static int arm7_9_set_software_breakpoints(arm7_9_common_t *arm7_9) { if (arm7_9->sw_breakpoints_added) @@ -137,7 +156,12 @@ static int arm7_9_set_software_breakpoints(arm7_9_common_t *arm7_9) return jtag_execute_queue(); } -/* set things up after a reset / on startup */ +/** + * Setup the common pieces for an ARM7/9 target after reset or on startup. + * + * @param target Pointer to an ARM7/9 target to setup + * @return Result of clearing the watchpoints on the target + */ int arm7_9_setup(target_t *target) { armv4_5_common_t *armv4_5 = target->arch_info; @@ -146,6 +170,18 @@ int arm7_9_setup(target_t *target) return arm7_9_clear_watchpoints(arm7_9); } +/** + * Retrieves the architecture information pointers for ARMv4/5 and ARM7/9 + * targets. A return of ERROR_OK signifies that the target is a valid target + * and that the pointers have been set properly. + * + * @param target Pointer to the target device to get the pointers from + * @param armv4_5_p Pointer to be filled in with the common struct for ARMV4/5 + * targets + * @param arm7_9_p Pointer to be filled in with the common struct for ARM7/9 + * targets + * @return ERROR_OK if successful + */ int arm7_9_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p) { armv4_5_common_t *armv4_5 = target->arch_info; @@ -167,8 +203,16 @@ int arm7_9_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm return ERROR_OK; } -/* we set up the breakpoint even if it is already set. Some action, e.g. reset - * might have erased the values in embedded ice +/** + * Set either a hardware or software breakpoint on an ARM7/9 target. The + * breakpoint is set up even if it is already set. Some actions, e.g. reset, + * might have erased the values in Embedded ICE. + * + * @param target Pointer to the target device to set the breakpoints on + * @param breakpoint Pointer to the breakpoint to be set + * @return For hardware breakpoints, this is the result of executing the JTAG + * queue. For software breakpoints, this will be the status of the + * required memory reads and writes */ int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) { @@ -280,6 +324,18 @@ int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) return retval; } +/** + * Unsets an existing breakpoint on an ARM7/9 target. If it is a hardware + * breakpoint, the watchpoint used will be freed and the Embedded ICE registers + * will be updated. Otherwise, the software breakpoint will be restored to its + * original instruction if it hasn't already been modified. + * + * @param target Pointer to ARM7/9 target to unset the breakpoint from + * @param breakpoint Pointer to breakpoint to be unset + * @return For hardware breakpoints, this is the result of executing the JTAG + * queue. For software breakpoints, this will be the status of the + * required memory reads and writes + */ int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint) { int retval = ERROR_OK; @@ -347,6 +403,15 @@ int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint) return retval; } +/** + * Add a breakpoint to an ARM7/9 target. This makes sure that there are no + * dangling breakpoints and that the desired breakpoint can be added. + * + * @param target Pointer to the target ARM7/9 device to add a breakpoint to + * @param breakpoint Pointer to the breakpoint to be added + * @return An error status if there is a problem adding the breakpoint or the + * result of setting the breakpoint + */ int arm7_9_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint) { armv4_5_common_t *armv4_5 = target->arch_info; @@ -388,6 +453,16 @@ int arm7_9_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint) return arm7_9_set_breakpoint(target, breakpoint); } +/** + * Removes a breakpoint from an ARM7/9 target. This will make sure there are no + * dangling breakpoints and updates available watchpoints if it is a hardware + * breakpoint. + * + * @param target Pointer to the target to have a breakpoint removed + * @param breakpoint Pointer to the breakpoint to be removed + * @return Error status if there was a problem unsetting the breakpoint or the + * watchpoints could not be cleared + */ int arm7_9_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint) { int retval = ERROR_OK; @@ -415,6 +490,16 @@ int arm7_9_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint) return ERROR_OK; } +/** + * Sets a watchpoint for an ARM7/9 target in one of the watchpoint units. It is + * considered a bug to call this function when there are no available watchpoint + * units. + * + * @param target Pointer to an ARM7/9 target to set a watchpoint on + * @param watchpoint Pointer to the watchpoint to be set + * @return Error status if watchpoint set fails or the result of executing the + * JTAG queue + */ int arm7_9_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint) { int retval = ERROR_OK; @@ -479,6 +564,14 @@ int arm7_9_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint) return ERROR_OK; } +/** + * Unset an existing watchpoint and clear the used watchpoint unit. + * + * @param target Pointer to the target to have the watchpoint removed + * @param watchpoint Pointer to the watchpoint to be removed + * @return Error status while trying to unset the watchpoint or the result of + * executing the JTAG queue + */ int arm7_9_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint) { int retval = ERROR_OK; @@ -520,6 +613,14 @@ int arm7_9_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint) return ERROR_OK; } +/** + * Add a watchpoint to an ARM7/9 target. If there are no watchpoint units + * available, an error response is returned. + * + * @param target Pointer to the ARM7/9 target to add a watchpoint to + * @param watchpoint Pointer to the watchpoint to be added + * @return Error status while trying to add the watchpoint + */ int arm7_9_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint) { armv4_5_common_t *armv4_5 = target->arch_info; @@ -546,6 +647,14 @@ int arm7_9_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint) return ERROR_OK; } +/** + * Remove a watchpoint from an ARM7/9 target. The watchpoint will be unset and + * the used watchpoint unit will be reopened. + * + * @param target Pointer to the target to remove a watchpoint from + * @param watchpoint Pointer to the watchpoint to be removed + * @return Result of trying to unset the watchpoint + */ int arm7_9_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint) { int retval = ERROR_OK; @@ -565,6 +674,15 @@ int arm7_9_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint) return ERROR_OK; } +/** + * Restarts the target by sending a RESTART instruction and moving the JTAG + * state to IDLE. This includes a timeout waiting for DBGACK and SYSCOMP to be + * asserted by the processor. + * + * @param target Pointer to target to issue commands to + * @return Error status if there is a timeout or a problem while executing the + * JTAG queue + */ int arm7_9_execute_sys_speed(struct target_s *target) { int retval; @@ -610,6 +728,14 @@ int arm7_9_execute_sys_speed(struct target_s *target) return ERROR_OK; } +/** + * Restarts the target by sending a RESTART instruction and moving the JTAG + * state to IDLE. This validates that DBGACK and SYSCOMP are set without + * waiting until they are. + * + * @param target Pointer to the target to issue commands to + * @return Always ERROR_OK + */ int arm7_9_execute_fast_sys_speed(struct target_s *target) { static int set=0; @@ -642,11 +768,19 @@ int arm7_9_execute_fast_sys_speed(struct target_s *target) } /* read debug status register */ - embeddedice_read_reg_w_check(dbg_stat, check_value, check_value); + embeddedice_read_reg_w_check(dbg_stat, check_value, check_mask); return ERROR_OK; } +/** + * Get some data from the ARM7/9 target. + * + * @param target Pointer to the ARM7/9 target to read data from + * @param size The number of 32bit words to be read + * @param buffer Pointer to the buffer that will hold the data + * @return The result of receiving data from the Embedded ICE unit + */ int arm7_9_target_request_data(target_t *target, u32 size, u8 *buffer) { armv4_5_common_t *armv4_5 = target->arch_info; @@ -660,6 +794,7 @@ int arm7_9_target_request_data(target_t *target, u32 size, u8 *buffer) retval = embeddedice_receive(jtag_info, data, size); + /* return the 32-bit ints in the 8-bit array */ for (i = 0; i < size; i++) { h_u32_to_le(buffer + (i * 4), data[i]); @@ -670,6 +805,15 @@ int arm7_9_target_request_data(target_t *target, u32 size, u8 *buffer) return retval; } +/** + * Handles requests to an ARM7/9 target. If debug messaging is enabled, the + * target is running and the DCC control register has the W bit high, this will + * execute the request on the target. + * + * @param priv Void pointer expected to be a target_t pointer + * @return ERROR_OK unless there are issues with the JTAG queue or when reading + * from the Embedded ICE unit + */ int arm7_9_handle_target_request(void *priv) { int retval = ERROR_OK; @@ -712,6 +856,26 @@ int arm7_9_handle_target_request(void *priv) return ERROR_OK; } +/** + * Polls an ARM7/9 target for its current status. If DBGACK is set, the target + * is manipulated to the right halted state based on its current state. This is + * what happens: + * + * + * + * + * + * + * + *
StateAction
TARGET_RUNNING | TARGET_RESETEnters debug mode. If TARGET_RESET, pc may be checked
TARGET_UNKNOWNWarning is logged
TARGET_DEBUG_RUNNINGEnters debug mode
TARGET_HALTEDNothing
+ * + * If the target does not end up in the halted state, a warning is produced. If + * DBGACK is cleared, then the target is expected to either be running or + * running in debug. + * + * @param target Pointer to the ARM7/9 target to poll + * @return ERROR_OK or an error status if a command fails + */ int arm7_9_poll(target_t *target) { int retval; @@ -781,7 +945,7 @@ int arm7_9_poll(target_t *target) } if (target->state != TARGET_HALTED) { - LOG_WARNING("DBGACK set, but the target did not end up in the halted stated %d", target->state); + LOG_WARNING("DBGACK set, but the target did not end up in the halted state %d", target->state); } } else @@ -793,14 +957,17 @@ int arm7_9_poll(target_t *target) return ERROR_OK; } -/* - Some -S targets (ARM966E-S in the STR912 isn't affected, ARM926EJ-S - in the LPC3180 and AT91SAM9260 is affected) completely stop the JTAG clock - while the core is held in reset(SRST). It isn't possible to program the halt - condition once reset was asserted, hence a hook that allows the target to set - up its reset-halt condition prior to asserting reset. -*/ - +/** + * Asserts the reset (SRST) on an ARM7/9 target. Some -S targets (ARM966E-S in + * the STR912 isn't affected, ARM926EJ-S in the LPC3180 and AT91SAM9260 is + * affected) completely stop the JTAG clock while the core is held in reset + * (SRST). It isn't possible to program the halt condition once reset is + * asserted, hence a hook that allows the target to set up its reset-halt + * condition is setup prior to asserting reset. + * + * @param target Pointer to an ARM7/9 target to assert reset on + * @return ERROR_FAIL if the JTAG device does not have SRST, otherwise ERROR_OK + */ int arm7_9_assert_reset(target_t *target) { armv4_5_common_t *armv4_5 = target->arch_info; @@ -839,7 +1006,7 @@ int arm7_9_assert_reset(target_t *target) } } - /* here we should issue a srst only, but we may have to assert trst as well */ + /* here we should issue an SRST only, but we may have to assert TRST as well */ if (jtag_reset_config & RESET_SRST_PULLS_TRST) { jtag_add_reset(1, 1); @@ -862,6 +1029,15 @@ int arm7_9_assert_reset(target_t *target) return ERROR_OK; } +/** + * Deassert the reset (SRST) signal on an ARM7/9 target. If SRST pulls TRST + * and the target is being reset into a halt, a warning will be triggered + * because it is not possible to reset into a halted mode in this case. The + * target is halted using the target's functions. + * + * @param target Pointer to the target to have the reset deasserted + * @return ERROR_OK or an error from polling or halting the target + */ int arm7_9_deassert_reset(target_t *target) { int retval=ERROR_OK; @@ -892,6 +1068,15 @@ int arm7_9_deassert_reset(target_t *target) return retval; } +/** + * Clears the halt condition for an ARM7/9 target. If it isn't coming out of + * reset and if DBGRQ is used, it is progammed to be deasserted. If the reset + * vector catch was used, it is restored. Otherwise, the control value is + * restored and the watchpoint unit is restored if it was in use. + * + * @param target Pointer to the ARM7/9 target to have halt cleared + * @return Always ERROR_OK + */ int arm7_9_clear_halt(target_t *target) { armv4_5_common_t *armv4_5 = target->arch_info; @@ -940,6 +1125,16 @@ int arm7_9_clear_halt(target_t *target) return ERROR_OK; } +/** + * Issue a software reset and halt to an ARM7/9 target. The target is halted + * and then there is a wait until the processor shows the halt. This wait can + * timeout and results in an error being returned. The software reset involves + * clearing the halt, updating the debug control register, changing to ARM mode, + * reset of the program counter, and reset of all of the registers. + * + * @param target Pointer to the ARM7/9 target to be reset and halted by software + * @return Error status if any of the commands fail, otherwise ERROR_OK + */ int arm7_9_soft_reset_halt(struct target_s *target) { armv4_5_common_t *armv4_5 = target->arch_info; @@ -1037,6 +1232,15 @@ int arm7_9_soft_reset_halt(struct target_s *target) return ERROR_OK; } +/** + * Halt an ARM7/9 target. This is accomplished by either asserting the DBGRQ + * line or by programming a watchpoint to trigger on any address. It is + * considered a bug to call this function while the target is in the + * TARGET_RESET state. + * + * @param target Pointer to the ARM7/9 target to be halted + * @return Always ERROR_OK + */ int arm7_9_halt(target_t *target) { if (target->state==TARGET_RESET) @@ -1089,6 +1293,17 @@ int arm7_9_halt(target_t *target) return ERROR_OK; } +/** + * Handle an ARM7/9 target's entry into debug mode. The halt is cleared on the + * ARM. The JTAG queue is then executed and the reason for debug entry is + * examined. Once done, the target is verified to be halted and the processor + * is forced into ARM mode. The core registers are saved for the current core + * mode and the program counter (register 15) is updated as needed. The core + * registers and CPSR and SPSR are saved for restoration later. + * + * @param target Pointer to target that is entering debug mode + * @return Error code if anything fails, otherwise ERROR_OK + */ int arm7_9_debug_entry(target_t *target) { int i; @@ -1250,6 +1465,15 @@ int arm7_9_debug_entry(target_t *target) return ERROR_OK; } +/** + * Validate the full context for an ARM7/9 target in all processor modes. If + * there are any invalid registers for the target, they will all be read. This + * includes the PSR. + * + * @param target Pointer to the ARM7/9 target to capture the full context from + * @return Error if the target is not halted, has an invalid core mode, or if + * the JTAG queue fails to execute + */ int arm7_9_full_context(target_t *target) { int i; @@ -1331,6 +1555,18 @@ int arm7_9_full_context(target_t *target) return ERROR_OK; } +/** + * Restore the processor context on an ARM7/9 target. The full processor + * context is analyzed to see if any of the registers are dirty on this end, but + * have a valid new value. If this is the case, the processor is changed to the + * appropriate mode and the new register values are written out to the + * processor. If there happens to be a dirty register with an invalid value, an + * error will be logged. + * + * @param target Pointer to the ARM7/9 target to have its context restored + * @return Error status if the target is not halted or the core mode in the + * armv4_5 struct is invalid. + */ int arm7_9_restore_context(target_t *target) { armv4_5_common_t *armv4_5 = target->arch_info; @@ -1473,6 +1709,14 @@ int arm7_9_restore_context(target_t *target) return ERROR_OK; } +/** + * Restart the core of an ARM7/9 target. A RESTART command is sent to the + * instruction register and the JTAG state is set to TAP_IDLE causing a core + * restart. + * + * @param target Pointer to the ARM7/9 target to be restarted + * @return Result of executing the JTAG queue + */ int arm7_9_restart_core(struct target_s *target) { armv4_5_common_t *armv4_5 = target->arch_info; @@ -1491,6 +1735,12 @@ int arm7_9_restart_core(struct target_s *target) return jtag_execute_queue(); } +/** + * Enable the watchpoints on an ARM7/9 target. The target's watchpoints are + * iterated through and are set on the target if they aren't already set. + * + * @param target Pointer to the ARM7/9 target to enable watchpoints on + */ void arm7_9_enable_watchpoints(struct target_s *target) { watchpoint_t *watchpoint = target->watchpoints; @@ -1503,6 +1753,12 @@ void arm7_9_enable_watchpoints(struct target_s *target) } } +/** + * Enable the breakpoints on an ARM7/9 target. The target's breakpoints are + * iterated through and are set on the target. + * + * @param target Pointer to the ARM7/9 target to enable breakpoints on + */ void arm7_9_enable_breakpoints(struct target_s *target) { breakpoint_t *breakpoint = target->breakpoints;