X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Farm7_9_common.c;h=a77004e707a5789a6cf35b1e64c9f87a9292a98e;hb=15f546e92fae1e468ba62e75039f28841cdc2c89;hp=e5969806148bc6dbe367d23b3338421ec4110125;hpb=0df5d1eb3c3a640c34de52787c4a70c07b53535f;p=openocd.git diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c index e596980614..a77004e707 100644 --- a/src/target/arm7_9_common.c +++ b/src/target/arm7_9_common.c @@ -2,7 +2,7 @@ * Copyright (C) 2005 by Dominic Rath * * Dominic.Rath@gmx.de * * * - * Copyright (C) 2007,2008 Øyvind Harboe * + * Copyright (C) 2007-2010 Øyvind Harboe * * oyvind.harboe@zylin.com * * * * Copyright (C) 2008 by Spencer Oliver * @@ -11,6 +11,8 @@ * Copyright (C) 2008 by Hongtao Zheng * * hontor@126.com * * * + * Copyright (C) 2009 by David Brownell * + * * * This program is free software; you can redistribute it and/or modify * * it under the terms of the GNU General Public License as published by * * the Free Software Foundation; either version 2 of the License, or * @@ -182,7 +184,7 @@ static int arm7_9_set_software_breakpoints(struct arm7_9_common *arm7_9) * @param target Pointer to an ARM7/9 target to setup * @return Result of clearing the watchpoints on the target */ -int arm7_9_setup(struct target *target) +static int arm7_9_setup(struct target *target) { struct arm7_9_common *arm7_9 = target_to_arm7_9(target); @@ -200,7 +202,7 @@ int arm7_9_setup(struct target *target) * queue. For software breakpoints, this will be the status of the * required memory reads and writes */ -int arm7_9_set_breakpoint(struct target *target, struct breakpoint *breakpoint) +static int arm7_9_set_breakpoint(struct target *target, struct breakpoint *breakpoint) { struct arm7_9_common *arm7_9 = target_to_arm7_9(target); int retval = ERROR_OK; @@ -329,7 +331,7 @@ int arm7_9_set_breakpoint(struct target *target, struct breakpoint *breakpoint) * queue. For software breakpoints, this will be the status of the * required memory reads and writes */ -int arm7_9_unset_breakpoint(struct target *target, struct breakpoint *breakpoint) +static int arm7_9_unset_breakpoint(struct target *target, struct breakpoint *breakpoint) { int retval = ERROR_OK; struct arm7_9_common *arm7_9 = target_to_arm7_9(target); @@ -375,6 +377,7 @@ int arm7_9_unset_breakpoint(struct target *target, struct breakpoint *breakpoint { return retval; } + current_instr = target_buffer_get_u32(target, (uint8_t *)¤t_instr); if (current_instr == arm7_9->arm_bkpt) if ((retval = target_write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK) { @@ -389,6 +392,7 @@ int arm7_9_unset_breakpoint(struct target *target, struct breakpoint *breakpoint { return retval; } + current_instr = target_buffer_get_u16(target, (uint8_t *)¤t_instr); if (current_instr == arm7_9->thumb_bkpt) if ((retval = target_write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK) { @@ -504,7 +508,7 @@ int arm7_9_remove_breakpoint(struct target *target, struct breakpoint *breakpoin * @return Error status if watchpoint set fails or the result of executing the * JTAG queue */ -int arm7_9_set_watchpoint(struct target *target, struct watchpoint *watchpoint) +static int arm7_9_set_watchpoint(struct target *target, struct watchpoint *watchpoint) { int retval = ERROR_OK; struct arm7_9_common *arm7_9 = target_to_arm7_9(target); @@ -575,7 +579,7 @@ int arm7_9_set_watchpoint(struct target *target, struct watchpoint *watchpoint) * @return Error status while trying to unset the watchpoint or the result of * executing the JTAG queue */ -int arm7_9_unset_watchpoint(struct target *target, struct watchpoint *watchpoint) +static int arm7_9_unset_watchpoint(struct target *target, struct watchpoint *watchpoint) { int retval = ERROR_OK; struct arm7_9_common *arm7_9 = target_to_arm7_9(target); @@ -685,12 +689,15 @@ int arm7_9_execute_sys_speed(struct target *target) struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; /* set RESTART instruction */ - jtag_set_end_state(TAP_IDLE); if (arm7_9->need_bypass_before_restart) { arm7_9->need_bypass_before_restart = 0; - arm_jtag_set_instr(jtag_info, 0xf, NULL); + retval = arm_jtag_set_instr(jtag_info, 0xf, NULL, TAP_IDLE); + if (retval != ERROR_OK) + return retval; } - arm_jtag_set_instr(jtag_info, 0x4, NULL); + retval = arm_jtag_set_instr(jtag_info, 0x4, NULL, TAP_IDLE); + if (retval != ERROR_OK) + return retval; long long then = timeval_ms(); int timeout; @@ -728,7 +735,7 @@ int arm7_9_execute_sys_speed(struct target *target) * @param target Pointer to the target to issue commands to * @return Always ERROR_OK */ -int arm7_9_execute_fast_sys_speed(struct target *target) +static int arm7_9_execute_fast_sys_speed(struct target *target) { static int set = 0; static uint8_t check_value[4], check_mask[4]; @@ -736,14 +743,18 @@ int arm7_9_execute_fast_sys_speed(struct target *target) struct arm7_9_common *arm7_9 = target_to_arm7_9(target); struct arm_jtag *jtag_info = &arm7_9->jtag_info; struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; + int retval; /* set RESTART instruction */ - jtag_set_end_state(TAP_IDLE); if (arm7_9->need_bypass_before_restart) { arm7_9->need_bypass_before_restart = 0; - arm_jtag_set_instr(jtag_info, 0xf, NULL); + retval = arm_jtag_set_instr(jtag_info, 0xf, NULL, TAP_IDLE); + if (retval != ERROR_OK) + return retval; } - arm_jtag_set_instr(jtag_info, 0x4, NULL); + retval = arm_jtag_set_instr(jtag_info, 0x4, NULL, TAP_IDLE); + if (retval != ERROR_OK) + return retval; if (!set) { @@ -804,7 +815,7 @@ int arm7_9_target_request_data(struct target *target, uint32_t size, uint8_t *bu * @return ERROR_OK unless there are issues with the JTAG queue or when reading * from the Embedded ICE unit */ -int arm7_9_handle_target_request(void *priv) +static int arm7_9_handle_target_request(void *priv) { int retval = ERROR_OK; struct target *target = priv; @@ -941,14 +952,16 @@ int arm7_9_poll(struct target *target) int arm7_9_assert_reset(struct target *target) { struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + enum reset_types jtag_reset_config = jtag_get_reset_config(); + bool use_event = false; LOG_DEBUG("target->state: %s", target_state_name(target)); - enum reset_types jtag_reset_config = jtag_get_reset_config(); - if (!(jtag_reset_config & RESET_HAS_SRST)) - { - LOG_ERROR("Can't assert SRST"); + if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT)) + use_event = true; + else if (!(jtag_reset_config & RESET_HAS_SRST)) { + LOG_ERROR("%s: how to reset?", target_name(target)); return ERROR_FAIL; } @@ -963,7 +976,8 @@ int arm7_9_assert_reset(struct target *target) */ bool srst_asserted = false; - if (((jtag_reset_config & RESET_SRST_PULLS_TRST) == 0) + if (!use_event + && !(jtag_reset_config & RESET_SRST_PULLS_TRST) && (jtag_reset_config & RESET_SRST_NO_GATING)) { jtag_add_reset(0, 1); @@ -973,48 +987,70 @@ int arm7_9_assert_reset(struct target *target) if (target->reset_halt) { /* - * Some targets do not support communication while SRST is asserted. We need to - * set up the reset vector catch here. + * For targets that don't support communication while SRST is + * asserted, we need to set up the reset vector catch first. * - * If TRST is asserted, then these settings will be reset anyway, so setting them - * here is harmless. + * When we use TRST+SRST and that's equivalent to a power-up + * reset, these settings may well be reset anyway; so setting + * them here won't matter. */ if (arm7_9->has_vector_catch) { - /* program vector catch register to catch reset vector */ - embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH], 0x1); + /* program vector catch register to catch reset */ + embeddedice_write_reg(&arm7_9->eice_cache + ->reg_list[EICE_VEC_CATCH], 0x1); - /* extra runtest added as issues were found with certain ARM9 cores (maybe more) - AT91SAM9260 and STR9 */ - jtag_add_runtest(1, jtag_get_end_state()); + /* extra runtest added as issues were found with + * certain ARM9 cores (maybe more) - AT91SAM9260 + * and STR9 + */ + jtag_add_runtest(1, TAP_IDLE); } else { - /* program watchpoint unit to match on reset vector address */ - embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], 0x0); - embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0x3); - embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff); - embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE); - embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff); + /* program watchpoint unit to match on reset vector + * address + */ + embeddedice_write_reg(&arm7_9->eice_cache + ->reg_list[EICE_W0_ADDR_VALUE], 0x0); + embeddedice_write_reg(&arm7_9->eice_cache + ->reg_list[EICE_W0_ADDR_MASK], 0x3); + embeddedice_write_reg(&arm7_9->eice_cache + ->reg_list[EICE_W0_DATA_MASK], + 0xffffffff); + embeddedice_write_reg(&arm7_9->eice_cache + ->reg_list[EICE_W0_CONTROL_VALUE], + EICE_W_CTRL_ENABLE); + embeddedice_write_reg(&arm7_9->eice_cache + ->reg_list[EICE_W0_CONTROL_MASK], + ~EICE_W_CTRL_nOPC & 0xff); } } - /* here we should issue an SRST only, but we may have to assert TRST as well */ - if (jtag_reset_config & RESET_SRST_PULLS_TRST) - { - jtag_add_reset(1, 1); - } else if (!srst_asserted) - { - jtag_add_reset(0, 1); + if (use_event) { + target_handle_event(target, TARGET_EVENT_RESET_ASSERT); + } else { + /* If we use SRST ... we'd like to issue just SRST, but the + * board or chip may be set up so we have to assert TRST as + * well. On some chips that combination is equivalent to a + * power-up reset, and generally clobbers EICE state. + */ + if (jtag_reset_config & RESET_SRST_PULLS_TRST) + jtag_add_reset(1, 1); + else if (!srst_asserted) + jtag_add_reset(0, 1); + jtag_add_sleep(50000); } target->state = TARGET_RESET; - jtag_add_sleep(50000); - - register_cache_invalidate(arm7_9->armv4_5_common.core_cache); + register_cache_invalidate(arm7_9->arm.core_cache); - if ((target->reset_halt) && ((jtag_reset_config & RESET_SRST_PULLS_TRST) == 0)) + /* REVISIT why isn't standard debug entry logic sufficient?? */ + if (target->reset_halt + && (!(jtag_reset_config & RESET_SRST_PULLS_TRST) + || use_event)) { - /* debug entry was already prepared in arm7_9_assert_reset() */ + /* debug entry was prepared above */ target->debug_reason = DBG_REASON_DBGRQ; } @@ -1039,24 +1075,29 @@ int arm7_9_deassert_reset(struct target *target) /* deassert reset lines */ jtag_add_reset(0, 0); + /* In case polling is disabled, we need to examine the + * target and poll here for this target to work correctly. + * + * Otherwise, e.g. halt will fail afterwards with bogus + * error messages as halt will believe that reset is + * still in effect. + */ + if ((retval = target_examine_one(target)) != ERROR_OK) + return retval; + + if ((retval = target_poll(target)) != ERROR_OK) + { + return retval; + } + enum reset_types jtag_reset_config = jtag_get_reset_config(); if (target->reset_halt && (jtag_reset_config & RESET_SRST_PULLS_TRST) != 0) { LOG_WARNING("srst pulls trst - can not reset into halted mode. Issuing halt after reset."); - /* set up embedded ice registers again */ - if ((retval = target_examine_one(target)) != ERROR_OK) - return retval; - - if ((retval = target_poll(target)) != ERROR_OK) - { - return retval; - } - if ((retval = target_halt(target)) != ERROR_OK) { return retval; } - } return retval; } @@ -1070,7 +1111,7 @@ int arm7_9_deassert_reset(struct target *target) * @param target Pointer to the ARM7/9 target to have halt cleared * @return Always ERROR_OK */ -int arm7_9_clear_halt(struct target *target) +static int arm7_9_clear_halt(struct target *target) { struct arm7_9_common *arm7_9 = target_to_arm7_9(target); struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]; @@ -1130,7 +1171,7 @@ int arm7_9_clear_halt(struct target *target) int arm7_9_soft_reset_halt(struct target *target) { struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - struct arm *armv4_5 = &arm7_9->armv4_5_common; + struct arm *arm = &arm7_9->arm; struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]; int i; @@ -1189,33 +1230,33 @@ int arm7_9_soft_reset_halt(struct target *target) uint32_t r0_thumb, pc_thumb; LOG_DEBUG("target entered debug from Thumb state, changing to ARM"); /* Entered debug from Thumb mode */ - armv4_5->core_state = ARM_STATE_THUMB; + arm->core_state = ARM_STATE_THUMB; arm7_9->change_to_arm(target, &r0_thumb, &pc_thumb); } /* REVISIT likewise for bit 5 -- switch Jazelle-to-ARM */ /* all register content is now invalid */ - register_cache_invalidate(armv4_5->core_cache); + register_cache_invalidate(arm->core_cache); /* SVC, ARM state, IRQ and FIQ disabled */ uint32_t cpsr; - cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 32); + cpsr = buf_get_u32(arm->cpsr->value, 0, 32); cpsr &= ~0xff; cpsr |= 0xd3; - arm_set_cpsr(armv4_5, cpsr); - armv4_5->cpsr->dirty = 1; + arm_set_cpsr(arm, cpsr); + arm->cpsr->dirty = 1; /* start fetching from 0x0 */ - buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0); - armv4_5->core_cache->reg_list[15].dirty = 1; - armv4_5->core_cache->reg_list[15].valid = 1; + buf_set_u32(arm->pc->value, 0, 32, 0x0); + arm->pc->dirty = 1; + arm->pc->valid = 1; /* reset registers */ for (i = 0; i <= 14; i++) { - struct reg *r = arm_reg_current(armv4_5, i); + struct reg *r = arm_reg_current(arm, i); buf_set_u32(r->value, 0, 32, 0xffffffff); r->dirty = 1; @@ -1310,7 +1351,7 @@ static int arm7_9_debug_entry(struct target *target) uint32_t cpsr, cpsr_mask = 0; int retval; struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - struct arm *armv4_5 = &arm7_9->armv4_5_common; + struct arm *arm = &arm7_9->arm; struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]; @@ -1351,7 +1392,7 @@ static int arm7_9_debug_entry(struct target *target) { LOG_DEBUG("target entered debug from Thumb state"); /* Entered debug from Thumb mode */ - armv4_5->core_state = ARM_STATE_THUMB; + arm->core_state = ARM_STATE_THUMB; cpsr_mask = 1 << 5; arm7_9->change_to_arm(target, &r0_thumb, &pc_thumb); LOG_DEBUG("r0_thumb: 0x%8.8" PRIx32 @@ -1363,13 +1404,13 @@ static int arm7_9_debug_entry(struct target *target) * B.7.3 for the reverse. That'd be the bare minimum... */ LOG_DEBUG("target entered debug from Jazelle state"); - armv4_5->core_state = ARM_STATE_JAZELLE; + arm->core_state = ARM_STATE_JAZELLE; cpsr_mask = 1 << 24; LOG_ERROR("Jazelle debug entry -- BROKEN!"); } else { LOG_DEBUG("target entered debug from ARM state"); /* Entered debug from ARM mode */ - armv4_5->core_state = ARM_STATE_ARM; + arm->core_state = ARM_STATE_ARM; } for (i = 0; i < 16; i++) @@ -1385,9 +1426,9 @@ static int arm7_9_debug_entry(struct target *target) /* Sync our CPSR copy with J or T bits EICE reported, but * which we then erased by putting the core into ARM mode. */ - arm_set_cpsr(armv4_5, cpsr | cpsr_mask); + arm_set_cpsr(arm, cpsr | cpsr_mask); - if (!is_arm_mode(armv4_5->core_mode)) + if (!is_arm_mode(arm->core_mode)) { target->state = TARGET_UNKNOWN; LOG_ERROR("cpsr contains invalid mode value - communication failure"); @@ -1395,27 +1436,27 @@ static int arm7_9_debug_entry(struct target *target) } LOG_DEBUG("target entered debug state in %s mode", - arm_mode_name(armv4_5->core_mode)); + arm_mode_name(arm->core_mode)); - if (armv4_5->core_state == ARM_STATE_THUMB) + if (arm->core_state == ARM_STATE_THUMB) { LOG_DEBUG("thumb state, applying fixups"); context[0] = r0_thumb; context[15] = pc_thumb; - } else if (armv4_5->core_state == ARM_STATE_ARM) + } else if (arm->core_state == ARM_STATE_ARM) { /* adjust value stored by STM */ context[15] -= 3 * 4; } if ((target->debug_reason != DBG_REASON_DBGRQ) || (!arm7_9->use_dbgrq)) - context[15] -= 3 * ((armv4_5->core_state == ARM_STATE_ARM) ? 4 : 2); + context[15] -= 3 * ((arm->core_state == ARM_STATE_ARM) ? 4 : 2); else - context[15] -= arm7_9->dbgreq_adjust_pc * ((armv4_5->core_state == ARM_STATE_ARM) ? 4 : 2); + context[15] -= arm7_9->dbgreq_adjust_pc * ((arm->core_state == ARM_STATE_ARM) ? 4 : 2); for (i = 0; i <= 15; i++) { - struct reg *r = arm_reg_current(armv4_5, i); + struct reg *r = arm_reg_current(arm, i); LOG_DEBUG("r%i: 0x%8.8" PRIx32 "", i, context[i]); @@ -1428,23 +1469,27 @@ static int arm7_9_debug_entry(struct target *target) LOG_DEBUG("entered debug state at PC 0x%" PRIx32 "", context[15]); /* exceptions other than USR & SYS have a saved program status register */ - if (armv4_5->spsr) { + if (arm->spsr) { uint32_t spsr; arm7_9->read_xpsr(target, &spsr, 1); if ((retval = jtag_execute_queue()) != ERROR_OK) { return retval; } - buf_set_u32(armv4_5->spsr->value, 0, 32, spsr); - armv4_5->spsr->dirty = 0; - armv4_5->spsr->valid = 1; + buf_set_u32(arm->spsr->value, 0, 32, spsr); + arm->spsr->dirty = 0; + arm->spsr->valid = 1; } if ((retval = jtag_execute_queue()) != ERROR_OK) return retval; if (arm7_9->post_debug_entry) - arm7_9->post_debug_entry(target); + { + retval = arm7_9->post_debug_entry(target); + if (retval != ERROR_OK) + return retval; + } return ERROR_OK; } @@ -1458,12 +1503,12 @@ static int arm7_9_debug_entry(struct target *target) * @return Error if the target is not halted, has an invalid core mode, or if * the JTAG queue fails to execute */ -int arm7_9_full_context(struct target *target) +static int arm7_9_full_context(struct target *target) { int i; int retval; struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - struct arm *armv4_5 = &arm7_9->armv4_5_common; + struct arm *arm = &arm7_9->arm; LOG_DEBUG("-"); @@ -1473,8 +1518,11 @@ int arm7_9_full_context(struct target *target) return ERROR_TARGET_NOT_HALTED; } - if (!is_arm_mode(armv4_5->core_mode)) + if (!is_arm_mode(arm->core_mode)) + { + LOG_ERROR("not a valid arm core mode - communication failure?"); return ERROR_FAIL; + } /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND) * SYS shares registers with User, so we don't touch SYS @@ -1490,7 +1538,7 @@ int arm7_9_full_context(struct target *target) */ for (j = 0; j <= 16; j++) { - if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid == 0) + if (ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i), j).valid == 0) valid = 0; } @@ -1499,7 +1547,7 @@ int arm7_9_full_context(struct target *target) uint32_t tmp_cpsr; /* change processor mode (and mask T bit) */ - tmp_cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 8) + tmp_cpsr = buf_get_u32(arm->cpsr->value, 0, 8) & 0xe0; tmp_cpsr |= armv4_5_number_to_mode(i); tmp_cpsr &= ~0x20; @@ -1507,12 +1555,13 @@ int arm7_9_full_context(struct target *target) for (j = 0; j < 15; j++) { - if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid == 0) + if (ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i), j).valid == 0) { - reg_p[j] = (uint32_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).value; + reg_p[j] = (uint32_t *)ARMV4_5_CORE_REG_MODE(arm->core_cache, + armv4_5_number_to_mode(i), j).value; mask |= 1 << j; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid = 1; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).dirty = 0; + ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i), j).valid = 1; + ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i), j).dirty = 0; } } @@ -1521,18 +1570,19 @@ int arm7_9_full_context(struct target *target) arm7_9->read_core_regs(target, mask, reg_p); /* check if the PSR has to be read */ - if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).valid == 0) + if (ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i), 16).valid == 0) { - arm7_9->read_xpsr(target, (uint32_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).value, 1); - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).valid = 1; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).dirty = 0; + arm7_9->read_xpsr(target, (uint32_t *)ARMV4_5_CORE_REG_MODE(arm->core_cache, + armv4_5_number_to_mode(i), 16).value, 1); + ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i), 16).valid = 1; + ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i), 16).dirty = 0; } } } /* restore processor mode (mask T bit) */ arm7_9->write_xpsr_im8(target, - buf_get_u32(armv4_5->cpsr->value, 0, 8) & ~0x20, + buf_get_u32(arm->cpsr->value, 0, 8) & ~0x20, 0, 0); if ((retval = jtag_execute_queue()) != ERROR_OK) @@ -1554,13 +1604,12 @@ int arm7_9_full_context(struct target *target) * @return Error status if the target is not halted or the core mode in the * armv4_5 struct is invalid. */ -int arm7_9_restore_context(struct target *target) +static int arm7_9_restore_context(struct target *target) { struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - struct arm *armv4_5 = &arm7_9->armv4_5_common; + struct arm *arm = &arm7_9->arm; struct reg *reg; - struct arm_reg *reg_arch_info; - enum arm_mode current_mode = armv4_5->core_mode; + enum arm_mode current_mode = arm->core_mode; int i, j; int dirty; int mode_change; @@ -1576,8 +1625,11 @@ int arm7_9_restore_context(struct target *target) if (arm7_9->pre_restore_context) arm7_9->pre_restore_context(target); - if (!is_arm_mode(armv4_5->core_mode)) + if (!is_arm_mode(arm->core_mode)) + { + LOG_ERROR("not a valid arm core mode - communication failure?"); return ERROR_FAIL; + } /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND) * SYS shares registers with User, so we don't touch SYS @@ -1585,25 +1637,28 @@ int arm7_9_restore_context(struct target *target) for (i = 0; i < 6; i++) { LOG_DEBUG("examining %s mode", - arm_mode_name(armv4_5->core_mode)); + arm_mode_name(arm->core_mode)); dirty = 0; mode_change = 0; /* check if there are dirty registers in the current mode */ for (j = 0; j <= 16; j++) { - reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j); - reg_arch_info = reg->arch_info; + reg = &ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i), j); if (reg->dirty == 1) { if (reg->valid == 1) { dirty = 1; LOG_DEBUG("examining dirty reg: %s", reg->name); + struct arm_reg *reg_arch_info; + reg_arch_info = reg->arch_info; if ((reg_arch_info->mode != ARM_MODE_ANY) && (reg_arch_info->mode != current_mode) - && !((reg_arch_info->mode == ARM_MODE_USR) && (armv4_5->core_mode == ARM_MODE_SYS)) - && !((reg_arch_info->mode == ARM_MODE_SYS) && (armv4_5->core_mode == ARM_MODE_USR))) + && !((reg_arch_info->mode == ARM_MODE_USR) + && (arm->core_mode == ARM_MODE_SYS)) + && !((reg_arch_info->mode == ARM_MODE_SYS) + && (arm->core_mode == ARM_MODE_USR))) { mode_change = 1; LOG_DEBUG("require mode change"); @@ -1627,7 +1682,7 @@ int arm7_9_restore_context(struct target *target) uint32_t tmp_cpsr; /* change processor mode (mask T bit) */ - tmp_cpsr = buf_get_u32(armv4_5->cpsr->value, + tmp_cpsr = buf_get_u32(arm->cpsr->value, 0, 8) & 0xe0; tmp_cpsr |= armv4_5_number_to_mode(i); tmp_cpsr &= ~0x20; @@ -1637,9 +1692,7 @@ int arm7_9_restore_context(struct target *target) for (j = 0; j <= 14; j++) { - reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j); - reg_arch_info = reg->arch_info; - + reg = &ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i), j); if (reg->dirty == 1) { @@ -1650,7 +1703,7 @@ int arm7_9_restore_context(struct target *target) reg->valid = 1; LOG_DEBUG("writing register %i mode %s " "with value 0x%8.8" PRIx32, j, - arm_mode_name(armv4_5->core_mode), + arm_mode_name(arm->core_mode), regs[j]); } } @@ -1660,7 +1713,8 @@ int arm7_9_restore_context(struct target *target) arm7_9->write_core_regs(target, mask, regs); } - reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16); + reg = &ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i), 16); + struct arm_reg *reg_arch_info; reg_arch_info = reg->arch_info; if ((reg->dirty) && (reg_arch_info->mode != ARM_MODE_ANY)) { @@ -1670,36 +1724,32 @@ int arm7_9_restore_context(struct target *target) } } - if (!armv4_5->cpsr->dirty && (armv4_5->core_mode != current_mode)) - { + if (!arm->cpsr->dirty && (arm->core_mode != current_mode)) { /* restore processor mode (mask T bit) */ uint32_t tmp_cpsr; - tmp_cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 8) & 0xE0; + tmp_cpsr = buf_get_u32(arm->cpsr->value, 0, 8) & 0xE0; tmp_cpsr |= armv4_5_number_to_mode(i); tmp_cpsr &= ~0x20; LOG_DEBUG("writing lower 8 bit of cpsr with value 0x%2.2x", (unsigned)(tmp_cpsr)); arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0); - } - else if (armv4_5->cpsr->dirty) - { + + } else if (arm->cpsr->dirty) { /* CPSR has been changed, full restore necessary (mask T bit) */ LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32, - buf_get_u32(armv4_5->cpsr->value, 0, 32)); + buf_get_u32(arm->cpsr->value, 0, 32)); arm7_9->write_xpsr(target, - buf_get_u32(armv4_5->cpsr->value, 0, 32) - & ~0x20, 0); - armv4_5->cpsr->dirty = 0; - armv4_5->cpsr->valid = 1; + buf_get_u32(arm->cpsr->value, 0, 32) + & ~0x20, 0); + arm->cpsr->dirty = 0; + arm->cpsr->valid = 1; } /* restore PC */ - LOG_DEBUG("writing PC with value 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)); - arm7_9->write_pc(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)); - armv4_5->core_cache->reg_list[15].dirty = 0; - - if (arm7_9->post_restore_context) - arm7_9->post_restore_context(target); + LOG_DEBUG("writing PC with value 0x%8.8" PRIx32, + buf_get_u32(arm->pc->value, 0, 32)); + arm7_9->write_pc(target, buf_get_u32(arm->pc->value, 0, 32)); + arm->pc->dirty = 0; return ERROR_OK; } @@ -1712,20 +1762,25 @@ int arm7_9_restore_context(struct target *target) * @param target Pointer to the ARM7/9 target to be restarted * @return Result of executing the JTAG queue */ -int arm7_9_restart_core(struct target *target) +static int arm7_9_restart_core(struct target *target) { struct arm7_9_common *arm7_9 = target_to_arm7_9(target); struct arm_jtag *jtag_info = &arm7_9->jtag_info; + int retval; /* set RESTART instruction */ - jtag_set_end_state(TAP_IDLE); if (arm7_9->need_bypass_before_restart) { arm7_9->need_bypass_before_restart = 0; - arm_jtag_set_instr(jtag_info, 0xf, NULL); + + retval = arm_jtag_set_instr(jtag_info, 0xf, NULL, TAP_IDLE); + if (retval != ERROR_OK) + return retval; } - arm_jtag_set_instr(jtag_info, 0x4, NULL); + retval = arm_jtag_set_instr(jtag_info, 0x4, NULL, TAP_IDLE); + if (retval != ERROR_OK) + return retval; - jtag_add_runtest(1, jtag_set_end_state(TAP_IDLE)); + jtag_add_runtest(1, TAP_IDLE); return jtag_execute_queue(); } @@ -1735,7 +1790,7 @@ int arm7_9_restart_core(struct target *target) * * @param target Pointer to the ARM7/9 target to enable watchpoints on */ -void arm7_9_enable_watchpoints(struct target *target) +static void arm7_9_enable_watchpoints(struct target *target) { struct watchpoint *watchpoint = target->watchpoints; @@ -1753,7 +1808,7 @@ void arm7_9_enable_watchpoints(struct target *target) * * @param target Pointer to the ARM7/9 target to enable breakpoints on */ -void arm7_9_enable_breakpoints(struct target *target) +static void arm7_9_enable_breakpoints(struct target *target) { struct breakpoint *breakpoint = target->breakpoints; @@ -1768,8 +1823,7 @@ void arm7_9_enable_breakpoints(struct target *target) int arm7_9_resume(struct target *target, int current, uint32_t address, int handle_breakpoints, int debug_execution) { struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - struct arm *armv4_5 = &arm7_9->armv4_5_common; - struct breakpoint *breakpoint = target->breakpoints; + struct arm *arm = &arm7_9->arm; struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]; int err, retval = ERROR_OK; @@ -1788,15 +1842,18 @@ int arm7_9_resume(struct target *target, int current, uint32_t address, int hand /* current = 1: continue on current pc, otherwise continue at
*/ if (!current) - buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address); + buf_set_u32(arm->pc->value, 0, 32, address); uint32_t current_pc; - current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32); + current_pc = buf_get_u32(arm->pc->value, 0, 32); /* the front-end may request us not to handle breakpoints */ if (handle_breakpoints) { - if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)))) + struct breakpoint *breakpoint; + breakpoint = breakpoint_find(target, + buf_get_u32(arm->pc->value, 0, 32)); + if (breakpoint != NULL) { LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 " (id: %d)", breakpoint->address, breakpoint->unique_id ); if ((retval = arm7_9_unset_breakpoint(target, breakpoint)) != ERROR_OK) @@ -1820,18 +1877,13 @@ int arm7_9_resume(struct target *target, int current, uint32_t address, int hand target->debug_reason = DBG_REASON_SINGLESTEP; if ((retval = arm7_9_restore_context(target)) != ERROR_OK) - { return retval; - } - if (armv4_5->core_state == ARM_STATE_ARM) + if (arm->core_state == ARM_STATE_ARM) arm7_9->branch_resume(target); - else if (armv4_5->core_state == ARM_STATE_THUMB) - { + else if (arm->core_state == ARM_STATE_THUMB) arm7_9->branch_resume_thumb(target); - } - else - { + else { LOG_ERROR("unhandled core state"); return ERROR_FAIL; } @@ -1853,8 +1905,11 @@ int arm7_9_resume(struct target *target, int current, uint32_t address, int hand return err; } - arm7_9_debug_entry(target); - LOG_DEBUG("new PC after step: 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)); + retval = arm7_9_debug_entry(target); + if (retval != ERROR_OK) + return retval; + LOG_DEBUG("new PC after step: 0x%8.8" PRIx32, + buf_get_u32(arm->pc->value, 0, 32)); LOG_DEBUG("set breakpoint at 0x%8.8" PRIx32 "", breakpoint->address); if ((retval = arm7_9_set_breakpoint(target, breakpoint)) != ERROR_OK) @@ -1869,20 +1924,13 @@ int arm7_9_resume(struct target *target, int current, uint32_t address, int hand arm7_9_enable_watchpoints(target); if ((retval = arm7_9_restore_context(target)) != ERROR_OK) - { return retval; - } - if (armv4_5->core_state == ARM_STATE_ARM) - { + if (arm->core_state == ARM_STATE_ARM) arm7_9->branch_resume(target); - } - else if (armv4_5->core_state == ARM_STATE_THUMB) - { + else if (arm->core_state == ARM_STATE_THUMB) arm7_9->branch_resume_thumb(target); - } - else - { + else { LOG_ERROR("unhandled core state"); return ERROR_FAIL; } @@ -1904,7 +1952,7 @@ int arm7_9_resume(struct target *target, int current, uint32_t address, int hand if (!debug_execution) { /* registers are now invalid */ - register_cache_invalidate(armv4_5->core_cache); + register_cache_invalidate(arm->core_cache); target->state = TARGET_RUNNING; if ((retval = target_call_event_callbacks(target, TARGET_EVENT_RESUMED)) != ERROR_OK) { @@ -1928,9 +1976,9 @@ int arm7_9_resume(struct target *target, int current, uint32_t address, int hand void arm7_9_enable_eice_step(struct target *target, uint32_t next_pc) { struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - struct arm *armv4_5 = &arm7_9->armv4_5_common; + struct arm *arm = &arm7_9->arm; uint32_t current_pc; - current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32); + current_pc = buf_get_u32(arm->pc->value, 0, 32); if (next_pc != current_pc) { @@ -1980,7 +2028,7 @@ void arm7_9_disable_eice_step(struct target *target) int arm7_9_step(struct target *target, int current, uint32_t address, int handle_breakpoints) { struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - struct arm *armv4_5 = &arm7_9->armv4_5_common; + struct arm *arm = &arm7_9->arm; struct breakpoint *breakpoint = NULL; int err, retval; @@ -1992,18 +2040,18 @@ int arm7_9_step(struct target *target, int current, uint32_t address, int handle /* current = 1: continue on current pc, otherwise continue at
*/ if (!current) - buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address); + buf_set_u32(arm->pc->value, 0, 32, address); - uint32_t current_pc; - current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32); + uint32_t current_pc = buf_get_u32(arm->pc->value, 0, 32); /* the front-end may request us not to handle breakpoints */ if (handle_breakpoints) - if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)))) - if ((retval = arm7_9_unset_breakpoint(target, breakpoint)) != ERROR_OK) - { - return retval; - } + breakpoint = breakpoint_find(target, current_pc); + if (breakpoint != NULL) { + retval = arm7_9_unset_breakpoint(target, breakpoint); + if (retval != ERROR_OK) + return retval; + } target->debug_reason = DBG_REASON_SINGLESTEP; @@ -2018,22 +2066,15 @@ int arm7_9_step(struct target *target, int current, uint32_t address, int handle } if ((retval = arm7_9_restore_context(target)) != ERROR_OK) - { return retval; - } arm7_9->enable_single_step(target, next_pc); - if (armv4_5->core_state == ARM_STATE_ARM) - { + if (arm->core_state == ARM_STATE_ARM) arm7_9->branch_resume(target); - } - else if (armv4_5->core_state == ARM_STATE_THUMB) - { + else if (arm->core_state == ARM_STATE_THUMB) arm7_9->branch_resume_thumb(target); - } - else - { + else { LOG_ERROR("unhandled core state"); return ERROR_FAIL; } @@ -2047,13 +2088,15 @@ int arm7_9_step(struct target *target, int current, uint32_t address, int handle arm7_9->disable_single_step(target); /* registers are now invalid */ - register_cache_invalidate(armv4_5->core_cache); + register_cache_invalidate(arm->core_cache); if (err != ERROR_OK) { target->state = TARGET_UNKNOWN; } else { - arm7_9_debug_entry(target); + retval = arm7_9_debug_entry(target); + if (retval != ERROR_OK) + return retval; if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK) { return retval; @@ -2074,30 +2117,30 @@ static int arm7_9_read_core_reg(struct target *target, struct reg *r, int num, enum arm_mode mode) { uint32_t* reg_p[16]; - uint32_t value; int retval; struct arm_reg *areg = r->arch_info; struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - struct arm *armv4_5 = &arm7_9->armv4_5_common; + struct arm *arm = &arm7_9->arm; - if (!is_arm_mode(armv4_5->core_mode)) + if (!is_arm_mode(arm->core_mode)) return ERROR_FAIL; if ((num < 0) || (num > 16)) - return ERROR_INVALID_ARGUMENTS; + return ERROR_COMMAND_SYNTAX_ERROR; if ((mode != ARM_MODE_ANY) - && (mode != armv4_5->core_mode) + && (mode != arm->core_mode) && (areg->mode != ARM_MODE_ANY)) { uint32_t tmp_cpsr; /* change processor mode (mask T bit) */ - tmp_cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 8) & 0xE0; + tmp_cpsr = buf_get_u32(arm->cpsr->value, 0, 8) & 0xE0; tmp_cpsr |= mode; tmp_cpsr &= ~0x20; arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0); } + uint32_t value = 0; if ((num >= 0) && (num <= 15)) { /* read a normal core register */ @@ -2123,11 +2166,11 @@ static int arm7_9_read_core_reg(struct target *target, struct reg *r, buf_set_u32(r->value, 0, 32, value); if ((mode != ARM_MODE_ANY) - && (mode != armv4_5->core_mode) + && (mode != arm->core_mode) && (areg->mode != ARM_MODE_ANY)) { /* restore processor mode (mask T bit) */ arm7_9->write_xpsr_im8(target, - buf_get_u32(armv4_5->cpsr->value, 0, 8) + buf_get_u32(arm->cpsr->value, 0, 8) & ~0x20, 0, 0); } @@ -2140,20 +2183,20 @@ static int arm7_9_write_core_reg(struct target *target, struct reg *r, uint32_t reg[16]; struct arm_reg *areg = r->arch_info; struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - struct arm *armv4_5 = &arm7_9->armv4_5_common; + struct arm *arm = &arm7_9->arm; - if (!is_arm_mode(armv4_5->core_mode)) + if (!is_arm_mode(arm->core_mode)) return ERROR_FAIL; if ((num < 0) || (num > 16)) - return ERROR_INVALID_ARGUMENTS; + return ERROR_COMMAND_SYNTAX_ERROR; if ((mode != ARM_MODE_ANY) - && (mode != armv4_5->core_mode) + && (mode != arm->core_mode) && (areg->mode != ARM_MODE_ANY)) { uint32_t tmp_cpsr; /* change processor mode (mask T bit) */ - tmp_cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 8) & 0xE0; + tmp_cpsr = buf_get_u32(arm->cpsr->value, 0, 8) & 0xE0; tmp_cpsr |= mode; tmp_cpsr &= ~0x20; arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0); @@ -2184,11 +2227,11 @@ static int arm7_9_write_core_reg(struct target *target, struct reg *r, r->dirty = 0; if ((mode != ARM_MODE_ANY) - && (mode != armv4_5->core_mode) + && (mode != arm->core_mode) && (areg->mode != ARM_MODE_ANY)) { /* restore processor mode (mask T bit) */ arm7_9->write_xpsr_im8(target, - buf_get_u32(armv4_5->cpsr->value, 0, 8) + buf_get_u32(arm->cpsr->value, 0, 8) & ~0x20, 0, 0); } @@ -2198,7 +2241,7 @@ static int arm7_9_write_core_reg(struct target *target, struct reg *r, int arm7_9_read_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) { struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - struct arm *armv4_5 = &arm7_9->armv4_5_common; + struct arm *arm = &arm7_9->arm; uint32_t reg[16]; uint32_t num_accesses = 0; int thisrun_accesses; @@ -2217,7 +2260,7 @@ int arm7_9_read_memory(struct target *target, uint32_t address, uint32_t size, u /* sanitize arguments */ if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer)) - return ERROR_INVALID_ARGUMENTS; + return ERROR_COMMAND_SYNTAX_ERROR; if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u))) return ERROR_TARGET_UNALIGNED_ACCESS; @@ -2341,11 +2384,11 @@ int arm7_9_read_memory(struct target *target, uint32_t address, uint32_t size, u break; } - if (!is_arm_mode(armv4_5->core_mode)) + if (!is_arm_mode(arm->core_mode)) return ERROR_FAIL; for (i = 0; i <= last_reg; i++) { - struct reg *r = arm_reg_current(armv4_5, i); + struct reg *r = arm_reg_current(arm, i); r->dirty = r->valid; } @@ -2357,12 +2400,12 @@ int arm7_9_read_memory(struct target *target, uint32_t address, uint32_t size, u return ERROR_TARGET_DATA_ABORT; } - if (((cpsr & 0x1f) == ARM_MODE_ABT) && (armv4_5->core_mode != ARM_MODE_ABT)) + if (((cpsr & 0x1f) == ARM_MODE_ABT) && (arm->core_mode != ARM_MODE_ABT)) { LOG_WARNING("memory read caused data abort (address: 0x%8.8" PRIx32 ", size: 0x%" PRIx32 ", count: 0x%" PRIx32 ")", address, size, count); arm7_9->write_xpsr_im8(target, - buf_get_u32(armv4_5->cpsr->value, 0, 8) + buf_get_u32(arm->cpsr->value, 0, 8) & ~0x20, 0, 0); return ERROR_TARGET_DATA_ABORT; @@ -2371,10 +2414,10 @@ int arm7_9_read_memory(struct target *target, uint32_t address, uint32_t size, u return ERROR_OK; } -int arm7_9_write_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) +int arm7_9_write_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, const uint8_t *buffer) { struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - struct arm *armv4_5 = &arm7_9->armv4_5_common; + struct arm *arm = &arm7_9->arm; struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]; uint32_t reg[16]; @@ -2397,7 +2440,7 @@ int arm7_9_write_memory(struct target *target, uint32_t address, uint32_t size, /* sanitize arguments */ if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer)) - return ERROR_INVALID_ARGUMENTS; + return ERROR_COMMAND_SYNTAX_ERROR; if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u))) return ERROR_TARGET_UNALIGNED_ACCESS; @@ -2437,7 +2480,20 @@ int arm7_9_write_memory(struct target *target, uint32_t address, uint32_t size, if (arm7_9->fast_memory_access) retval = arm7_9_execute_fast_sys_speed(target); else + { retval = arm7_9_execute_sys_speed(target); + + /* + * if memory writes are made when the clock is running slow + * (i.e. 32 kHz) which is necessary in some scripts to reconfigure + * processor operations after a "reset halt" or "reset init", + * need to immediately stroke the keep alive or will end up with + * gdb "keep alive not sent error message" problem. + */ + + keep_alive(); + } + if (retval != ERROR_OK) { return retval; @@ -2473,7 +2529,20 @@ int arm7_9_write_memory(struct target *target, uint32_t address, uint32_t size, if (arm7_9->fast_memory_access) retval = arm7_9_execute_fast_sys_speed(target); else + { retval = arm7_9_execute_sys_speed(target); + + /* + * if memory writes are made when the clock is running slow + * (i.e. 32 kHz) which is necessary in some scripts to reconfigure + * processor operations after a "reset halt" or "reset init", + * need to immediately stroke the keep alive or will end up with + * gdb "keep alive not sent error message" problem. + */ + + keep_alive(); + } + if (retval != ERROR_OK) { return retval; @@ -2508,7 +2577,20 @@ int arm7_9_write_memory(struct target *target, uint32_t address, uint32_t size, if (arm7_9->fast_memory_access) retval = arm7_9_execute_fast_sys_speed(target); else - retval = arm7_9_execute_sys_speed(target); + { + retval = arm7_9_execute_sys_speed(target); + + /* + * if memory writes are made when the clock is running slow + * (i.e. 32 kHz) which is necessary in some scripts to reconfigure + * processor operations after a "reset halt" or "reset init", + * need to immediately stroke the keep alive or will end up with + * gdb "keep alive not sent error message" problem. + */ + + keep_alive(); + } + if (retval != ERROR_OK) { return retval; @@ -2525,11 +2607,11 @@ int arm7_9_write_memory(struct target *target, uint32_t address, uint32_t size, buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1); embeddedice_store_reg(dbg_ctrl); - if (!is_arm_mode(armv4_5->core_mode)) + if (!is_arm_mode(arm->core_mode)) return ERROR_FAIL; for (i = 0; i <= last_reg; i++) { - struct reg *r = arm_reg_current(armv4_5, i); + struct reg *r = arm_reg_current(arm, i); r->dirty = r->valid; } @@ -2541,12 +2623,12 @@ int arm7_9_write_memory(struct target *target, uint32_t address, uint32_t size, return ERROR_TARGET_DATA_ABORT; } - if (((cpsr & 0x1f) == ARM_MODE_ABT) && (armv4_5->core_mode != ARM_MODE_ABT)) + if (((cpsr & 0x1f) == ARM_MODE_ABT) && (arm->core_mode != ARM_MODE_ABT)) { LOG_WARNING("memory write caused data abort (address: 0x%8.8" PRIx32 ", size: 0x%" PRIx32 ", count: 0x%" PRIx32 ")", address, size, count); arm7_9->write_xpsr_im8(target, - buf_get_u32(armv4_5->cpsr->value, 0, 8) + buf_get_u32(arm->cpsr->value, 0, 8) & ~0x20, 0, 0); return ERROR_TARGET_DATA_ABORT; @@ -2556,7 +2638,7 @@ int arm7_9_write_memory(struct target *target, uint32_t address, uint32_t size, } static int dcc_count; -static uint8_t *dcc_buffer; +static const uint8_t *dcc_buffer; static int arm7_9_dcc_completion(struct target *target, uint32_t exit_point, int timeout_ms, void *arch_info) { @@ -2568,7 +2650,7 @@ static int arm7_9_dcc_completion(struct target *target, uint32_t exit_point, int int little = target->endianness == TARGET_LITTLE_ENDIAN; int count = dcc_count; - uint8_t *buffer = dcc_buffer; + const uint8_t *buffer = dcc_buffer; if (count > 2) { /* Handle first & last using standard embeddedice_write_reg and the middle ones w/the @@ -2621,7 +2703,7 @@ static const uint32_t dcc_code[] = 0xeafffff9 /* b w */ }; -int arm7_9_bulk_write_memory(struct target *target, uint32_t address, uint32_t count, uint8_t *buffer) +int arm7_9_bulk_write_memory(struct target *target, uint32_t address, uint32_t count, const uint8_t *buffer) { int retval; struct arm7_9_common *arm7_9 = target_to_arm7_9(target); @@ -2707,10 +2789,10 @@ int arm7_9_examine(struct target *target) (*cache_p) = t; arm7_9->eice_cache = (*cache_p); - if (arm7_9->armv4_5_common.etm) + if (arm7_9->arm.etm) (*cache_p)->next = etm_build_reg_cache(target, &arm7_9->jtag_info, - arm7_9->armv4_5_common.etm); + arm7_9->arm.etm); target_set_examined(target); } @@ -2718,11 +2800,34 @@ int arm7_9_examine(struct target *target) retval = embeddedice_setup(target); if (retval == ERROR_OK) retval = arm7_9_setup(target); - if (retval == ERROR_OK && arm7_9->armv4_5_common.etm) + if (retval == ERROR_OK && arm7_9->arm.etm) retval = etm_setup(target); return retval; } + +int arm7_9_check_reset(struct target *target) +{ + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + + if (get_target_reset_nag() && !arm7_9->dcc_downloads) + { + LOG_WARNING("NOTE! DCC downloads have not been enabled, defaulting to slow memory writes. Type 'help dcc'."); + } + + if (get_target_reset_nag() && (target->working_area_size == 0)) + { + LOG_WARNING("NOTE! Severe performance degradation without working memory enabled."); + } + + if (get_target_reset_nag() && !arm7_9->fast_memory_access) + { + LOG_WARNING("NOTE! Severe performance degradation without fast memory access enabled. Type 'help fast'."); + } + + return ERROR_OK; +} + COMMAND_HANDLER(handle_arm7_9_dbgrq_command) { struct target *target = get_current_target(CMD_CTX); @@ -2780,55 +2885,39 @@ COMMAND_HANDLER(handle_arm7_9_dcc_downloads_command) return ERROR_OK; } -COMMAND_HANDLER(handle_arm7_9_semihosting_command) +static int arm7_9_setup_semihosting(struct target *target, int enable) { - struct target *target = get_current_target(CMD_CTX); struct arm7_9_common *arm7_9 = target_to_arm7_9(target); if (!is_arm7_9(arm7_9)) { - command_print(CMD_CTX, "current target isn't an ARM7/ARM9 target"); + LOG_USER("current target isn't an ARM7/ARM9 target"); return ERROR_TARGET_INVALID; } - if (CMD_ARGC > 0) - { - int semihosting; - - COMMAND_PARSE_ENABLE(CMD_ARGV[0], semihosting); - - if (arm7_9->has_vector_catch) { - struct reg *vector_catch = &arm7_9->eice_cache - ->reg_list[EICE_VEC_CATCH]; - - if (!vector_catch->valid) - embeddedice_read_reg(vector_catch); - buf_set_u32(vector_catch->value, 2, 1, semihosting); - embeddedice_store_reg(vector_catch); - } else { - /* TODO: allow optional high vectors and/or BKPT_HARD */ - if (semihosting) - breakpoint_add(target, 8, 4, BKPT_SOFT); - else - breakpoint_remove(target, 8); - } - - /* FIXME never let that "catch" be dropped! */ - arm7_9->armv4_5_common.is_semihosting = semihosting; + if (arm7_9->has_vector_catch) { + struct reg *vector_catch = &arm7_9->eice_cache + ->reg_list[EICE_VEC_CATCH]; + if (!vector_catch->valid) + embeddedice_read_reg(vector_catch); + buf_set_u32(vector_catch->value, 2, 1, enable); + embeddedice_store_reg(vector_catch); + } else { + /* TODO: allow optional high vectors and/or BKPT_HARD */ + if (enable) + breakpoint_add(target, 8, 4, BKPT_SOFT); + else + breakpoint_remove(target, 8); } - command_print(CMD_CTX, "semihosting is %s", - arm7_9->armv4_5_common.is_semihosting - ? "enabled" : "disabled"); - return ERROR_OK; } int arm7_9_init_arch_info(struct target *target, struct arm7_9_common *arm7_9) { int retval = ERROR_OK; - struct arm *armv4_5 = &arm7_9->armv4_5_common; + struct arm *arm = &arm7_9->arm; arm7_9->common_magic = ARM7_9_COMMON_MAGIC; @@ -2842,12 +2931,13 @@ int arm7_9_init_arch_info(struct target *target, struct arm7_9_common *arm7_9) arm7_9->fast_memory_access = false; arm7_9->dcc_downloads = false; - armv4_5->arch_info = arm7_9; - armv4_5->read_core_reg = arm7_9_read_core_reg; - armv4_5->write_core_reg = arm7_9_write_core_reg; - armv4_5->full_context = arm7_9_full_context; + arm->arch_info = arm7_9; + arm->read_core_reg = arm7_9_read_core_reg; + arm->write_core_reg = arm7_9_write_core_reg; + arm->full_context = arm7_9_full_context; + arm->setup_semihosting = arm7_9_setup_semihosting; - retval = arm_init_arch_info(target, armv4_5); + retval = arm_init_arch_info(target, arm); if (retval != ERROR_OK) return retval; @@ -2858,34 +2948,27 @@ int arm7_9_init_arch_info(struct target *target, struct arm7_9_common *arm7_9) static const struct command_registration arm7_9_any_command_handlers[] = { { "dbgrq", - .handler = &handle_arm7_9_dbgrq_command, + .handler = handle_arm7_9_dbgrq_command, .mode = COMMAND_ANY, - .usage = "", + .usage = "['enable'|'disable']", .help = "use EmbeddedICE dbgrq instead of breakpoint " "for target halt requests", }, { "fast_memory_access", - .handler = &handle_arm7_9_fast_memory_access_command, + .handler = handle_arm7_9_fast_memory_access_command, .mode = COMMAND_ANY, - .usage = "", + .usage = "['enable'|'disable']", .help = "use fast memory accesses instead of slower " "but potentially safer accesses", }, { "dcc_downloads", - .handler = &handle_arm7_9_dcc_downloads_command, + .handler = handle_arm7_9_dcc_downloads_command, .mode = COMMAND_ANY, - .usage = "", + .usage = "['enable'|'disable']", .help = "use DCC downloads for larger memory writes", }, - { - "semihosting", - .handler = &handle_arm7_9_semihosting_command, - .mode = COMMAND_EXEC, - .usage = "", - .help = "activate support for semihosting operations", - }, COMMAND_REGISTRATION_DONE }; const struct command_registration arm7_9_command_handlers[] = { @@ -2899,6 +2982,7 @@ const struct command_registration arm7_9_command_handlers[] = { .name = "arm7_9", .mode = COMMAND_ANY, .help = "arm7/9 specific commands", + .usage = "", .chain = arm7_9_any_command_handlers, }, COMMAND_REGISTRATION_DONE