X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Farm7_9_common.c;h=ea04f3f85bb74e2c58487eebc9afca0525afc8e7;hb=afe0298399bd06700926822e6d49c5bc44151956;hp=3894f850cb52120306594ea9f978f4b433c5f690;hpb=8012b3963fc49c7edf87f31a93bc0039095f5b59;p=openocd.git diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c index 3894f850cb..ea04f3f85b 100644 --- a/src/target/arm7_9_common.c +++ b/src/target/arm7_9_common.c @@ -37,7 +37,7 @@ #include "arm_simulator.h" -int arm7_9_debug_entry(target_t *target); +int arm7_9_debug_entry(struct target *target); /** * Clear watchpoints for an ARM7/9 target. @@ -66,7 +66,7 @@ static int arm7_9_clear_watchpoints(struct arm7_9_common *arm7_9) * @param arm7_9 Pointer to the common struct for an ARM7/9 target * @param breakpoint Pointer to the breakpoint to be used as a watchpoint */ -static void arm7_9_assign_wp(struct arm7_9_common *arm7_9, breakpoint_t *breakpoint) +static void arm7_9_assign_wp(struct arm7_9_common *arm7_9, struct breakpoint *breakpoint) { if (!arm7_9->wp0_used) { @@ -159,46 +159,13 @@ static int arm7_9_set_software_breakpoints(struct arm7_9_common *arm7_9) * @param target Pointer to an ARM7/9 target to setup * @return Result of clearing the watchpoints on the target */ -int arm7_9_setup(target_t *target) +int arm7_9_setup(struct target *target) { struct arm7_9_common *arm7_9 = target_to_arm7_9(target); return arm7_9_clear_watchpoints(arm7_9); } -/** - * Retrieves the architecture information pointers for ARMv4/5 and ARM7/9 - * targets. A return of ERROR_OK signifies that the target is a valid target - * and that the pointers have been set properly. - * - * @param target Pointer to the target device to get the pointers from - * @param armv4_5_p Pointer to be filled in with the common struct for ARMV4/5 - * targets - * @param arm7_9_p Pointer to be filled in with the common struct for ARM7/9 - * targets - * @return ERROR_OK if successful - */ -int arm7_9_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, struct arm7_9_common **arm7_9_p) -{ - struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common; - - /* FIXME stop using this routine; just target_to_arm7_9() and - * verify the resulting pointer using a replacement routine - * that emits a usage message. - */ - if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC) - return ERROR_TARGET_INVALID; - - if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC) - return ERROR_TARGET_INVALID; - - *armv4_5_p = armv4_5; - *arm7_9_p = arm7_9; - - return ERROR_OK; -} - /** * Set either a hardware or software breakpoint on an ARM7/9 target. The * breakpoint is set up even if it is already set. Some actions, e.g. reset, @@ -210,7 +177,7 @@ int arm7_9_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, str * queue. For software breakpoints, this will be the status of the * required memory reads and writes */ -int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) +int arm7_9_set_breakpoint(struct target *target, struct breakpoint *breakpoint) { struct arm7_9_common *arm7_9 = target_to_arm7_9(target); int retval = ERROR_OK; @@ -339,7 +306,7 @@ int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) * queue. For software breakpoints, this will be the status of the * required memory reads and writes */ -int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint) +int arm7_9_unset_breakpoint(struct target *target, struct breakpoint *breakpoint) { int retval = ERROR_OK; struct arm7_9_common *arm7_9 = target_to_arm7_9(target); @@ -434,7 +401,7 @@ int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint) * @return An error status if there is a problem adding the breakpoint or the * result of setting the breakpoint */ -int arm7_9_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint) +int arm7_9_add_breakpoint(struct target *target, struct breakpoint *breakpoint) { struct arm7_9_common *arm7_9 = target_to_arm7_9(target); @@ -484,7 +451,7 @@ int arm7_9_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint) * @return Error status if there was a problem unsetting the breakpoint or the * watchpoints could not be cleared */ -int arm7_9_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint) +int arm7_9_remove_breakpoint(struct target *target, struct breakpoint *breakpoint) { int retval = ERROR_OK; struct arm7_9_common *arm7_9 = target_to_arm7_9(target); @@ -520,7 +487,7 @@ int arm7_9_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint) * @return Error status if watchpoint set fails or the result of executing the * JTAG queue */ -int arm7_9_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint) +int arm7_9_set_watchpoint(struct target *target, struct watchpoint *watchpoint) { int retval = ERROR_OK; struct arm7_9_common *arm7_9 = target_to_arm7_9(target); @@ -591,7 +558,7 @@ int arm7_9_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint) * @return Error status while trying to unset the watchpoint or the result of * executing the JTAG queue */ -int arm7_9_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint) +int arm7_9_unset_watchpoint(struct target *target, struct watchpoint *watchpoint) { int retval = ERROR_OK; struct arm7_9_common *arm7_9 = target_to_arm7_9(target); @@ -639,7 +606,7 @@ int arm7_9_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint) * @param watchpoint Pointer to the watchpoint to be added * @return Error status while trying to add the watchpoint */ -int arm7_9_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint) +int arm7_9_add_watchpoint(struct target *target, struct watchpoint *watchpoint) { struct arm7_9_common *arm7_9 = target_to_arm7_9(target); @@ -672,7 +639,7 @@ int arm7_9_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint) * @param watchpoint Pointer to the watchpoint to be removed * @return Result of trying to unset the watchpoint */ -int arm7_9_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint) +int arm7_9_remove_watchpoint(struct target *target, struct watchpoint *watchpoint) { int retval = ERROR_OK; struct arm7_9_common *arm7_9 = target_to_arm7_9(target); @@ -699,12 +666,12 @@ int arm7_9_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint) * @return Error status if there is a timeout or a problem while executing the * JTAG queue */ -int arm7_9_execute_sys_speed(struct target_s *target) +int arm7_9_execute_sys_speed(struct target *target) { int retval; struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - arm_jtag_t *jtag_info = &arm7_9->jtag_info; - reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; + struct arm_jtag *jtag_info = &arm7_9->jtag_info; + struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; /* set RESTART instruction */ jtag_set_end_state(TAP_IDLE); @@ -750,14 +717,14 @@ int arm7_9_execute_sys_speed(struct target_s *target) * @param target Pointer to the target to issue commands to * @return Always ERROR_OK */ -int arm7_9_execute_fast_sys_speed(struct target_s *target) +int arm7_9_execute_fast_sys_speed(struct target *target) { static int set = 0; static uint8_t check_value[4], check_mask[4]; struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - arm_jtag_t *jtag_info = &arm7_9->jtag_info; - reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; + struct arm_jtag *jtag_info = &arm7_9->jtag_info; + struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; /* set RESTART instruction */ jtag_set_end_state(TAP_IDLE); @@ -794,10 +761,10 @@ int arm7_9_execute_fast_sys_speed(struct target_s *target) * @param buffer Pointer to the buffer that will hold the data * @return The result of receiving data from the Embedded ICE unit */ -int arm7_9_target_request_data(target_t *target, uint32_t size, uint8_t *buffer) +int arm7_9_target_request_data(struct target *target, uint32_t size, uint8_t *buffer) { struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm_jtag *jtag_info = &arm7_9->jtag_info; uint32_t *data; int retval = ERROR_OK; uint32_t i; @@ -822,19 +789,19 @@ int arm7_9_target_request_data(target_t *target, uint32_t size, uint8_t *buffer) * target is running and the DCC control register has the W bit high, this will * execute the request on the target. * - * @param priv Void pointer expected to be a target_t pointer + * @param priv Void pointer expected to be a struct target pointer * @return ERROR_OK unless there are issues with the JTAG queue or when reading * from the Embedded ICE unit */ int arm7_9_handle_target_request(void *priv) { int retval = ERROR_OK; - target_t *target = priv; + struct target *target = priv; if (!target_was_examined(target)) return ERROR_OK; struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - arm_jtag_t *jtag_info = &arm7_9->jtag_info; - reg_t *dcc_control = &arm7_9->eice_cache->reg_list[EICE_COMMS_CTRL]; + struct arm_jtag *jtag_info = &arm7_9->jtag_info; + struct reg *dcc_control = &arm7_9->eice_cache->reg_list[EICE_COMMS_CTRL]; if (!target->dbg_msg_enabled) return ERROR_OK; @@ -887,11 +854,11 @@ int arm7_9_handle_target_request(void *priv) * @param target Pointer to the ARM7/9 target to poll * @return ERROR_OK or an error status if a command fails */ -int arm7_9_poll(target_t *target) +int arm7_9_poll(struct target *target) { int retval; struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; + struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; /* read debug status register */ embeddedice_read_reg(dbg_stat); @@ -931,7 +898,7 @@ int arm7_9_poll(target_t *target) if (check_pc) { - reg_t *reg = register_get_by_name(target->reg_cache, "pc", 1); + struct reg *reg = register_get_by_name(target->reg_cache, "pc", 1); uint32_t t=*((uint32_t *)reg->value); if (t != 0) { @@ -980,7 +947,7 @@ int arm7_9_poll(target_t *target) * @param target Pointer to an ARM7/9 target to assert reset on * @return ERROR_FAIL if the JTAG device does not have SRST, otherwise ERROR_OK */ -int arm7_9_assert_reset(target_t *target) +int arm7_9_assert_reset(struct target *target) { struct arm7_9_common *arm7_9 = target_to_arm7_9(target); @@ -1072,7 +1039,7 @@ int arm7_9_assert_reset(target_t *target) * @param target Pointer to the target to have the reset deasserted * @return ERROR_OK or an error from polling or halting the target */ -int arm7_9_deassert_reset(target_t *target) +int arm7_9_deassert_reset(struct target *target) { int retval = ERROR_OK; LOG_DEBUG("target->state: %s", @@ -1112,10 +1079,10 @@ int arm7_9_deassert_reset(target_t *target) * @param target Pointer to the ARM7/9 target to have halt cleared * @return Always ERROR_OK */ -int arm7_9_clear_halt(target_t *target) +int arm7_9_clear_halt(struct target *target) { struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]; + struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]; /* we used DBGRQ only if we didn't come out of reset */ if (!arm7_9->debug_entry_from_reset && arm7_9->use_dbgrq) @@ -1169,12 +1136,12 @@ int arm7_9_clear_halt(target_t *target) * @param target Pointer to the ARM7/9 target to be reset and halted by software * @return Error status if any of the commands fail, otherwise ERROR_OK */ -int arm7_9_soft_reset_halt(struct target_s *target) +int arm7_9_soft_reset_halt(struct target *target) { struct arm7_9_common *arm7_9 = target_to_arm7_9(target); struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common; - reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; - reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]; + struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; + struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]; int i; int retval; @@ -1282,7 +1249,7 @@ int arm7_9_soft_reset_halt(struct target_s *target) * @param target Pointer to the ARM7/9 target to be halted * @return Always ERROR_OK */ -int arm7_9_halt(target_t *target) +int arm7_9_halt(struct target *target) { if (target->state == TARGET_RESET) { @@ -1291,7 +1258,7 @@ int arm7_9_halt(target_t *target) } struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]; + struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]; LOG_DEBUG("target->state: %s", target_state_name(target)); @@ -1344,7 +1311,7 @@ int arm7_9_halt(target_t *target) * @param target Pointer to target that is entering debug mode * @return Error code if anything fails, otherwise ERROR_OK */ -int arm7_9_debug_entry(target_t *target) +int arm7_9_debug_entry(struct target *target) { int i; uint32_t context[16]; @@ -1354,8 +1321,8 @@ int arm7_9_debug_entry(target_t *target) int retval; struct arm7_9_common *arm7_9 = target_to_arm7_9(target); struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common; - reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; - reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]; + struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; + struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]; #ifdef _DEBUG_ARM7_9_ LOG_DEBUG("-"); @@ -1502,7 +1469,7 @@ int arm7_9_debug_entry(target_t *target) * @return Error if the target is not halted, has an invalid core mode, or if * the JTAG queue fails to execute */ -int arm7_9_full_context(target_t *target) +int arm7_9_full_context(struct target *target) { int i; int retval; @@ -1595,12 +1562,12 @@ int arm7_9_full_context(target_t *target) * @return Error status if the target is not halted or the core mode in the * armv4_5 struct is invalid. */ -int arm7_9_restore_context(target_t *target) +int arm7_9_restore_context(struct target *target) { struct arm7_9_common *arm7_9 = target_to_arm7_9(target); struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common; - reg_t *reg; - armv4_5_core_reg_t *reg_arch_info; + struct reg *reg; + struct armv4_5_core_reg *reg_arch_info; enum armv4_5_mode current_mode = armv4_5->core_mode; int i, j; int dirty; @@ -1745,10 +1712,10 @@ int arm7_9_restore_context(target_t *target) * @param target Pointer to the ARM7/9 target to be restarted * @return Result of executing the JTAG queue */ -int arm7_9_restart_core(struct target_s *target) +int arm7_9_restart_core(struct target *target) { struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm_jtag *jtag_info = &arm7_9->jtag_info; /* set RESTART instruction */ jtag_set_end_state(TAP_IDLE); @@ -1768,9 +1735,9 @@ int arm7_9_restart_core(struct target_s *target) * * @param target Pointer to the ARM7/9 target to enable watchpoints on */ -void arm7_9_enable_watchpoints(struct target_s *target) +void arm7_9_enable_watchpoints(struct target *target) { - watchpoint_t *watchpoint = target->watchpoints; + struct watchpoint *watchpoint = target->watchpoints; while (watchpoint) { @@ -1786,9 +1753,9 @@ void arm7_9_enable_watchpoints(struct target_s *target) * * @param target Pointer to the ARM7/9 target to enable breakpoints on */ -void arm7_9_enable_breakpoints(struct target_s *target) +void arm7_9_enable_breakpoints(struct target *target) { - breakpoint_t *breakpoint = target->breakpoints; + struct breakpoint *breakpoint = target->breakpoints; /* set any pending breakpoints */ while (breakpoint) @@ -1798,12 +1765,12 @@ void arm7_9_enable_breakpoints(struct target_s *target) } } -int arm7_9_resume(struct target_s *target, int current, uint32_t address, int handle_breakpoints, int debug_execution) +int arm7_9_resume(struct target *target, int current, uint32_t address, int handle_breakpoints, int debug_execution) { struct arm7_9_common *arm7_9 = target_to_arm7_9(target); struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common; - breakpoint_t *breakpoint = target->breakpoints; - reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]; + struct breakpoint *breakpoint = target->breakpoints; + struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]; int err, retval = ERROR_OK; LOG_DEBUG("-"); @@ -1958,7 +1925,7 @@ int arm7_9_resume(struct target_s *target, int current, uint32_t address, int ha return ERROR_OK; } -void arm7_9_enable_eice_step(target_t *target, uint32_t next_pc) +void arm7_9_enable_eice_step(struct target *target, uint32_t next_pc) { struct arm7_9_common *arm7_9 = target_to_arm7_9(target); struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common; @@ -1995,7 +1962,7 @@ void arm7_9_enable_eice_step(target_t *target, uint32_t next_pc) } } -void arm7_9_disable_eice_step(target_t *target) +void arm7_9_disable_eice_step(struct target *target) { struct arm7_9_common *arm7_9 = target_to_arm7_9(target); @@ -2010,11 +1977,11 @@ void arm7_9_disable_eice_step(target_t *target) embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE]); } -int arm7_9_step(struct target_s *target, int current, uint32_t address, int handle_breakpoints) +int arm7_9_step(struct target *target, int current, uint32_t address, int handle_breakpoints) { struct arm7_9_common *arm7_9 = target_to_arm7_9(target); struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common; - breakpoint_t *breakpoint = NULL; + struct breakpoint *breakpoint = NULL; int err, retval; if (target->state != TARGET_HALTED) @@ -2103,7 +2070,7 @@ int arm7_9_step(struct target_s *target, int current, uint32_t address, int hand return err; } -int arm7_9_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mode) +int arm7_9_read_core_reg(struct target *target, int num, enum armv4_5_mode mode) { uint32_t* reg_p[16]; uint32_t value; @@ -2114,7 +2081,7 @@ int arm7_9_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mod if (armv4_5_mode_to_number(armv4_5->core_mode)==-1) return ERROR_FAIL; - enum armv4_5_mode reg_mode = ((armv4_5_core_reg_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode; + enum armv4_5_mode reg_mode = ((struct armv4_5_core_reg*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode; if ((num < 0) || (num > 16)) return ERROR_INVALID_ARGUMENTS; @@ -2144,7 +2111,7 @@ int arm7_9_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mod /* read a program status register * if the register mode is MODE_ANY, we read the cpsr, otherwise a spsr */ - armv4_5_core_reg_t *arch_info = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info; + struct armv4_5_core_reg *arch_info = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info; int spsr = (arch_info->mode == ARMV4_5_MODE_ANY) ? 0 : 1; arm7_9->read_xpsr(target, &value, spsr); @@ -2169,7 +2136,7 @@ int arm7_9_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mod return ERROR_OK; } -int arm7_9_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mode, uint32_t value) +int arm7_9_write_core_reg(struct target *target, int num, enum armv4_5_mode mode, uint32_t value) { uint32_t reg[16]; struct arm7_9_common *arm7_9 = target_to_arm7_9(target); @@ -2178,7 +2145,7 @@ int arm7_9_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mo if (armv4_5_mode_to_number(armv4_5->core_mode)==-1) return ERROR_FAIL; - enum armv4_5_mode reg_mode = ((armv4_5_core_reg_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode; + enum armv4_5_mode reg_mode = ((struct armv4_5_core_reg*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode; if ((num < 0) || (num > 16)) return ERROR_INVALID_ARGUMENTS; @@ -2207,7 +2174,7 @@ int arm7_9_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mo /* write a program status register * if the register mode is MODE_ANY, we write the cpsr, otherwise a spsr */ - armv4_5_core_reg_t *arch_info = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info; + struct armv4_5_core_reg *arch_info = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info; int spsr = (arch_info->mode == ARMV4_5_MODE_ANY) ? 0 : 1; /* if we're writing the CPSR, mask the T bit */ @@ -2230,7 +2197,7 @@ int arm7_9_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mo return jtag_execute_queue(); } -int arm7_9_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) +int arm7_9_read_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) { struct arm7_9_common *arm7_9 = target_to_arm7_9(target); struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common; @@ -2405,11 +2372,11 @@ int arm7_9_read_memory(struct target_s *target, uint32_t address, uint32_t size, return ERROR_OK; } -int arm7_9_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) +int arm7_9_write_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) { struct arm7_9_common *arm7_9 = target_to_arm7_9(target); struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common; - reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]; + struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]; uint32_t reg[16]; uint32_t num_accesses = 0; @@ -2591,7 +2558,7 @@ int arm7_9_write_memory(struct target_s *target, uint32_t address, uint32_t size static int dcc_count; static uint8_t *dcc_buffer; -static int arm7_9_dcc_completion(struct target_s *target, uint32_t exit_point, int timeout_ms, void *arch_info) +static int arm7_9_dcc_completion(struct target *target, uint32_t exit_point, int timeout_ms, void *arch_info) { int retval = ERROR_OK; struct arm7_9_common *arm7_9 = target_to_arm7_9(target); @@ -2609,7 +2576,7 @@ static int arm7_9_dcc_completion(struct target_s *target, uint32_t exit_point, i embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little)); buffer += 4; - embeddedice_reg_t *ice_reg = arm7_9->eice_cache->reg_list[EICE_COMMS_DATA].arch_info; + struct embeddedice_reg *ice_reg = arm7_9->eice_cache->reg_list[EICE_COMMS_DATA].arch_info; uint8_t reg_addr = ice_reg->addr & 0x1f; struct jtag_tap *tap; tap = ice_reg->jtag_info->tap; @@ -2654,9 +2621,9 @@ static const uint32_t dcc_code[] = 0xeafffff9 /* b w */ }; -int armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info, int (*run_it)(struct target_s *target, uint32_t exit_point, int timeout_ms, void *arch_info)); +int armv4_5_run_algorithm_inner(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info, int (*run_it)(struct target *target, uint32_t exit_point, int timeout_ms, void *arch_info)); -int arm7_9_bulk_write_memory(target_t *target, uint32_t address, uint32_t count, uint8_t *buffer) +int arm7_9_bulk_write_memory(struct target *target, uint32_t address, uint32_t count, uint8_t *buffer) { int retval; struct arm7_9_common *arm7_9 = target_to_arm7_9(target); @@ -2690,7 +2657,7 @@ int arm7_9_bulk_write_memory(target_t *target, uint32_t address, uint32_t count, } } - armv4_5_algorithm_t armv4_5_info; + struct armv4_5_algorithm armv4_5_info; struct reg_param reg_params[1]; armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC; @@ -2721,10 +2688,10 @@ int arm7_9_bulk_write_memory(target_t *target, uint32_t address, uint32_t count, return retval; } -int arm7_9_checksum_memory(struct target_s *target, uint32_t address, uint32_t count, uint32_t* checksum) +int arm7_9_checksum_memory(struct target *target, uint32_t address, uint32_t count, uint32_t* checksum) { - working_area_t *crc_algorithm; - armv4_5_algorithm_t armv4_5_info; + struct working_area *crc_algorithm; + struct armv4_5_algorithm armv4_5_info; struct reg_param reg_params[2]; int retval; @@ -2805,11 +2772,11 @@ int arm7_9_checksum_memory(struct target_s *target, uint32_t address, uint32_t c return ERROR_OK; } -int arm7_9_blank_check_memory(struct target_s *target, uint32_t address, uint32_t count, uint32_t* blank) +int arm7_9_blank_check_memory(struct target *target, uint32_t address, uint32_t count, uint32_t* blank) { - working_area_t *erase_check_algorithm; + struct working_area *erase_check_algorithm; struct reg_param reg_params[3]; - armv4_5_algorithm_t armv4_5_info; + struct armv4_5_algorithm armv4_5_info; int retval; uint32_t i; @@ -2876,26 +2843,25 @@ COMMAND_HANDLER(handle_arm7_9_write_xpsr_command) uint32_t value; int spsr; int retval; - target_t *target = get_current_target(cmd_ctx); - armv4_5_common_t *armv4_5; - struct arm7_9_common *arm7_9; + struct target *target = get_current_target(cmd_ctx); + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK) + if (!is_arm7_9(arm7_9)) { command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target"); - return ERROR_OK; + return ERROR_TARGET_INVALID; } if (target->state != TARGET_HALTED) { command_print(cmd_ctx, "can't write registers while running"); - return ERROR_OK; + return ERROR_FAIL; } if (argc < 2) { command_print(cmd_ctx, "usage: write_xpsr "); - return ERROR_OK; + return ERROR_FAIL; } COMMAND_PARSE_NUMBER(u32, args[0], value); @@ -2921,26 +2887,25 @@ COMMAND_HANDLER(handle_arm7_9_write_xpsr_im8_command) int rotate; int spsr; int retval; - target_t *target = get_current_target(cmd_ctx); - armv4_5_common_t *armv4_5; - struct arm7_9_common *arm7_9; + struct target *target = get_current_target(cmd_ctx); + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK) + if (!is_arm7_9(arm7_9)) { command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target"); - return ERROR_OK; + return ERROR_TARGET_INVALID; } if (target->state != TARGET_HALTED) { command_print(cmd_ctx, "can't write registers while running"); - return ERROR_OK; + return ERROR_FAIL; } if (argc < 3) { command_print(cmd_ctx, "usage: write_xpsr_im8 "); - return ERROR_OK; + return ERROR_FAIL; } COMMAND_PARSE_NUMBER(u32, args[0], value); @@ -2962,26 +2927,25 @@ COMMAND_HANDLER(handle_arm7_9_write_core_reg_command) uint32_t value; uint32_t mode; int num; - target_t *target = get_current_target(cmd_ctx); - armv4_5_common_t *armv4_5; - struct arm7_9_common *arm7_9; + struct target *target = get_current_target(cmd_ctx); + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK) + if (!is_arm7_9(arm7_9)) { command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target"); - return ERROR_OK; + return ERROR_TARGET_INVALID; } if (target->state != TARGET_HALTED) { command_print(cmd_ctx, "can't write registers while running"); - return ERROR_OK; + return ERROR_FAIL; } if (argc < 3) { command_print(cmd_ctx, "usage: write_core_reg "); - return ERROR_OK; + return ERROR_FAIL; } COMMAND_PARSE_NUMBER(int, args[0], num); @@ -2993,14 +2957,13 @@ COMMAND_HANDLER(handle_arm7_9_write_core_reg_command) COMMAND_HANDLER(handle_arm7_9_dbgrq_command) { - target_t *target = get_current_target(cmd_ctx); - armv4_5_common_t *armv4_5; - struct arm7_9_common *arm7_9; + struct target *target = get_current_target(cmd_ctx); + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK) + if (!is_arm7_9(arm7_9)) { command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target"); - return ERROR_OK; + return ERROR_TARGET_INVALID; } if (argc > 0) @@ -3026,14 +2989,13 @@ COMMAND_HANDLER(handle_arm7_9_dbgrq_command) COMMAND_HANDLER(handle_arm7_9_fast_memory_access_command) { - target_t *target = get_current_target(cmd_ctx); - armv4_5_common_t *armv4_5; - struct arm7_9_common *arm7_9; + struct target *target = get_current_target(cmd_ctx); + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK) + if (!is_arm7_9(arm7_9)) { command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target"); - return ERROR_OK; + return ERROR_TARGET_INVALID; } if (argc > 0) @@ -3059,14 +3021,13 @@ COMMAND_HANDLER(handle_arm7_9_fast_memory_access_command) COMMAND_HANDLER(handle_arm7_9_dcc_downloads_command) { - target_t *target = get_current_target(cmd_ctx); - armv4_5_common_t *armv4_5; - struct arm7_9_common *arm7_9; + struct target *target = get_current_target(cmd_ctx); + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK) + if (!is_arm7_9(arm7_9)) { command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target"); - return ERROR_OK; + return ERROR_TARGET_INVALID; } if (argc > 0) @@ -3090,10 +3051,10 @@ COMMAND_HANDLER(handle_arm7_9_dcc_downloads_command) return ERROR_OK; } -int arm7_9_init_arch_info(target_t *target, struct arm7_9_common *arm7_9) +int arm7_9_init_arch_info(struct target *target, struct arm7_9_common *arm7_9) { int retval = ERROR_OK; - armv4_5_common_t *armv4_5 = &arm7_9->armv4_5_common; + struct arm *armv4_5 = &arm7_9->armv4_5_common; arm7_9->common_magic = ARM7_9_COMMON_MAGIC; @@ -3119,9 +3080,9 @@ int arm7_9_init_arch_info(target_t *target, struct arm7_9_common *arm7_9) 1, 1, target); } -int arm7_9_register_commands(struct command_context_s *cmd_ctx) +int arm7_9_register_commands(struct command_context *cmd_ctx) { - command_t *arm7_9_cmd; + struct command *arm7_9_cmd; arm7_9_cmd = register_command(cmd_ctx, NULL, "arm7_9", NULL, COMMAND_ANY, "arm7/9 specific commands");