X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Farm7tdmi.c;h=27a8337fcfc79c3b647b5a5cd9220883aa7ee2a3;hb=b7e4c26b9bb10e6e0ebfb07e5d43f0d62526cde2;hp=c9deb0ee1c17b7a75e0166f1c41de660857bb2b3;hpb=e86dee32004d750e8654fe449bfcdffaed7339fa;p=openocd.git diff --git a/src/target/arm7tdmi.c b/src/target/arm7tdmi.c index c9deb0ee1c..27a8337fcf 100644 --- a/src/target/arm7tdmi.c +++ b/src/target/arm7tdmi.c @@ -5,6 +5,9 @@ * Copyright (C) 2008 by Spencer Oliver * * spen@spen-soft.co.uk * * * + * Copyright (C) 2007,2008 Øyvind Harboe * + * oyvind.harboe@zylin.com * + * * * This program is free software; you can redistribute it and/or modify * * it under the terms of the GNU General Public License as published by * * the Free Software Foundation; either version 2 of the License, or * @@ -25,73 +28,20 @@ #endif #include "arm7tdmi.h" +#include "target_type.h" -#include "arm7_9_common.h" -#include "register.h" -#include "target.h" -#include "armv4_5.h" -#include "embeddedice.h" -#include "etm.h" -#include "log.h" -#include "jtag.h" -#include "arm_jtag.h" -#include -#include +/* + * For information about ARM7TDMI, see ARM DDI 0210C (r4p1) + * or ARM DDI 0029G (r3). "Debug In Depth", Appendix B, + * covers JTAG support. + */ #if 0 #define _DEBUG_INSTRUCTION_EXECUTION_ #endif -/* forward declarations */ - -int arm7tdmi_target_create(struct target_s *target,Jim_Interp *interp); -int arm7tdmi_quit(void); - -/* target function declarations */ -int arm7tdmi_poll(struct target_s *target); -int arm7tdmi_halt(target_t *target); - -target_type_t arm7tdmi_target = -{ - .name = "arm7tdmi", - - .poll = arm7_9_poll, - .arch_state = armv4_5_arch_state, - - .target_request_data = arm7_9_target_request_data, - - .halt = arm7_9_halt, - .resume = arm7_9_resume, - .step = arm7_9_step, - - .assert_reset = arm7_9_assert_reset, - .deassert_reset = arm7_9_deassert_reset, - .soft_reset_halt = arm7_9_soft_reset_halt, - - .get_gdb_reg_list = armv4_5_get_gdb_reg_list, - - .read_memory = arm7_9_read_memory, - .write_memory = arm7_9_write_memory, - .bulk_write_memory = arm7_9_bulk_write_memory, - .checksum_memory = arm7_9_checksum_memory, - .blank_check_memory = arm7_9_blank_check_memory, - - .run_algorithm = armv4_5_run_algorithm, - - .add_breakpoint = arm7_9_add_breakpoint, - .remove_breakpoint = arm7_9_remove_breakpoint, - .add_watchpoint = arm7_9_add_watchpoint, - .remove_watchpoint = arm7_9_remove_watchpoint, - - .register_commands = arm7tdmi_register_commands, - .target_create = arm7tdmi_target_create, - .init_target = arm7tdmi_init_target, - .examine = arm7tdmi_examine, - .quit = arm7tdmi_quit -}; - -int arm7tdmi_examine_debug_reason(target_t *target) +static int arm7tdmi_examine_debug_reason(target_t *target) { int retval = ERROR_OK; /* get pointers to arch-specific information */ @@ -103,39 +53,29 @@ int arm7tdmi_examine_debug_reason(target_t *target) && (target->debug_reason != DBG_REASON_SINGLESTEP)) { scan_field_t fields[2]; - u8 databus[4]; - u8 breakpoint; + uint8_t databus[4]; + uint8_t breakpoint; - jtag_add_end_state(TAP_DRPAUSE); + jtag_set_end_state(TAP_DRPAUSE); fields[0].tap = arm7_9->jtag_info.tap; fields[0].num_bits = 1; fields[0].out_value = NULL; - fields[0].in_value = &breakpoint; - - - fields[0].in_handler = NULL; - fields[1].tap = arm7_9->jtag_info.tap; fields[1].num_bits = 32; fields[1].out_value = NULL; - fields[1].in_value = databus; - - - fields[1].in_handler = NULL; - - if((retval = arm_jtag_scann(&arm7_9->jtag_info, 0x1)) != ERROR_OK) + if ((retval = arm_jtag_scann(&arm7_9->jtag_info, 0x1)) != ERROR_OK) { return retval; } arm_jtag_set_instr(&arm7_9->jtag_info, arm7_9->jtag_info.intest_instr, NULL); - jtag_add_dr_scan(2, fields, TAP_DRPAUSE); - if((retval = jtag_execute_queue()) != ERROR_OK) + jtag_add_dr_scan(2, fields, jtag_set_end_state(TAP_DRPAUSE)); + if ((retval = jtag_execute_queue()) != ERROR_OK) { return retval; } @@ -145,7 +85,7 @@ int arm7tdmi_examine_debug_reason(target_t *target) fields[1].in_value = NULL; fields[1].out_value = databus; - jtag_add_dr_scan(2, fields, TAP_DRPAUSE); + jtag_add_dr_scan(2, fields, jtag_set_end_state(TAP_DRPAUSE)); if (breakpoint & 1) target->debug_reason = DBG_REASON_WATCHPOINT; @@ -156,26 +96,32 @@ int arm7tdmi_examine_debug_reason(target_t *target) return ERROR_OK; } -static int arm7tdmi_num_bits[]={1, 32}; -static __inline int arm7tdmi_clock_out_inner(arm_jtag_t *jtag_info, u32 out, int breakpoint) +static const int arm7tdmi_num_bits[] = {1, 32}; + +static __inline int arm7tdmi_clock_out_inner(arm_jtag_t *jtag_info, uint32_t out, int breakpoint) { - u32 values[2]={breakpoint, flip_u32(out, 32)}; + uint32_t values[2]={breakpoint, flip_u32(out, 32)}; jtag_add_dr_out(jtag_info->tap, 2, arm7tdmi_num_bits, values, - TAP_INVALID); + jtag_get_end_state()); - jtag_add_runtest(0, TAP_INVALID); + jtag_add_runtest(0, jtag_get_end_state()); return ERROR_OK; } -/* put an instruction in the ARM7TDMI pipeline or write the data bus, and optionally read data */ -static __inline int arm7tdmi_clock_out(arm_jtag_t *jtag_info, u32 out, u32 *deprecated, int breakpoint) +/* put an instruction in the ARM7TDMI pipeline or write the data bus, + * and optionally read data + * + * FIXME remove the unused "deprecated" parameter + */ +static __inline int arm7tdmi_clock_out(arm_jtag_t *jtag_info, + uint32_t out, uint32_t *deprecated, int breakpoint) { - jtag_add_end_state(TAP_DRPAUSE); + jtag_set_end_state(TAP_DRPAUSE); arm_jtag_scann(jtag_info, 0x1); arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL); @@ -183,13 +129,13 @@ static __inline int arm7tdmi_clock_out(arm_jtag_t *jtag_info, u32 out, u32 *depr } /* clock the target, reading the databus */ -int arm7tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in) +static int arm7tdmi_clock_data_in(arm_jtag_t *jtag_info, uint32_t *in) { int retval = ERROR_OK; scan_field_t fields[2]; - jtag_add_end_state(TAP_DRPAUSE); - if((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK) + jtag_set_end_state(TAP_DRPAUSE); + if ((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK) { return retval; } @@ -198,59 +144,85 @@ int arm7tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in) fields[0].tap = jtag_info->tap; fields[0].num_bits = 1; fields[0].out_value = NULL; - fields[0].in_value = NULL; - - - fields[0].in_handler = NULL; - fields[1].tap = jtag_info->tap; fields[1].num_bits = 32; fields[1].out_value = NULL; - - fields[1].in_value = NULL; - fields[1].in_handler = arm_jtag_buf_to_u32_flip; /* deprecated! invoke this from user code! */ - fields[1].in_handler_priv = in; - - + fields[1].in_value = (uint8_t *)in; - jtag_add_dr_scan(2, fields, TAP_INVALID); + jtag_add_dr_scan(2, fields, jtag_get_end_state()); - jtag_add_runtest(0, TAP_INVALID); + jtag_add_callback(arm7flip32, (jtag_callback_data_t)in); + + jtag_add_runtest(0, jtag_get_end_state()); #ifdef _DEBUG_INSTRUCTION_EXECUTION_ -{ - if((retval = jtag_execute_queue()) != ERROR_OK) - { - return retval; - } + if ((retval = jtag_execute_queue()) != ERROR_OK) + return retval; - if (in) - { - LOG_DEBUG("in: 0x%8.8x", *in); - } - else - { - LOG_ERROR("BUG: called with in == NULL"); - } -} + if (in) + LOG_DEBUG("in: 0x%8.8x", *in); + else + LOG_ERROR("BUG: called with in == NULL"); #endif return ERROR_OK; } +void arm_endianness(uint8_t *tmp, void *in, int size, int be, int flip) +{ + uint32_t readback = le_to_h_u32(tmp); + if (flip) + readback = flip_u32(readback, 32); + switch (size) + { + case 4: + if (be) + { + h_u32_to_be(((uint8_t*)in), readback); + } else + { + h_u32_to_le(((uint8_t*)in), readback); + } + break; + case 2: + if (be) + { + h_u16_to_be(((uint8_t*)in), readback & 0xffff); + } else + { + h_u16_to_le(((uint8_t*)in), readback & 0xffff); + } + break; + case 1: + *((uint8_t *)in)= readback & 0xff; + break; + } +} + +static int arm7endianness(jtag_callback_data_t arg, + jtag_callback_data_t size, jtag_callback_data_t be, + jtag_callback_data_t captured) +{ + uint8_t *in = (uint8_t *)arg; + + arm_endianness((uint8_t *)captured, in, (int)size, (int)be, 1); + return ERROR_OK; +} + /* clock the target, and read the databus * the *in pointer points to a buffer where elements of 'size' bytes - * are stored in big (be==1) or little (be==0) endianness + * are stored in big (be == 1) or little (be == 0) endianness */ -int arm7tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size, int be) +static int arm7tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, + void *in, int size, int be) { int retval = ERROR_OK; scan_field_t fields[2]; - jtag_add_end_state(TAP_DRPAUSE); - if((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK) + jtag_set_end_state(TAP_DRPAUSE); + if ((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK) { return retval; } @@ -259,48 +231,29 @@ int arm7tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size, fields[0].tap = jtag_info->tap; fields[0].num_bits = 1; fields[0].out_value = NULL; - fields[0].in_value = NULL; - - - fields[0].in_handler = NULL; - fields[1].tap = jtag_info->tap; fields[1].num_bits = 32; fields[1].out_value = NULL; - - fields[1].in_value = NULL; - switch (size) - { - case 4: - fields[1].in_handler = (be) ? arm_jtag_buf_to_be32_flip : arm_jtag_buf_to_le32_flip; /* deprecated! invoke this from user code! */ - break; - case 2: - fields[1].in_handler = (be) ? arm_jtag_buf_to_be16_flip : arm_jtag_buf_to_le16_flip; /* deprecated! invoke this from user code! */ - break; - case 1: - fields[1].in_handler = arm_jtag_buf_to_8_flip; /* deprecated! invoke this from user code! */ - break; - } - fields[1].in_handler_priv = in; - - + jtag_alloc_in_value32(&fields[1]); + + jtag_add_dr_scan(2, fields, jtag_get_end_state()); - jtag_add_dr_scan(2, fields, TAP_INVALID); + jtag_add_callback4(arm7endianness, (jtag_callback_data_t)in, (jtag_callback_data_t)size, (jtag_callback_data_t)be, (jtag_callback_data_t)fields[1].in_value); - jtag_add_runtest(0, TAP_INVALID); + jtag_add_runtest(0, jtag_get_end_state()); #ifdef _DEBUG_INSTRUCTION_EXECUTION_ { - if((retval = jtag_execute_queue()) != ERROR_OK) + if ((retval = jtag_execute_queue()) != ERROR_OK) { return retval; } if (in) { - LOG_DEBUG("in: 0x%8.8x", *(u32*)in); + LOG_DEBUG("in: 0x%8.8x", *(uint32_t*)in); } else { @@ -312,7 +265,8 @@ int arm7tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size, return ERROR_OK; } -void arm7tdmi_change_to_arm(target_t *target, u32 *r0, u32 *pc) +static void arm7tdmi_change_to_arm(target_t *target, + uint32_t *r0, uint32_t *pc) { /* get pointers to arch-specific information */ armv4_5_common_t *armv4_5 = target->arch_info; @@ -362,7 +316,15 @@ void arm7tdmi_change_to_arm(target_t *target, u32 *r0, u32 *pc) *pc -= 0xa; } -void arm7tdmi_read_core_regs(target_t *target, u32 mask, u32* core_regs[16]) + +/* FIX!!! is this a potential performance bottleneck w.r.t. requiring too many + * roundtrips when jtag_execute_queue() has a large overhead(e.g. for USB)s? + * + * The solution is to arrange for a large out/in scan in this loop and + * and convert data afterwards. + */ +static void arm7tdmi_read_core_regs(target_t *target, + uint32_t mask, uint32_t* core_regs[16]) { int i; /* get pointers to arch-specific information */ @@ -383,12 +345,13 @@ void arm7tdmi_read_core_regs(target_t *target, u32 mask, u32* core_regs[16]) for (i = 0; i <= 15; i++) { if (mask & (1 << i)) - /* nothing fetched, STM still in EXECUTE (1+i cycle) */ + /* nothing fetched, STM still in EXECUTE (1 + i cycle) */ arm7tdmi_clock_data_in(jtag_info, core_regs[i]); } } -void arm7tdmi_read_core_regs_target_buffer(target_t *target, u32 mask, void* buffer, int size) +static void arm7tdmi_read_core_regs_target_buffer(target_t *target, + uint32_t mask, void* buffer, int size) { int i; /* get pointers to arch-specific information */ @@ -396,9 +359,9 @@ void arm7tdmi_read_core_regs_target_buffer(target_t *target, u32 mask, void* buf arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm_jtag_t *jtag_info = &arm7_9->jtag_info; int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0; - u32 *buf_u32 = buffer; - u16 *buf_u16 = buffer; - u8 *buf_u8 = buffer; + uint32_t *buf_u32 = buffer; + uint16_t *buf_u16 = buffer; + uint8_t *buf_u8 = buffer; /* STMIA r0-15, [r0] at debug speed * register values will start to appear on 4th DCLK @@ -412,7 +375,7 @@ void arm7tdmi_read_core_regs_target_buffer(target_t *target, u32 mask, void* buf for (i = 0; i <= 15; i++) { - /* nothing fetched, STM still in EXECUTE (1+i cycle), read databus */ + /* nothing fetched, STM still in EXECUTE (1 + i cycle), read databus */ if (mask & (1 << i)) { switch (size) @@ -431,7 +394,7 @@ void arm7tdmi_read_core_regs_target_buffer(target_t *target, u32 mask, void* buf } } -void arm7tdmi_read_xpsr(target_t *target, u32 *xpsr, int spsr) +static void arm7tdmi_read_xpsr(target_t *target, uint32_t *xpsr, int spsr) { /* get pointers to arch-specific information */ armv4_5_common_t *armv4_5 = target->arch_info; @@ -451,14 +414,14 @@ void arm7tdmi_read_xpsr(target_t *target, u32 *xpsr, int spsr) arm7tdmi_clock_data_in(jtag_info, xpsr); } -void arm7tdmi_write_xpsr(target_t *target, u32 xpsr, int spsr) +static void arm7tdmi_write_xpsr(target_t *target, uint32_t xpsr, int spsr) { /* get pointers to arch-specific information */ armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm_jtag_t *jtag_info = &arm7_9->jtag_info; - LOG_DEBUG("xpsr: %8.8x, spsr: %i", xpsr, spsr); + LOG_DEBUG("xpsr: %8.8" PRIx32 ", spsr: %i", xpsr, spsr); /* MSR1 fetched */ arm7tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr & 0xff, 0, 1, spsr), NULL, 0); @@ -482,7 +445,8 @@ void arm7tdmi_write_xpsr(target_t *target, u32 xpsr, int spsr) arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0); } -void arm7tdmi_write_xpsr_im8(target_t *target, u8 xpsr_im, int rot, int spsr) +static void arm7tdmi_write_xpsr_im8(target_t *target, + uint8_t xpsr_im, int rot, int spsr) { /* get pointers to arch-specific information */ armv4_5_common_t *armv4_5 = target->arch_info; @@ -501,7 +465,8 @@ void arm7tdmi_write_xpsr_im8(target_t *target, u8 xpsr_im, int rot, int spsr) arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0); } -void arm7tdmi_write_core_regs(target_t *target, u32 mask, u32 core_regs[16]) +static void arm7tdmi_write_core_regs(target_t *target, + uint32_t mask, uint32_t core_regs[16]) { int i; /* get pointers to arch-specific information */ @@ -522,13 +487,13 @@ void arm7tdmi_write_core_regs(target_t *target, u32 mask, u32 core_regs[16]) for (i = 0; i <= 15; i++) { if (mask & (1 << i)) - /* nothing fetched, LDM still in EXECUTE (1+i cycle) */ + /* nothing fetched, LDM still in EXECUTE (1 + i cycle) */ arm7tdmi_clock_out_inner(jtag_info, core_regs[i], 0); } arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0); } -void arm7tdmi_load_word_regs(target_t *target, u32 mask) +static void arm7tdmi_load_word_regs(target_t *target, uint32_t mask) { /* get pointers to arch-specific information */ armv4_5_common_t *armv4_5 = target->arch_info; @@ -541,7 +506,7 @@ void arm7tdmi_load_word_regs(target_t *target, u32 mask) arm7tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 1), NULL, 0); } -void arm7tdmi_load_hword_reg(target_t *target, int num) +static void arm7tdmi_load_hword_reg(target_t *target, int num) { /* get pointers to arch-specific information */ armv4_5_common_t *armv4_5 = target->arch_info; @@ -554,7 +519,7 @@ void arm7tdmi_load_hword_reg(target_t *target, int num) arm7tdmi_clock_out(jtag_info, ARMV4_5_LDRH_IP(num, 0), NULL, 0); } -void arm7tdmi_load_byte_reg(target_t *target, int num) +static void arm7tdmi_load_byte_reg(target_t *target, int num) { /* get pointers to arch-specific information */ armv4_5_common_t *armv4_5 = target->arch_info; @@ -567,7 +532,7 @@ void arm7tdmi_load_byte_reg(target_t *target, int num) arm7tdmi_clock_out(jtag_info, ARMV4_5_LDRB_IP(num, 0), NULL, 0); } -void arm7tdmi_store_word_regs(target_t *target, u32 mask) +static void arm7tdmi_store_word_regs(target_t *target, uint32_t mask) { /* get pointers to arch-specific information */ armv4_5_common_t *armv4_5 = target->arch_info; @@ -580,7 +545,7 @@ void arm7tdmi_store_word_regs(target_t *target, u32 mask) arm7tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask, 0, 1), NULL, 0); } -void arm7tdmi_store_hword_reg(target_t *target, int num) +static void arm7tdmi_store_hword_reg(target_t *target, int num) { /* get pointers to arch-specific information */ armv4_5_common_t *armv4_5 = target->arch_info; @@ -593,7 +558,7 @@ void arm7tdmi_store_hword_reg(target_t *target, int num) arm7tdmi_clock_out(jtag_info, ARMV4_5_STRH_IP(num, 0), NULL, 0); } -void arm7tdmi_store_byte_reg(target_t *target, int num) +static void arm7tdmi_store_byte_reg(target_t *target, int num) { /* get pointers to arch-specific information */ armv4_5_common_t *armv4_5 = target->arch_info; @@ -606,7 +571,7 @@ void arm7tdmi_store_byte_reg(target_t *target, int num) arm7tdmi_clock_out(jtag_info, ARMV4_5_STRB_IP(num, 0), NULL, 0); } -void arm7tdmi_write_pc(target_t *target, u32 pc) +static void arm7tdmi_write_pc(target_t *target, uint32_t pc) { /* get pointers to arch-specific information */ armv4_5_common_t *armv4_5 = target->arch_info; @@ -633,7 +598,7 @@ void arm7tdmi_write_pc(target_t *target, u32 pc) arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0); } -void arm7tdmi_branch_resume(target_t *target) +static void arm7tdmi_branch_resume(target_t *target) { /* get pointers to arch-specific information */ armv4_5_common_t *armv4_5 = target->arch_info; @@ -644,7 +609,7 @@ void arm7tdmi_branch_resume(target_t *target) arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_B(0xfffffa, 0), 0); } -void arm7tdmi_branch_resume_thumb(target_t *target) +static void arm7tdmi_branch_resume_thumb(target_t *target) { LOG_DEBUG("-"); @@ -705,7 +670,7 @@ void arm7tdmi_branch_resume_thumb(target_t *target) arm7tdmi_clock_out(jtag_info, ARMV4_5_T_B(0x7f8), NULL, 0); } -void arm7tdmi_build_reg_cache(target_t *target) +static void arm7tdmi_build_reg_cache(target_t *target) { reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache); /* get pointers to arch-specific information */ @@ -720,12 +685,12 @@ int arm7tdmi_examine(struct target_s *target) int retval; armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; - if (!target->type->examined) + if (!target_was_examined(target)) { /* get pointers to arch-specific information */ reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache); - reg_cache_t *t=embeddedice_build_reg_cache(target, arm7_9); - if (t==NULL) + reg_cache_t *t = embeddedice_build_reg_cache(target, arm7_9); + if (t == NULL) return ERROR_FAIL; (*cache_p) = t; @@ -737,15 +702,15 @@ int arm7tdmi_examine(struct target_s *target) (*cache_p)->next = etm_build_reg_cache(target, jtag_info, arm7_9->etm_ctx); arm7_9->etm_ctx->reg_cache = (*cache_p)->next; } - target->type->examined = 1; + target_set_examined(target); } - if ((retval=embeddedice_setup(target))!=ERROR_OK) + if ((retval = embeddedice_setup(target)) != ERROR_OK) return retval; - if ((retval=arm7_9_setup(target))!=ERROR_OK) + if ((retval = arm7_9_setup(target)) != ERROR_OK) return retval; if (arm7_9->etm_ctx) { - if ((retval=etm_setup(target))!=ERROR_OK) + if ((retval = etm_setup(target)) != ERROR_OK) return retval; } return ERROR_OK; @@ -758,11 +723,6 @@ int arm7tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *tar return ERROR_OK; } -int arm7tdmi_quit(void) -{ - return ERROR_OK; -} - int arm7tdmi_init_arch_info(target_t *target, arm7tdmi_common_t *arm7tdmi, jtag_tap_t *tap) { armv4_5_common_t *armv4_5; @@ -801,7 +761,6 @@ int arm7tdmi_init_arch_info(target_t *target, arm7tdmi_common_t *arm7tdmi, jtag_ arm7_9->enable_single_step = arm7_9_enable_eice_step; arm7_9->disable_single_step = arm7_9_disable_eice_step; - arm7_9->pre_debug_entry = NULL; arm7_9->post_debug_entry = NULL; arm7_9->pre_restore_context = NULL; @@ -822,21 +781,52 @@ int arm7tdmi_init_arch_info(target_t *target, arm7tdmi_common_t *arm7tdmi, jtag_ return ERROR_OK; } -int arm7tdmi_target_create( struct target_s *target, Jim_Interp *interp ) +static int arm7tdmi_target_create(struct target_s *target, Jim_Interp *interp) { arm7tdmi_common_t *arm7tdmi; arm7tdmi = calloc(1,sizeof(arm7tdmi_common_t)); arm7tdmi_init_arch_info(target, arm7tdmi, target->tap); + arm7tdmi->arm7_9_common.armv4_5_common.is_armv4 = true; return ERROR_OK; } -int arm7tdmi_register_commands(struct command_context_s *cmd_ctx) +/** Holds methods for ARM7TDMI targets. */ +target_type_t arm7tdmi_target = { - int retval; + .name = "arm7tdmi", - retval = arm7_9_register_commands(cmd_ctx); + .poll = arm7_9_poll, + .arch_state = armv4_5_arch_state, - return retval; -} + .target_request_data = arm7_9_target_request_data, + + .halt = arm7_9_halt, + .resume = arm7_9_resume, + .step = arm7_9_step, + + .assert_reset = arm7_9_assert_reset, + .deassert_reset = arm7_9_deassert_reset, + .soft_reset_halt = arm7_9_soft_reset_halt, + + .get_gdb_reg_list = armv4_5_get_gdb_reg_list, + + .read_memory = arm7_9_read_memory, + .write_memory = arm7_9_write_memory, + .bulk_write_memory = arm7_9_bulk_write_memory, + .checksum_memory = arm7_9_checksum_memory, + .blank_check_memory = arm7_9_blank_check_memory, + + .run_algorithm = armv4_5_run_algorithm, + + .add_breakpoint = arm7_9_add_breakpoint, + .remove_breakpoint = arm7_9_remove_breakpoint, + .add_watchpoint = arm7_9_add_watchpoint, + .remove_watchpoint = arm7_9_remove_watchpoint, + + .register_commands = arm7_9_register_commands, + .target_create = arm7tdmi_target_create, + .init_target = arm7tdmi_init_target, + .examine = arm7tdmi_examine, +};