X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Farm7tdmi.c;h=b0348392f0096af39d172fbfc87492a2fb7f7c70;hb=da15f9f8c29064f0124e60ac0ac21ddd11fdcc2c;hp=634aa2997f42700bab3d85f050690e82df970d04;hpb=0989cd4d5d69850df38122f9ba1e7d5b4009fb51;p=openocd.git

diff --git a/src/target/arm7tdmi.c b/src/target/arm7tdmi.c
index 634aa2997f..b0348392f0 100644
--- a/src/target/arm7tdmi.c
+++ b/src/target/arm7tdmi.c
@@ -19,9 +19,7 @@
  *   GNU General Public License for more details.                          *
  *                                                                         *
  *   You should have received a copy of the GNU General Public License     *
- *   along with this program; if not, write to the                         *
- *   Free Software Foundation, Inc.,                                       *
- *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
+ *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  ***************************************************************************/
 
 #ifdef HAVE_CONFIG_H
@@ -32,6 +30,7 @@
 #include "target_type.h"
 #include "register.h"
 #include "arm_opcodes.h"
+#include "arm_semihosting.h"
 
 /*
  * For information about ARM7TDMI, see ARM DDI 0210C (r4p1)
@@ -66,7 +65,7 @@ static int arm7tdmi_examine_debug_reason(struct target *target)
 		retval = arm_jtag_scann(&arm7_9->jtag_info, 0x1, TAP_DRPAUSE);
 		if (retval != ERROR_OK)
 			return retval;
-		retval = arm_jtag_set_instr(&arm7_9->jtag_info, arm7_9->jtag_info.intest_instr, NULL, TAP_DRPAUSE);
+		retval = arm_jtag_set_instr(arm7_9->jtag_info.tap, arm7_9->jtag_info.intest_instr, NULL, TAP_DRPAUSE);
 		if (retval != ERROR_OK)
 			return retval;
 
@@ -95,12 +94,18 @@ static const int arm7tdmi_num_bits[] = {1, 32};
 
 static inline int arm7tdmi_clock_out_inner(struct arm_jtag *jtag_info, uint32_t out, int breakpoint)
 {
-	uint32_t values[2] = {breakpoint, flip_u32(out, 32)};
+	uint8_t bp = breakpoint ? 1 : 0;
+	uint8_t out_value[4];
+	buf_set_u32(out_value, 0, 32, flip_u32(out, 32));
 
-	jtag_add_dr_out(jtag_info->tap,
+	struct scan_field fields[2] = {
+			{ .num_bits = arm7tdmi_num_bits[0], .out_value = &bp },
+			{ .num_bits = arm7tdmi_num_bits[1], .out_value = out_value },
+	};
+
+	jtag_add_dr_scan(jtag_info->tap,
 			2,
-			arm7tdmi_num_bits,
-			values,
+			fields,
 			TAP_DRPAUSE);
 
 	jtag_add_runtest(0, TAP_DRPAUSE);
@@ -110,17 +115,15 @@ static inline int arm7tdmi_clock_out_inner(struct arm_jtag *jtag_info, uint32_t
 
 /* put an instruction in the ARM7TDMI pipeline or write the data bus,
  * and optionally read data
- *
- * FIXME remove the unused "deprecated" parameter
  */
 static inline int arm7tdmi_clock_out(struct arm_jtag *jtag_info,
-		uint32_t out, uint32_t *deprecated, int breakpoint)
+		uint32_t out, int breakpoint)
 {
 	int retval;
 	retval = arm_jtag_scann(jtag_info, 0x1, TAP_DRPAUSE);
 	if (retval != ERROR_OK)
 		return retval;
-	retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_DRPAUSE);
+	retval = arm_jtag_set_instr(jtag_info->tap, jtag_info->intest_instr, NULL, TAP_DRPAUSE);
 	if (retval != ERROR_OK)
 		return retval;
 
@@ -136,7 +139,7 @@ static int arm7tdmi_clock_data_in(struct arm_jtag *jtag_info, uint32_t *in)
 	retval = arm_jtag_scann(jtag_info, 0x1, TAP_DRPAUSE);
 	if (retval != ERROR_OK)
 		return retval;
-	retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_DRPAUSE);
+	retval = arm_jtag_set_instr(jtag_info->tap, jtag_info->intest_instr, NULL, TAP_DRPAUSE);
 	if (retval != ERROR_OK)
 		return retval;
 
@@ -181,7 +184,7 @@ static int arm7tdmi_clock_data_in_endianness(struct arm_jtag *jtag_info,
 	retval = arm_jtag_scann(jtag_info, 0x1, TAP_DRPAUSE);
 	if (retval != ERROR_OK)
 		return retval;
-	retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_DRPAUSE);
+	retval = arm_jtag_set_instr(jtag_info->tap, jtag_info->intest_instr, NULL, TAP_DRPAUSE);
 	if (retval != ERROR_OK)
 		return retval;
 
@@ -241,35 +244,35 @@ static void arm7tdmi_change_to_arm(struct target *target,
 	 * to allow common handling of ARM and THUMB debugging */
 
 	/* fetch STR r0, [r0] */
-	arm7tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), NULL, 0);
-	arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
-	arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
+	arm7tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), 0);
+	arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0);
+	arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0);
 	/* nothing fetched, STR r0, [r0] in Execute (2) */
 	arm7tdmi_clock_data_in(jtag_info, r0);
 
 	/* MOV r0, r15 fetched, STR in Decode */
-	arm7tdmi_clock_out(jtag_info, ARMV4_5_T_MOV(0, 15), NULL, 0);
-	arm7tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), NULL, 0);
-	arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
-	arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
+	arm7tdmi_clock_out(jtag_info, ARMV4_5_T_MOV(0, 15), 0);
+	arm7tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), 0);
+	arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0);
+	arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0);
 	/* nothing fetched, STR r0, [r0] in Execute (2) */
 	arm7tdmi_clock_data_in(jtag_info, pc);
 
 	/* use pc-relative LDR to clear r0[1:0] (for switch to ARM mode) */
-	arm7tdmi_clock_out(jtag_info, ARMV4_5_T_LDR_PCREL(0), NULL, 0);
-	arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
-	arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
+	arm7tdmi_clock_out(jtag_info, ARMV4_5_T_LDR_PCREL(0), 0);
+	arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0);
+	arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0);
 	/* nothing fetched, data for LDR r0, [PC, #0] */
-	arm7tdmi_clock_out(jtag_info, 0x0, NULL, 0);
+	arm7tdmi_clock_out(jtag_info, 0x0, 0);
 	/* nothing fetched, data from previous cycle is written to register */
-	arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
+	arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0);
 
 	/* fetch BX */
-	arm7tdmi_clock_out(jtag_info, ARMV4_5_T_BX(0), NULL, 0);
+	arm7tdmi_clock_out(jtag_info, ARMV4_5_T_BX(0), 0);
 	/* NOP fetched, BX in Decode, MOV in Execute */
-	arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
+	arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0);
 	/* NOP fetched, BX in Execute (1) */
-	arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
+	arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0);
 
 	jtag_execute_queue();
 
@@ -296,12 +299,12 @@ static void arm7tdmi_read_core_regs(struct target *target,
 	/* STMIA r0-15, [r0] at debug speed
 	 * register values will start to appear on 4th DCLK
 	 */
-	arm7tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), NULL, 0);
+	arm7tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), 0);
 
 	/* fetch NOP, STM in DECODE stage */
-	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
+	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0);
 	/* fetch NOP, STM in EXECUTE stage (1st cycle) */
-	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
+	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0);
 
 	for (i = 0; i <= 15; i++) {
 		if (mask & (1 << i))
@@ -324,12 +327,12 @@ static void arm7tdmi_read_core_regs_target_buffer(struct target *target,
 	/* STMIA r0-15, [r0] at debug speed
 	 * register values will start to appear on 4th DCLK
 	 */
-	arm7tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), NULL, 0);
+	arm7tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), 0);
 
 	/* fetch NOP, STM in DECODE stage */
-	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
+	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0);
 	/* fetch NOP, STM in EXECUTE stage (1st cycle) */
-	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
+	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0);
 
 	for (i = 0; i <= 15; i++) {
 		/* nothing fetched, STM still in EXECUTE (1 + i cycle), read databus */
@@ -355,14 +358,14 @@ static void arm7tdmi_read_xpsr(struct target *target, uint32_t *xpsr, int spsr)
 	struct arm_jtag *jtag_info = &arm7_9->jtag_info;
 
 	/* MRS r0, cpsr */
-	arm7tdmi_clock_out(jtag_info, ARMV4_5_MRS(0, spsr & 1), NULL, 0);
+	arm7tdmi_clock_out(jtag_info, ARMV4_5_MRS(0, spsr & 1), 0);
 
 	/* STR r0, [r15] */
-	arm7tdmi_clock_out(jtag_info, ARMV4_5_STR(0, 15), NULL, 0);
+	arm7tdmi_clock_out(jtag_info, ARMV4_5_STR(0, 15), 0);
 	/* fetch NOP, STR in DECODE stage */
-	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
+	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0);
 	/* fetch NOP, STR in EXECUTE stage (1st cycle) */
-	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
+	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0);
 	/* nothing fetched, STR still in EXECUTE (2nd cycle) */
 	arm7tdmi_clock_data_in(jtag_info, xpsr);
 }
@@ -375,25 +378,25 @@ static void arm7tdmi_write_xpsr(struct target *target, uint32_t xpsr, int spsr)
 	LOG_DEBUG("xpsr: %8.8" PRIx32 ", spsr: %i", xpsr, spsr);
 
 	/* MSR1 fetched */
-	arm7tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr & 0xff, 0, 1, spsr), NULL, 0);
+	arm7tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr & 0xff, 0, 1, spsr), 0);
 	/* MSR2 fetched, MSR1 in DECODE */
-	arm7tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff00) >> 8, 0xc, 2, spsr), NULL, 0);
+	arm7tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff00) >> 8, 0xc, 2, spsr), 0);
 	/* MSR3 fetched, MSR1 in EXECUTE (1), MSR2 in DECODE */
-	arm7tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff0000) >> 16, 0x8, 4, spsr), NULL, 0);
+	arm7tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff0000) >> 16, 0x8, 4, spsr), 0);
 	/* nothing fetched, MSR1 in EXECUTE (2) */
-	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
+	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0);
 	/* MSR4 fetched, MSR2 in EXECUTE (1), MSR3 in DECODE */
-	arm7tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff000000) >> 24, 0x4, 8, spsr), NULL, 0);
+	arm7tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff000000) >> 24, 0x4, 8, spsr), 0);
 	/* nothing fetched, MSR2 in EXECUTE (2) */
-	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
+	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0);
 	/* NOP fetched, MSR3 in EXECUTE (1), MSR4 in DECODE */
-	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
+	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0);
 	/* nothing fetched, MSR3 in EXECUTE (2) */
-	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
+	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0);
 	/* NOP fetched, MSR4 in EXECUTE (1) */
-	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
+	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0);
 	/* nothing fetched, MSR4 in EXECUTE (2) */
-	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
+	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0);
 }
 
 static void arm7tdmi_write_xpsr_im8(struct target *target,
@@ -405,13 +408,13 @@ static void arm7tdmi_write_xpsr_im8(struct target *target,
 	LOG_DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr);
 
 	/* MSR fetched */
-	arm7tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr_im, rot, 1, spsr), NULL, 0);
+	arm7tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr_im, rot, 1, spsr), 0);
 	/* NOP fetched, MSR in DECODE */
-	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
+	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0);
 	/* NOP fetched, MSR in EXECUTE (1) */
-	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
+	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0);
 	/* nothing fetched, MSR in EXECUTE (2) */
-	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
+	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0);
 }
 
 static void arm7tdmi_write_core_regs(struct target *target,
@@ -424,7 +427,7 @@ static void arm7tdmi_write_core_regs(struct target *target,
 	/* LDMIA r0-15, [r0] at debug speed
 	* register values will start to appear on 4th DCLK
 	*/
-	arm7tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 0), NULL, 0);
+	arm7tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 0), 0);
 
 	/* fetch NOP, LDM in DECODE stage */
 	arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0);
@@ -445,9 +448,9 @@ static void arm7tdmi_load_word_regs(struct target *target, uint32_t mask)
 	struct arm_jtag *jtag_info = &arm7_9->jtag_info;
 
 	/* put system-speed load-multiple into the pipeline */
-	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
-	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);
-	arm7tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 1), NULL, 0);
+	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0);
+	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 1);
+	arm7tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 1), 0);
 }
 
 static void arm7tdmi_load_hword_reg(struct target *target, int num)
@@ -456,9 +459,9 @@ static void arm7tdmi_load_hword_reg(struct target *target, int num)
 	struct arm_jtag *jtag_info = &arm7_9->jtag_info;
 
 	/* put system-speed load half-word into the pipeline */
-	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
-	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);
-	arm7tdmi_clock_out(jtag_info, ARMV4_5_LDRH_IP(num, 0), NULL, 0);
+	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0);
+	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 1);
+	arm7tdmi_clock_out(jtag_info, ARMV4_5_LDRH_IP(num, 0), 0);
 }
 
 static void arm7tdmi_load_byte_reg(struct target *target, int num)
@@ -467,9 +470,9 @@ static void arm7tdmi_load_byte_reg(struct target *target, int num)
 	struct arm_jtag *jtag_info = &arm7_9->jtag_info;
 
 	/* put system-speed load byte into the pipeline */
-	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
-	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);
-	arm7tdmi_clock_out(jtag_info, ARMV4_5_LDRB_IP(num, 0), NULL, 0);
+	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0);
+	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 1);
+	arm7tdmi_clock_out(jtag_info, ARMV4_5_LDRB_IP(num, 0), 0);
 }
 
 static void arm7tdmi_store_word_regs(struct target *target, uint32_t mask)
@@ -478,9 +481,9 @@ static void arm7tdmi_store_word_regs(struct target *target, uint32_t mask)
 	struct arm_jtag *jtag_info = &arm7_9->jtag_info;
 
 	/* put system-speed store-multiple into the pipeline */
-	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
-	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);
-	arm7tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask, 0, 1), NULL, 0);
+	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0);
+	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 1);
+	arm7tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask, 0, 1), 0);
 }
 
 static void arm7tdmi_store_hword_reg(struct target *target, int num)
@@ -489,9 +492,9 @@ static void arm7tdmi_store_hword_reg(struct target *target, int num)
 	struct arm_jtag *jtag_info = &arm7_9->jtag_info;
 
 	/* put system-speed store half-word into the pipeline */
-	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
-	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);
-	arm7tdmi_clock_out(jtag_info, ARMV4_5_STRH_IP(num, 0), NULL, 0);
+	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0);
+	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 1);
+	arm7tdmi_clock_out(jtag_info, ARMV4_5_STRH_IP(num, 0), 0);
 }
 
 static void arm7tdmi_store_byte_reg(struct target *target, int num)
@@ -500,9 +503,9 @@ static void arm7tdmi_store_byte_reg(struct target *target, int num)
 	struct arm_jtag *jtag_info = &arm7_9->jtag_info;
 
 	/* put system-speed store byte into the pipeline */
-	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
-	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);
-	arm7tdmi_clock_out(jtag_info, ARMV4_5_STRB_IP(num, 0), NULL, 0);
+	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0);
+	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 1);
+	arm7tdmi_clock_out(jtag_info, ARMV4_5_STRB_IP(num, 0), 0);
 }
 
 static void arm7tdmi_write_pc(struct target *target, uint32_t pc)
@@ -513,7 +516,7 @@ static void arm7tdmi_write_pc(struct target *target, uint32_t pc)
 	/* LDMIA r0-15, [r0] at debug speed
 	 * register values will start to appear on 4th DCLK
 	 */
-	arm7tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 0x8000, 0, 0), NULL, 0);
+	arm7tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 0x8000, 0, 0), 0);
 	/* fetch NOP, LDM in DECODE stage */
 	arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0);
 	/* fetch NOP, LDM in EXECUTE stage (1st cycle) */
@@ -535,7 +538,7 @@ static void arm7tdmi_branch_resume(struct target *target)
 	struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
 	struct arm_jtag *jtag_info = &arm7_9->jtag_info;
 
-	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);
+	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 1);
 	arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_B(0xfffffa, 0), 0);
 }
 
@@ -551,53 +554,52 @@ static void arm7tdmi_branch_resume_thumb(struct target *target)
 	/* LDMIA r0, [r0] at debug speed
 	 * register values will start to appear on 4th DCLK
 	 */
-	arm7tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 0x1, 0, 0), NULL, 0);
+	arm7tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 0x1, 0, 0), 0);
 
 	/* fetch NOP, LDM in DECODE stage */
-	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
+	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0);
 	/* fetch NOP, LDM in EXECUTE stage (1st cycle) */
-	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
+	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0);
 	/* nothing fetched, LDM in EXECUTE stage (2nd cycle) */
-	arm7tdmi_clock_out(jtag_info,
-			buf_get_u32(arm->pc->value, 0, 32) | 1, NULL, 0);
+	arm7tdmi_clock_out(jtag_info, buf_get_u32(arm->pc->value, 0, 32) | 1, 0);
 	/* nothing fetched, LDM in EXECUTE stage (3rd cycle) */
-	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
+	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0);
 
 	/* Branch and eXchange */
-	arm7tdmi_clock_out(jtag_info, ARMV4_5_BX(0), NULL, 0);
+	arm7tdmi_clock_out(jtag_info, ARMV4_5_BX(0), 0);
 
 	embeddedice_read_reg(dbg_stat);
 
 	/* fetch NOP, BX in DECODE stage */
-	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
+	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0);
 
 	/* target is now in Thumb state */
 	embeddedice_read_reg(dbg_stat);
 
 	/* fetch NOP, BX in EXECUTE stage (1st cycle) */
-	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
+	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0);
 
 	/* target is now in Thumb state */
 	embeddedice_read_reg(dbg_stat);
 
 	/* load r0 value */
-	arm7tdmi_clock_out(jtag_info, ARMV4_5_T_LDR_PCREL(0), NULL, 0);
+	arm7tdmi_clock_out(jtag_info, ARMV4_5_T_LDR_PCREL(0), 0);
 	/* fetch NOP, LDR in Decode */
-	arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
+	arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0);
 	/* fetch NOP, LDR in Execute */
-	arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
+	arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0);
 	/* nothing fetched, LDR in EXECUTE stage (2nd cycle) */
-	arm7tdmi_clock_out(jtag_info, buf_get_u32(arm->core_cache->reg_list[0].value, 0, 32), NULL, 0);
+	arm7tdmi_clock_out(jtag_info, buf_get_u32(arm->core_cache->reg_list[0].value, 0, 32), 0);
 	/* nothing fetched, LDR in EXECUTE stage (3rd cycle) */
-	arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
+	arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0);
 
-	arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
-	arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
+	arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0);
+	arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0);
 
 	embeddedice_read_reg(dbg_stat);
 
-	arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 1);
-	arm7tdmi_clock_out(jtag_info, ARMV4_5_T_B(0x7f8), NULL, 0);
+	arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 1);
+	arm7tdmi_clock_out(jtag_info, ARMV4_5_T_B(0x7f8), 0);
 }
 
 static void arm7tdmi_build_reg_cache(struct target *target)
@@ -608,13 +610,25 @@ static void arm7tdmi_build_reg_cache(struct target *target)
 	(*cache_p) = arm_build_reg_cache(target, arm);
 }
 
+static void arm7tdmi_free_reg_cache(struct target *target)
+{
+	struct arm *arm = target_to_arm(target);
+
+	arm_free_reg_cache(arm);
+}
+
 int arm7tdmi_init_target(struct command_context *cmd_ctx, struct target *target)
 {
 	arm7tdmi_build_reg_cache(target);
-
+	arm_semihosting_init(target);
 	return ERROR_OK;
 }
 
+void arm7tdmi_deinit_target(struct target *target)
+{
+	arm7tdmi_free_reg_cache(target);
+}
+
 int arm7tdmi_init_arch_info(struct target *target,
 		struct arm7_9_common *arm7_9, struct jtag_tap *tap)
 {
@@ -648,6 +662,9 @@ int arm7tdmi_init_arch_info(struct target *target,
 	arm7_9->enable_single_step = arm7_9_enable_eice_step;
 	arm7_9->disable_single_step = arm7_9_disable_eice_step;
 
+	arm7_9->write_memory = arm7_9_write_memory;
+	arm7_9->bulk_write_memory = arm7_9_bulk_write_memory;
+
 	arm7_9->post_debug_entry = NULL;
 
 	arm7_9->pre_restore_context = NULL;
@@ -669,7 +686,7 @@ static int arm7tdmi_target_create(struct target *target, Jim_Interp *interp)
 
 	arm7_9 = calloc(1, sizeof(struct arm7_9_common));
 	arm7tdmi_init_arch_info(target, arm7_9, target->tap);
-	arm7_9->arm.is_armv4 = true;
+	arm7_9->arm.arch = ARM_ARCH_V4;
 
 	return ERROR_OK;
 }
@@ -691,11 +708,11 @@ struct target_type arm7tdmi_target = {
 	.deassert_reset = arm7_9_deassert_reset,
 	.soft_reset_halt = arm7_9_soft_reset_halt,
 
+	.get_gdb_arch = arm_get_gdb_arch,
 	.get_gdb_reg_list = arm_get_gdb_reg_list,
 
 	.read_memory = arm7_9_read_memory,
-	.write_memory = arm7_9_write_memory,
-	.bulk_write_memory = arm7_9_bulk_write_memory,
+	.write_memory = arm7_9_write_memory_opt,
 
 	.checksum_memory = arm_checksum_memory,
 	.blank_check_memory = arm_blank_check_memory,
@@ -710,6 +727,7 @@ struct target_type arm7tdmi_target = {
 	.commands  = arm7_9_command_handlers,
 	.target_create  = arm7tdmi_target_create,
 	.init_target = arm7tdmi_init_target,
+	.deinit_target = arm7tdmi_deinit_target,
 	.examine = arm7_9_examine,
 	.check_reset = arm7_9_check_reset,
 };