X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Farm920t.c;h=29f7917dcd8a9a753bbb2180778d69d11ae39716;hb=8f446fcf676e9cd13cf53d9946f0cae5d29a10ec;hp=0173550d8698a7d98512960797c5600a25943e61;hpb=d0dee7ccafcf87259fadf6c5de43df8583b0e885;p=openocd.git diff --git a/src/target/arm920t.c b/src/target/arm920t.c index 0173550d86..29f7917dcd 100644 --- a/src/target/arm920t.c +++ b/src/target/arm920t.c @@ -24,6 +24,7 @@ #include "arm920t.h" #include "time_support.h" #include "target_type.h" +#include "register.h" /* @@ -51,7 +52,7 @@ #define ARM920T_CP15_PHYS_ADDR(x, y, z) ((x << 5) | (y << 1) << (z)) -static int arm920t_read_cp15_physical(target_t *target, +static int arm920t_read_cp15_physical(struct target *target, int reg_addr, uint32_t *value) { struct arm920t_common *arm920t = target_to_arm920(target); @@ -61,7 +62,7 @@ static int arm920t_read_cp15_physical(target_t *target, uint8_t reg_addr_buf = reg_addr & 0x3f; uint8_t nr_w_buf = 0; - jtag_info = &arm920t->arm9tdmi_common.arm7_9_common.jtag_info; + jtag_info = &arm920t->arm7_9_common.jtag_info; jtag_set_end_state(TAP_IDLE); arm_jtag_scann(jtag_info, 0xf); @@ -103,7 +104,7 @@ static int arm920t_read_cp15_physical(target_t *target, return ERROR_OK; } -static int arm920t_write_cp15_physical(target_t *target, +static int arm920t_write_cp15_physical(struct target *target, int reg_addr, uint32_t value) { struct arm920t_common *arm920t = target_to_arm920(target); @@ -114,7 +115,7 @@ static int arm920t_write_cp15_physical(target_t *target, uint8_t nr_w_buf = 1; uint8_t value_buf[4]; - jtag_info = &arm920t->arm9tdmi_common.arm7_9_common.jtag_info; + jtag_info = &arm920t->arm7_9_common.jtag_info; buf_set_u32(value_buf, 0, 32, value); @@ -151,7 +152,7 @@ static int arm920t_write_cp15_physical(target_t *target, return ERROR_OK; } -static int arm920t_execute_cp15(target_t *target, uint32_t cp15_opcode, +static int arm920t_execute_cp15(struct target *target, uint32_t cp15_opcode, uint32_t arm_opcode) { int retval; @@ -163,7 +164,7 @@ static int arm920t_execute_cp15(target_t *target, uint32_t cp15_opcode, uint8_t nr_w_buf = 0; uint8_t cp15_opcode_buf[4]; - jtag_info = &arm920t->arm9tdmi_common.arm7_9_common.jtag_info; + jtag_info = &arm920t->arm7_9_common.jtag_info; jtag_set_end_state(TAP_IDLE); arm_jtag_scann(jtag_info, 0xf); @@ -208,7 +209,7 @@ static int arm920t_execute_cp15(target_t *target, uint32_t cp15_opcode, return ERROR_OK; } -static int arm920t_read_cp15_interpreted(target_t *target, +static int arm920t_read_cp15_interpreted(struct target *target, uint32_t cp15_opcode, uint32_t address, uint32_t *value) { struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target); @@ -243,7 +244,7 @@ static int arm920t_read_cp15_interpreted(target_t *target, LOG_DEBUG("cp15_opcode: %8.8x, address: %8.8x, value: %8.8x", cp15_opcode, address, *value); #endif - if (armv4_5_mode_to_number(armv4_5->core_mode)==-1) + if (!is_arm_mode(armv4_5->core_mode)) return ERROR_FAIL; ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = 1; @@ -253,7 +254,7 @@ static int arm920t_read_cp15_interpreted(target_t *target, } static -int arm920t_write_cp15_interpreted(target_t *target, +int arm920t_write_cp15_interpreted(struct target *target, uint32_t cp15_opcode, uint32_t value, uint32_t address) { uint32_t cp15c15 = 0x0; @@ -283,7 +284,7 @@ int arm920t_write_cp15_interpreted(target_t *target, LOG_DEBUG("cp15_opcode: %8.8x, value: %8.8x, address: %8.8x", cp15_opcode, value, address); #endif - if (armv4_5_mode_to_number(armv4_5->core_mode)==-1) + if (!is_arm_mode(armv4_5->core_mode)) return ERROR_FAIL; ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = 1; @@ -293,7 +294,7 @@ int arm920t_write_cp15_interpreted(target_t *target, } // EXPORTED to FA256 -uint32_t arm920t_get_ttb(target_t *target) +uint32_t arm920t_get_ttb(struct target *target) { int retval; uint32_t ttb = 0x0; @@ -305,7 +306,7 @@ uint32_t arm920t_get_ttb(target_t *target) } // EXPORTED to FA256 -void arm920t_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache) +void arm920t_disable_mmu_caches(struct target *target, int mmu, int d_u_cache, int i_cache) { uint32_t cp15_control; @@ -326,7 +327,7 @@ void arm920t_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_ } // EXPORTED to FA256 -void arm920t_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache) +void arm920t_enable_mmu_caches(struct target *target, int mmu, int d_u_cache, int i_cache) { uint32_t cp15_control; @@ -347,7 +348,7 @@ void arm920t_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_c } // EXPORTED to FA256 -void arm920t_post_debug_entry(target_t *target) +void arm920t_post_debug_entry(struct target *target) { uint32_t cp15c15; struct arm920t_common *arm920t = target_to_arm920(target); @@ -391,7 +392,7 @@ void arm920t_post_debug_entry(target_t *target) } // EXPORTED to FA256 -void arm920t_pre_restore_context(target_t *target) +void arm920t_pre_restore_context(struct target *target) { uint32_t cp15c15; struct arm920t_common *arm920t = target_to_arm920(target); @@ -415,7 +416,7 @@ void arm920t_pre_restore_context(target_t *target) static const char arm920_not[] = "target is not an ARM920"; -static int arm920t_verify_pointer(struct command_context_s *cmd_ctx, +static int arm920t_verify_pointer(struct command_context *cmd_ctx, struct arm920t_common *arm920t) { if (arm920t->common_magic != ARM920T_COMMON_MAGIC) { @@ -427,7 +428,7 @@ static int arm920t_verify_pointer(struct command_context_s *cmd_ctx, } /** Logs summary of ARM920 state for a halted target. */ -int arm920t_arch_state(struct target_s *target) +int arm920t_arch_state(struct target *target) { static const char *state[] = { @@ -443,14 +444,14 @@ int arm920t_arch_state(struct target_s *target) return ERROR_TARGET_INVALID; } - armv4_5 = &arm920t->arm9tdmi_common.arm7_9_common.armv4_5_common; + armv4_5 = &arm920t->arm7_9_common.armv4_5_common; LOG_USER("target halted in %s state due to %s, current mode: %s\n" "cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n" "MMU: %s, D-Cache: %s, I-Cache: %s", armv4_5_state_strings[armv4_5->core_state], Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name, - armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)], + arm_mode_name(armv4_5->core_mode), buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32), buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32), state[arm920t->armv4_5_mmu.mmu_enabled], @@ -460,7 +461,7 @@ int arm920t_arch_state(struct target_s *target) return ERROR_OK; } -static int arm920_mmu(struct target_s *target, int *enabled) +static int arm920_mmu(struct target *target, int *enabled) { if (target->state != TARGET_HALTED) { LOG_ERROR("%s: target not halted", __func__); @@ -471,7 +472,7 @@ static int arm920_mmu(struct target_s *target, int *enabled) return ERROR_OK; } -static int arm920_virt2phys(struct target_s *target, +static int arm920_virt2phys(struct target *target, uint32_t virt, uint32_t *phys) { /** @todo Implement this! */ @@ -480,7 +481,7 @@ static int arm920_virt2phys(struct target_s *target, } /** Reads a buffer, in the specified word size, with current MMU settings. */ -int arm920t_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) +int arm920t_read_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) { int retval; @@ -490,7 +491,7 @@ int arm920t_read_memory(struct target_s *target, uint32_t address, uint32_t size } -static int arm920t_read_phys_memory(struct target_s *target, +static int arm920t_read_phys_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) { @@ -500,7 +501,7 @@ static int arm920t_read_phys_memory(struct target_s *target, address, size, count, buffer); } -static int arm920t_write_phys_memory(struct target_s *target, +static int arm920t_write_phys_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) { @@ -512,7 +513,7 @@ static int arm920t_write_phys_memory(struct target_s *target, /** Writes a buffer, in the specified word size, with current MMU settings. */ -int arm920t_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) +int arm920t_write_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) { int retval; @@ -549,7 +550,7 @@ int arm920t_write_memory(struct target_s *target, uint32_t address, uint32_t siz } // EXPORTED to FA256 -int arm920t_soft_reset_halt(struct target_s *target) +int arm920t_soft_reset_halt(struct target *target) { int retval = ERROR_OK; struct arm920t_common *arm920t = target_to_arm920(target); @@ -620,14 +621,12 @@ int arm920t_soft_reset_halt(struct target_s *target) return ERROR_OK; } -int arm920t_init_arch_info(target_t *target, struct arm920t_common *arm920t, struct jtag_tap *tap) +int arm920t_init_arch_info(struct target *target, struct arm920t_common *arm920t, struct jtag_tap *tap) { - struct arm9tdmi_common *arm9tdmi = &arm920t->arm9tdmi_common; - struct arm7_9_common *arm7_9 = &arm9tdmi->arm7_9_common; + struct arm7_9_common *arm7_9 = &arm920t->arm7_9_common; - /* initialize arm9tdmi specific info (including arm7_9 and armv4_5) - */ - arm9tdmi_init_arch_info(target, arm9tdmi, tap); + /* initialize arm7/arm9 specific info (including armv4_5) */ + arm9tdmi_init_arch_info(target, arm7_9, tap); arm920t->common_magic = ARM920T_COMMON_MAGIC; @@ -655,7 +654,7 @@ int arm920t_init_arch_info(target_t *target, struct arm920t_common *arm920t, str return ERROR_OK; } -static int arm920t_target_create(struct target_s *target, Jim_Interp *interp) +static int arm920t_target_create(struct target *target, Jim_Interp *interp) { struct arm920t_common *arm920t = calloc(1,sizeof(struct arm920t_common)); @@ -665,7 +664,7 @@ static int arm920t_target_create(struct target_s *target, Jim_Interp *interp) COMMAND_HANDLER(arm920t_handle_read_cache_command) { int retval = ERROR_OK; - target_t *target = get_current_target(cmd_ctx); + struct target *target = get_current_target(CMD_CTX); struct arm920t_common *arm920t = target_to_arm920(target); struct arm7_9_common *arm7_9 = target_to_arm7_9(target); struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common; @@ -679,17 +678,17 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command) struct arm920t_cache_line d_cache[8][64], i_cache[8][64]; int segment, index; - retval = arm920t_verify_pointer(cmd_ctx, arm920t); + retval = arm920t_verify_pointer(CMD_CTX, arm920t); if (retval != ERROR_OK) return retval; - if (argc != 1) + if (CMD_ARGC != 1) { - command_print(cmd_ctx, "usage: arm920t read_cache "); + command_print(CMD_CTX, "usage: arm920t read_cache "); return ERROR_OK; } - if ((output = fopen(args[0], "w")) == NULL) + if ((output = fopen(CMD_ARGV[0], "w")) == NULL) { LOG_DEBUG("error opening cache content file"); return ERROR_OK; @@ -886,11 +885,11 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command) /* restore CP15 MMU and Cache settings */ arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl_saved); - command_print(cmd_ctx, "cache content successfully output to %s", args[0]); + command_print(CMD_CTX, "cache content successfully output to %s", CMD_ARGV[0]); fclose(output); - if (armv4_5_mode_to_number(armv4_5->core_mode)==-1) + if (!is_arm_mode(armv4_5->core_mode)) return ERROR_FAIL; /* mark registers dirty. */ @@ -911,7 +910,7 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command) COMMAND_HANDLER(arm920t_handle_read_mmu_command) { int retval = ERROR_OK; - target_t *target = get_current_target(cmd_ctx); + struct target *target = get_current_target(CMD_CTX); struct arm920t_common *arm920t = target_to_arm920(target); struct arm7_9_common *arm7_9 = target_to_arm7_9(target); struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common; @@ -925,17 +924,17 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command) struct arm920t_tlb_entry d_tlb[64], i_tlb[64]; int victim; - retval = arm920t_verify_pointer(cmd_ctx, arm920t); + retval = arm920t_verify_pointer(CMD_CTX, arm920t); if (retval != ERROR_OK) return retval; - if (argc != 1) + if (CMD_ARGC != 1) { - command_print(cmd_ctx, "usage: arm920t read_mmu "); + command_print(CMD_CTX, "usage: arm920t read_mmu "); return ERROR_OK; } - if ((output = fopen(args[0], "w")) == NULL) + if ((output = fopen(CMD_ARGV[0], "w")) == NULL) { LOG_DEBUG("error opening mmu content file"); return ERROR_OK; @@ -1169,11 +1168,11 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command) fprintf(output, "%i: 0x%8.8" PRIx32 " 0x%8.8" PRIx32 " 0x%8.8" PRIx32 " %s\n", i, i_tlb[i].cam, i_tlb[i].ram1, i_tlb[i].ram2, (i_tlb[i].cam & 0x20) ? "(valid)" : "(invalid)"); } - command_print(cmd_ctx, "mmu content successfully output to %s", args[0]); + command_print(CMD_CTX, "mmu content successfully output to %s", CMD_ARGV[0]); fclose(output); - if (armv4_5_mode_to_number(armv4_5->core_mode)==-1) + if (!is_arm_mode(armv4_5->core_mode)) return ERROR_FAIL; /* mark registers dirty */ @@ -1194,31 +1193,31 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command) COMMAND_HANDLER(arm920t_handle_cp15_command) { int retval; - target_t *target = get_current_target(cmd_ctx); + struct target *target = get_current_target(CMD_CTX); struct arm920t_common *arm920t = target_to_arm920(target); - retval = arm920t_verify_pointer(cmd_ctx, arm920t); + retval = arm920t_verify_pointer(CMD_CTX, arm920t); if (retval != ERROR_OK) return retval; if (target->state != TARGET_HALTED) { - command_print(cmd_ctx, "target must be stopped for \"%s\" command", CMD_NAME); + command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME); return ERROR_OK; } /* one or more argument, access a single register (write if second argument is given */ - if (argc >= 1) + if (CMD_ARGC >= 1) { int address; - COMMAND_PARSE_NUMBER(int, args[0], address); + COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], address); - if (argc == 1) + if (CMD_ARGC == 1) { uint32_t value; if ((retval = arm920t_read_cp15_physical(target, address, &value)) != ERROR_OK) { - command_print(cmd_ctx, "couldn't access reg %i", address); + command_print(CMD_CTX, "couldn't access reg %i", address); return ERROR_OK; } if ((retval = jtag_execute_queue()) != ERROR_OK) @@ -1226,18 +1225,18 @@ COMMAND_HANDLER(arm920t_handle_cp15_command) return retval; } - command_print(cmd_ctx, "%i: %8.8" PRIx32 "", address, value); + command_print(CMD_CTX, "%i: %8.8" PRIx32 "", address, value); } - else if (argc == 2) + else if (CMD_ARGC == 2) { uint32_t value; - COMMAND_PARSE_NUMBER(u32, args[1], value); + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value); if ((retval = arm920t_write_cp15_physical(target, address, value)) != ERROR_OK) { - command_print(cmd_ctx, "couldn't access reg %i", address); + command_print(CMD_CTX, "couldn't access reg %i", address); return ERROR_OK; } - command_print(cmd_ctx, "%i: %8.8" PRIx32 "", address, value); + command_print(CMD_CTX, "%i: %8.8" PRIx32 "", address, value); } } @@ -1247,65 +1246,65 @@ COMMAND_HANDLER(arm920t_handle_cp15_command) COMMAND_HANDLER(arm920t_handle_cp15i_command) { int retval; - target_t *target = get_current_target(cmd_ctx); + struct target *target = get_current_target(CMD_CTX); struct arm920t_common *arm920t = target_to_arm920(target); - retval = arm920t_verify_pointer(cmd_ctx, arm920t); + retval = arm920t_verify_pointer(CMD_CTX, arm920t); if (retval != ERROR_OK) return retval; if (target->state != TARGET_HALTED) { - command_print(cmd_ctx, "target must be stopped for \"%s\" command", CMD_NAME); + command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME); return ERROR_OK; } /* one or more argument, access a single register (write if second argument is given */ - if (argc >= 1) + if (CMD_ARGC >= 1) { uint32_t opcode; - COMMAND_PARSE_NUMBER(u32, args[0], opcode); + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], opcode); - if (argc == 1) + if (CMD_ARGC == 1) { uint32_t value; if ((retval = arm920t_read_cp15_interpreted(target, opcode, 0x0, &value)) != ERROR_OK) { - command_print(cmd_ctx, "couldn't execute %8.8" PRIx32 "", opcode); + command_print(CMD_CTX, "couldn't execute %8.8" PRIx32 "", opcode); return ERROR_OK; } - command_print(cmd_ctx, "%8.8" PRIx32 ": %8.8" PRIx32 "", opcode, value); + command_print(CMD_CTX, "%8.8" PRIx32 ": %8.8" PRIx32 "", opcode, value); } - else if (argc == 2) + else if (CMD_ARGC == 2) { uint32_t value; - COMMAND_PARSE_NUMBER(u32, args[1], value); + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value); if ((retval = arm920t_write_cp15_interpreted(target, opcode, value, 0)) != ERROR_OK) { - command_print(cmd_ctx, "couldn't execute %8.8" PRIx32 "", opcode); + command_print(CMD_CTX, "couldn't execute %8.8" PRIx32 "", opcode); return ERROR_OK; } - command_print(cmd_ctx, "%8.8" PRIx32 ": %8.8" PRIx32 "", opcode, value); + command_print(CMD_CTX, "%8.8" PRIx32 ": %8.8" PRIx32 "", opcode, value); } - else if (argc == 3) + else if (CMD_ARGC == 3) { uint32_t value; - COMMAND_PARSE_NUMBER(u32, args[1], value); + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value); uint32_t address; - COMMAND_PARSE_NUMBER(u32, args[2], address); + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], address); if ((retval = arm920t_write_cp15_interpreted(target, opcode, value, address)) != ERROR_OK) { - command_print(cmd_ctx, "couldn't execute %8.8" PRIx32 "", opcode); + command_print(CMD_CTX, "couldn't execute %8.8" PRIx32 "", opcode); return ERROR_OK; } - command_print(cmd_ctx, "%8.8" PRIx32 ": %8.8" PRIx32 " %8.8" PRIx32 "", opcode, value, address); + command_print(CMD_CTX, "%8.8" PRIx32 ": %8.8" PRIx32 " %8.8" PRIx32 "", opcode, value, address); } } else { - command_print(cmd_ctx, "usage: arm920t cp15i [value] [address]"); + command_print(CMD_CTX, "usage: arm920t cp15i [value] [address]"); } return ERROR_OK; @@ -1314,18 +1313,18 @@ COMMAND_HANDLER(arm920t_handle_cp15i_command) COMMAND_HANDLER(arm920t_handle_cache_info_command) { int retval; - target_t *target = get_current_target(cmd_ctx); + struct target *target = get_current_target(CMD_CTX); struct arm920t_common *arm920t = target_to_arm920(target); - retval = arm920t_verify_pointer(cmd_ctx, arm920t); + retval = arm920t_verify_pointer(CMD_CTX, arm920t); if (retval != ERROR_OK) return retval; - return armv4_5_handle_cache_info_command(cmd_ctx, &arm920t->armv4_5_mmu.armv4_5_cache); + return armv4_5_handle_cache_info_command(CMD_CTX, &arm920t->armv4_5_mmu.armv4_5_cache); } -static int arm920t_mrc(target_t *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value) +static int arm920t_mrc(struct target *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value) { if (cpnum!=15) { @@ -1336,7 +1335,7 @@ static int arm920t_mrc(target_t *target, int cpnum, uint32_t op1, uint32_t op2, return arm920t_read_cp15_interpreted(target, mrc_opcode(cpnum, op1, op2, CRn, CRm), 0, value); } -static int arm920t_mcr(target_t *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value) +static int arm920t_mcr(struct target *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value) { if (cpnum!=15) { @@ -1348,10 +1347,10 @@ static int arm920t_mcr(target_t *target, int cpnum, uint32_t op1, uint32_t op2, } /** Registers commands to access coprocessor, cache, and MMU resources. */ -int arm920t_register_commands(struct command_context_s *cmd_ctx) +int arm920t_register_commands(struct command_context *cmd_ctx) { int retval; - command_t *arm920t_cmd; + struct command *arm920t_cmd; retval = arm9tdmi_register_commands(cmd_ctx); @@ -1407,8 +1406,9 @@ struct target_type arm920t_target = .virt2phys = arm920_virt2phys, .bulk_write_memory = arm7_9_bulk_write_memory, - .checksum_memory = arm7_9_checksum_memory, - .blank_check_memory = arm7_9_blank_check_memory, + + .checksum_memory = arm_checksum_memory, + .blank_check_memory = arm_blank_check_memory, .run_algorithm = armv4_5_run_algorithm, @@ -1420,7 +1420,7 @@ struct target_type arm920t_target = .register_commands = arm920t_register_commands, .target_create = arm920t_target_create, .init_target = arm9tdmi_init_target, - .examine = arm9tdmi_examine, + .examine = arm7_9_examine, .mrc = arm920t_mrc, .mcr = arm920t_mcr, };