X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Farm920t.c;h=f057d7b9b485eb3e101cfb221a354127955d47ab;hb=4e079d18bffaed0372ab5b2f13cfd5d14db79d21;hp=a7816fd8c6a61ac817a12d678d2580b6037054ec;hpb=e018c7c1d29e8dabb9b4a90bb9eb3574eb1668bb;p=openocd.git diff --git a/src/target/arm920t.c b/src/target/arm920t.c index a7816fd8c6..f057d7b9b4 100644 --- a/src/target/arm920t.c +++ b/src/target/arm920t.c @@ -1,3 +1,4 @@ + /*************************************************************************** * Copyright (C) 2005 by Dominic Rath * * Dominic.Rath@gmx.de * @@ -88,12 +89,16 @@ static int arm920t_read_cp15_physical(struct target *target, uint8_t access_type_buf = 1; uint8_t reg_addr_buf = reg_addr & 0x3f; uint8_t nr_w_buf = 0; + int retval; jtag_info = &arm920t->arm7_9_common.jtag_info; - jtag_set_end_state(TAP_IDLE); - arm_jtag_scann(jtag_info, 0xf); - arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL); + retval = arm_jtag_scann(jtag_info, 0xf, TAP_IDLE); + if (retval != ERROR_OK) + return retval; + retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE); + if (retval != ERROR_OK) + return retval; fields[0].num_bits = 1; fields[0].out_value = &access_type_buf; @@ -111,11 +116,11 @@ static int arm920t_read_cp15_physical(struct target *target, fields[3].out_value = &nr_w_buf; fields[3].in_value = NULL; - jtag_add_dr_scan(jtag_info->tap, 4, fields, jtag_get_end_state()); + jtag_add_dr_scan(jtag_info->tap, 4, fields, TAP_IDLE); fields[1].in_value = (uint8_t *)value; - jtag_add_dr_scan(jtag_info->tap, 4, fields, jtag_get_end_state()); + jtag_add_dr_scan(jtag_info->tap, 4, fields, TAP_IDLE); jtag_add_callback(arm_le_to_h_u32, (jtag_callback_data_t)value); @@ -137,14 +142,18 @@ static int arm920t_write_cp15_physical(struct target *target, uint8_t reg_addr_buf = reg_addr & 0x3f; uint8_t nr_w_buf = 1; uint8_t value_buf[4]; + int retval; jtag_info = &arm920t->arm7_9_common.jtag_info; buf_set_u32(value_buf, 0, 32, value); - jtag_set_end_state(TAP_IDLE); - arm_jtag_scann(jtag_info, 0xf); - arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL); + retval = arm_jtag_scann(jtag_info, 0xf, TAP_IDLE); + if (retval != ERROR_OK) + return retval; + retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE); + if (retval != ERROR_OK) + return retval; fields[0].num_bits = 1; fields[0].out_value = &access_type_buf; @@ -162,7 +171,7 @@ static int arm920t_write_cp15_physical(struct target *target, fields[3].out_value = &nr_w_buf; fields[3].in_value = NULL; - jtag_add_dr_scan(jtag_info->tap, 4, fields, jtag_get_end_state()); + jtag_add_dr_scan(jtag_info->tap, 4, fields, TAP_IDLE); #ifdef _DEBUG_INSTRUCTION_EXECUTION_ LOG_DEBUG("addr: 0x%x value: %8.8x", reg_addr, value); @@ -192,9 +201,12 @@ static int arm920t_execute_cp15(struct target *target, uint32_t cp15_opcode, jtag_info = &arm920t->arm7_9_common.jtag_info; - jtag_set_end_state(TAP_IDLE); - arm_jtag_scann(jtag_info, 0xf); - arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL); + retval = arm_jtag_scann(jtag_info, 0xf, TAP_IDLE); + if (retval != ERROR_OK) + return retval; + retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE); + if (retval != ERROR_OK) + return retval; buf_set_u32(cp15_opcode_buf, 0, 32, cp15_opcode); @@ -214,7 +226,7 @@ static int arm920t_execute_cp15(struct target *target, uint32_t cp15_opcode, fields[3].out_value = &nr_w_buf; fields[3].in_value = NULL; - jtag_add_dr_scan(jtag_info->tap, 4, fields, jtag_get_end_state()); + jtag_add_dr_scan(jtag_info->tap, 4, fields, TAP_IDLE); arm9tdmi_clock_out(jtag_info, arm_opcode, 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1); @@ -269,7 +281,10 @@ static int arm920t_read_cp15_interpreted(struct target *target, #endif if (!is_arm_mode(armv4_5->core_mode)) + { + LOG_ERROR("not a valid arm core mode - communication failure?"); return ERROR_FAIL; + } r[0].dirty = 1; r[1].dirty = 1; @@ -311,7 +326,10 @@ int arm920t_write_cp15_interpreted(struct target *target, #endif if (!is_arm_mode(armv4_5->core_mode)) + { + LOG_ERROR("not a valid arm core mode - communication failure?"); return ERROR_FAIL; + } r[0].dirty = 1; r[1].dirty = 1; @@ -320,7 +338,7 @@ int arm920t_write_cp15_interpreted(struct target *target, } // EXPORTED to FA256 -uint32_t arm920t_get_ttb(struct target *target) +int arm920t_get_ttb(struct target *target, uint32_t *result) { int retval; uint32_t ttb = 0x0; @@ -330,18 +348,24 @@ uint32_t arm920t_get_ttb(struct target *target) 0xeebf0f51, 0x0, &ttb)) != ERROR_OK) return retval; - return ttb; + *result = ttb; + return ERROR_OK; } // EXPORTED to FA256 -void arm920t_disable_mmu_caches(struct target *target, int mmu, +int arm920t_disable_mmu_caches(struct target *target, int mmu, int d_u_cache, int i_cache) { uint32_t cp15_control; + int retval; /* read cp15 control register */ - arm920t_read_cp15_physical(target, CP15PHYS_CTRL, &cp15_control); - jtag_execute_queue(); + retval = arm920t_read_cp15_physical(target, CP15PHYS_CTRL, &cp15_control); + if (retval != ERROR_OK) + return retval; + retval = jtag_execute_queue(); + if (retval != ERROR_OK) + return retval; if (mmu) cp15_control &= ~0x1U; @@ -352,18 +376,24 @@ void arm920t_disable_mmu_caches(struct target *target, int mmu, if (i_cache) cp15_control &= ~0x1000U; - arm920t_write_cp15_physical(target, CP15PHYS_CTRL, cp15_control); + retval = arm920t_write_cp15_physical(target, CP15PHYS_CTRL, cp15_control); + return retval; } // EXPORTED to FA256 -void arm920t_enable_mmu_caches(struct target *target, int mmu, +int arm920t_enable_mmu_caches(struct target *target, int mmu, int d_u_cache, int i_cache) { uint32_t cp15_control; + int retval; /* read cp15 control register */ - arm920t_read_cp15_physical(target, CP15PHYS_CTRL, &cp15_control); - jtag_execute_queue(); + retval = arm920t_read_cp15_physical(target, CP15PHYS_CTRL, &cp15_control); + if (retval != ERROR_OK) + return retval; + retval = jtag_execute_queue(); + if (retval != ERROR_OK) + return retval; if (mmu) cp15_control |= 0x1U; @@ -374,28 +404,38 @@ void arm920t_enable_mmu_caches(struct target *target, int mmu, if (i_cache) cp15_control |= 0x1000U; - arm920t_write_cp15_physical(target, CP15PHYS_CTRL, cp15_control); + retval = arm920t_write_cp15_physical(target, CP15PHYS_CTRL, cp15_control); + return retval; } // EXPORTED to FA256 -void arm920t_post_debug_entry(struct target *target) +int arm920t_post_debug_entry(struct target *target) { uint32_t cp15c15; struct arm920t_common *arm920t = target_to_arm920(target); + int retval; /* examine cp15 control reg */ - arm920t_read_cp15_physical(target, + retval = arm920t_read_cp15_physical(target, CP15PHYS_CTRL, &arm920t->cp15_control_reg); - jtag_execute_queue(); + if (retval != ERROR_OK) + return retval; + retval = jtag_execute_queue(); + if (retval != ERROR_OK) + return retval; LOG_DEBUG("cp15_control_reg: %8.8" PRIx32, arm920t->cp15_control_reg); if (arm920t->armv4_5_mmu.armv4_5_cache.ctype == -1) { uint32_t cache_type_reg; /* identify caches */ - arm920t_read_cp15_physical(target, + retval = arm920t_read_cp15_physical(target, CP15PHYS_CACHETYPE, &cache_type_reg); - jtag_execute_queue(); + if (retval != ERROR_OK) + return retval; + retval = jtag_execute_queue(); + if (retval != ERROR_OK) + return retval; armv4_5_identify_cache(cache_type_reg, &arm920t->armv4_5_mmu.armv4_5_cache); } @@ -409,10 +449,18 @@ void arm920t_post_debug_entry(struct target *target) /* save i/d fault status and address register */ /* FIXME use opcode macros */ - arm920t_read_cp15_interpreted(target, 0xee150f10, 0x0, &arm920t->d_fsr); - arm920t_read_cp15_interpreted(target, 0xee150f30, 0x0, &arm920t->i_fsr); - arm920t_read_cp15_interpreted(target, 0xee160f10, 0x0, &arm920t->d_far); - arm920t_read_cp15_interpreted(target, 0xee160f30, 0x0, &arm920t->i_far); + retval = arm920t_read_cp15_interpreted(target, 0xee150f10, 0x0, &arm920t->d_fsr); + if (retval != ERROR_OK) + return retval; + retval = arm920t_read_cp15_interpreted(target, 0xee150f30, 0x0, &arm920t->i_fsr); + if (retval != ERROR_OK) + return retval; + retval = arm920t_read_cp15_interpreted(target, 0xee160f10, 0x0, &arm920t->d_far); + if (retval != ERROR_OK) + return retval; + retval = arm920t_read_cp15_interpreted(target, 0xee160f30, 0x0, &arm920t->i_far); + if (retval != ERROR_OK) + return retval; LOG_DEBUG("D FSR: 0x%8.8" PRIx32 ", D FAR: 0x%8.8" PRIx32 ", I FSR: 0x%8.8" PRIx32 ", I FAR: 0x%8.8" PRIx32, @@ -422,13 +470,20 @@ void arm920t_post_debug_entry(struct target *target) { /* read-modify-write CP15 test state register * to disable I/D-cache linefills */ - arm920t_read_cp15_physical(target, + retval = arm920t_read_cp15_physical(target, CP15PHYS_TESTSTATE, &cp15c15); - jtag_execute_queue(); + if (retval != ERROR_OK) + return retval; + retval = jtag_execute_queue(); + if (retval != ERROR_OK) + return retval; cp15c15 |= 0x600; - arm920t_write_cp15_physical(target, + retval = arm920t_write_cp15_physical(target, CP15PHYS_TESTSTATE, cp15c15); + if (retval != ERROR_OK) + return retval; } + return ERROR_OK; } // EXPORTED to FA256 @@ -478,7 +533,6 @@ int arm920t_arch_state(struct target *target) }; struct arm920t_common *arm920t = target_to_arm920(target); - struct arm *armv4_5; if (arm920t->common_magic != ARM920T_COMMON_MAGIC) { @@ -486,8 +540,6 @@ int arm920t_arch_state(struct target *target) return ERROR_TARGET_INVALID; } - armv4_5 = &arm920t->arm7_9_common.armv4_5_common; - arm_arch_state(target); LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s", state[arm920t->armv4_5_mmu.mmu_enabled], @@ -511,18 +563,14 @@ static int arm920_mmu(struct target *target, int *enabled) static int arm920_virt2phys(struct target *target, uint32_t virt, uint32_t *phys) { - int type; uint32_t cb; - int domain; - uint32_t ap; struct arm920t_common *arm920t = target_to_arm920(target); - uint32_t ret = armv4_5_mmu_translate_va(target, - &arm920t->armv4_5_mmu, virt, &type, &cb, &domain, &ap); - if (type == -1) - { - return ret; - } + uint32_t ret; + int retval = armv4_5_mmu_translate_va(target, + &arm920t->armv4_5_mmu, virt, &cb, &ret); + if (retval != ERROR_OK) + return retval; *phys = ret; return ERROR_OK; } @@ -551,7 +599,7 @@ static int arm920t_read_phys_memory(struct target *target, static int arm920t_write_phys_memory(struct target *target, uint32_t address, uint32_t size, - uint32_t count, uint8_t *buffer) + uint32_t count, const uint8_t *buffer) { struct arm920t_common *arm920t = target_to_arm920(target); @@ -562,7 +610,7 @@ static int arm920t_write_phys_memory(struct target *target, /** Writes a buffer, in the specified word size, with current MMU settings. */ int arm920t_write_memory(struct target *target, uint32_t address, - uint32_t size, uint32_t count, uint8_t *buffer) + uint32_t size, uint32_t count, const uint8_t *buffer) { int retval; const uint32_t cache_mask = ~0x1f; /* cache line size : 32 byte */ @@ -570,7 +618,11 @@ int arm920t_write_memory(struct target *target, uint32_t address, /* FIX!!!! this should be cleaned up and made much more general. The * plan is to write up and test on arm920t specifically and - * then generalize and clean up afterwards. */ + * then generalize and clean up afterwards. + * + * Also it should be moved to the callbacks that handle breakpoints + * specifically and not the generic memory write fn's. See XScale code. + */ if (arm920t->armv4_5_mmu.mmu_enabled && (count == 1) && ((size==2) || (size==4))) { @@ -579,19 +631,16 @@ int arm920t_write_memory(struct target *target, uint32_t address, * in memory marked read only * by MMU */ - int type; uint32_t cb; - int domain; - uint32_t ap; uint32_t pa; /* * We need physical address and cb */ - pa = armv4_5_mmu_translate_va(target, &arm920t->armv4_5_mmu, - address, &type, &cb, &domain, &ap); - if (type == -1) - return pa; + retval = armv4_5_mmu_translate_va(target, &arm920t->armv4_5_mmu, + address, &cb, &pa); + if (retval != ERROR_OK) + return retval; if (arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled) { @@ -705,7 +754,7 @@ int arm920t_write_memory(struct target *target, uint32_t address, } } - return retval; + return ERROR_OK; } // EXPORTED to FA256 @@ -787,7 +836,7 @@ static int arm920t_mcr(struct target *target, int cpnum, uint32_t CRn, uint32_t CRm, uint32_t value); -int arm920t_init_arch_info(struct target *target, +static int arm920t_init_arch_info(struct target *target, struct arm920t_common *arm920t, struct jtag_tap *tap) { struct arm7_9_common *arm7_9 = &arm920t->arm7_9_common; @@ -846,8 +895,7 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command) uint32_t C15_C_D_Ind, C15_C_I_Ind; int i; FILE *output; - struct arm920t_cache_line d_cache[8][64], i_cache[8][64]; - int segment, index; + int segment, index_t; struct reg *r; retval = arm920t_verify_pointer(CMD_CTX, arm920t); @@ -916,12 +964,12 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command) arm920t_write_cp15_physical(target, CP15PHYS_TESTSTATE, cp15c15); - for (index = 0; index < 64; index++) + for (index_t = 0; index_t < 64; index_t++) { /* Ra: * r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */ - regs[0] = 0x0 | (segment << 5) | (index << 26); + regs[0] = 0x0 | (segment << 5) | (index_t << 26); arm9tdmi_write_core_regs(target, 0x1, regs); /* set interpret mode */ @@ -955,18 +1003,15 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command) return retval; } - d_cache[segment][index].cam = regs[9]; - /* mask LFSR[6] */ regs[9] &= 0xfffffffe; fprintf(output, "\nsegment: %i, index: %i, CAM: 0x%8.8" PRIx32 ", content (%s):\n", - segment, index, regs[9], + segment, index_t, regs[9], (regs[9] & 0x10) ? "valid" : "invalid"); for (i = 1; i < 9; i++) { - d_cache[segment][index].data[i] = regs[i]; fprintf(output, "%i: 0x%8.8" PRIx32 "\n", i-1, regs[i]); } @@ -1024,12 +1069,12 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command) arm920t_write_cp15_physical(target, CP15PHYS_TESTSTATE, cp15c15); - for (index = 0; index < 64; index++) + for (index_t = 0; index_t < 64; index_t++) { /* Ra: * r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */ - regs[0] = 0x0 | (segment << 5) | (index << 26); + regs[0] = 0x0 | (segment << 5) | (index_t << 26); arm9tdmi_write_core_regs(target, 0x1, regs); /* set interpret mode */ @@ -1063,18 +1108,15 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command) return retval; } - i_cache[segment][index].cam = regs[9]; - /* mask LFSR[6] */ regs[9] &= 0xfffffffe; fprintf(output, "\nsegment: %i, index: %i, " "CAM: 0x%8.8" PRIx32 ", content (%s):\n", - segment, index, regs[9], + segment, index_t, regs[9], (regs[9] & 0x10) ? "valid" : "invalid"); for (i = 1; i < 9; i++) { - i_cache[segment][index].data[i] = regs[i]; fprintf(output, "%i: 0x%8.8" PRIx32 "\n", i-1, regs[i]); } @@ -1108,7 +1150,10 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command) fclose(output); if (!is_arm_mode(armv4_5->core_mode)) + { + LOG_ERROR("not a valid arm core mode - communication failure?"); return ERROR_FAIL; + } /* force writeback of the valid data */ r = armv4_5->core_cache->reg_list; @@ -1435,7 +1480,10 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command) fclose(output); if (!is_arm_mode(armv4_5->core_mode)) + { + LOG_ERROR("not a valid arm core mode - communication failure?"); return ERROR_FAIL; + } /* force writeback of the valid data */ r = armv4_5->core_cache->reg_list;