X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Farm926ejs.c;h=3c80802145890525f6e7aeea9e09d3fe2d2bf6e4;hb=7280a52e6964d7e5c700670a7ff25cfd8a9d6316;hp=d9c677ffa88e7bb6c06d98bbcb12771e5152454b;hpb=d3315c4183c34cf48590e9c92ef2b96180271a0a;p=openocd.git

diff --git a/src/target/arm926ejs.c b/src/target/arm926ejs.c
index d9c677ffa8..3c80802145 100644
--- a/src/target/arm926ejs.c
+++ b/src/target/arm926ejs.c
@@ -159,8 +159,9 @@ int arm926ejs_cp15_read(target_t *target, uint32_t op1, uint32_t op2, uint32_t C
 
 	jtag_add_dr_scan(4, fields, jtag_get_end_state());
 
-	/*TODO: add timeout*/
-	do
+	long long then = timeval_ms();
+
+	for (;;)
 	{
 		/* rescan with NOP, to wait for the access to complete */
 		access = 0;
@@ -173,7 +174,19 @@ int arm926ejs_cp15_read(target_t *target, uint32_t op1, uint32_t op2, uint32_t C
 		{
 			return retval;
 		}
-	} while (buf_get_u32(&access, 0, 1) != 1);
+
+		if (buf_get_u32(&access, 0, 1) == 1)
+		{
+			break;
+		}
+
+		/* 10ms timeout */
+		if ((timeval_ms()-then)>10)
+		{
+			LOG_ERROR("cp15 read operation timed out");
+			return ERROR_FAIL;
+		}
+	}
 
 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 	LOG_DEBUG("addr: 0x%x value: %8.8x", address, *value);
@@ -228,8 +241,10 @@ int arm926ejs_cp15_write(target_t *target, uint32_t op1, uint32_t op2, uint32_t
 	fields[3].in_value = NULL;
 
 	jtag_add_dr_scan(4, fields, jtag_get_end_state());
-	/*TODO: add timeout*/
-	do
+
+	long long then = timeval_ms();
+
+	for (;;)
 	{
 		/* rescan with NOP, to wait for the access to complete */
 		access = 0;
@@ -239,7 +254,19 @@ int arm926ejs_cp15_write(target_t *target, uint32_t op1, uint32_t op2, uint32_t
 		{
 			return retval;
 		}
-	} while (buf_get_u32(&access, 0, 1) != 1);
+
+		if (buf_get_u32(&access, 0, 1) == 1)
+		{
+			break;
+		}
+
+		/* 10ms timeout */
+		if ((timeval_ms()-then)>10)
+		{
+			LOG_ERROR("cp15 write operation timed out");
+			return ERROR_FAIL;
+		}
+	}
 
 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 	LOG_DEBUG("addr: 0x%x value: %8.8x", address, value);
@@ -250,7 +277,7 @@ int arm926ejs_cp15_write(target_t *target, uint32_t op1, uint32_t op2, uint32_t
 	return ERROR_OK;
 }
 
-int arm926ejs_examine_debug_reason(target_t *target)
+static int arm926ejs_examine_debug_reason(target_t *target)
 {
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
@@ -267,7 +294,11 @@ int arm926ejs_examine_debug_reason(target_t *target)
 
 	switch (debug_reason)
 	{
-		/* case 0:  no debug entry */
+		case 0:
+			LOG_DEBUG("no *NEW* debug entry (?missed one?)");
+			/* ... since last restart or debug reset ... */
+			target->debug_reason = DBG_REASON_DBGRQ;
+			break;
 		case 1:
 			LOG_DEBUG("breakpoint from EICE unit 0");
 			target->debug_reason = DBG_REASON_BREAKPOINT;
@@ -333,20 +364,21 @@ int arm926ejs_examine_debug_reason(target_t *target)
 			 * openocd development mailing list if you have hardware
 			 * to donate to look into this problem....
 			 */
-			LOG_ERROR("mystery debug reason MOE = 0xc. Try issuing a resume + halt.");
+			LOG_WARNING("WARNING: mystery debug reason MOE = 0xc. Try issuing a resume + halt.");
 			target->debug_reason = DBG_REASON_DBGRQ;
-			retval = ERROR_TARGET_FAILURE;
 			break;
 		default:
-			LOG_ERROR("BUG: unknown debug reason: 0x%x", debug_reason);
+			LOG_WARNING("WARNING: unknown debug reason: 0x%x", debug_reason);
+			/* Oh agony! should we interpret this as a halt request or
+			 * that the target stopped on it's own accord?
+			 */
 			target->debug_reason = DBG_REASON_DBGRQ;
 			/* if we fail here, we won't talk to the target and it will
 			 * be reported to be in the halted state */
-			retval = ERROR_TARGET_FAILURE;
 			break;
 	}
 
-	return retval;
+	return ERROR_OK;
 }
 
 uint32_t arm926ejs_get_ttb(target_t *target)