X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Farm_adi_v5.c;h=60bd5466694f0e1a045a6eba77eba3594faee863;hb=d01b3d69ec17da19576c85bb36245399211eb620;hp=4176dcaddebcd7319c5f7ca307509b23a7da70dc;hpb=209cb38aa155825175e2806d6093cecb5d77edc1;p=openocd.git diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c index 4176dcadde..60bd546669 100644 --- a/src/target/arm_adi_v5.c +++ b/src/target/arm_adi_v5.c @@ -1094,11 +1094,14 @@ int dap_lookup_cs_component(struct adiv5_ap *ap, return ERROR_OK; } -/** Holds registers of a CoreSight component */ +/** Holds registers and coordinates of a CoreSight component */ struct cs_component_vals { + struct adiv5_ap *ap; + target_addr_t component_base; uint64_t pid; uint32_t cid; uint32_t devarch; + uint32_t devid; uint32_t devtype_memtype; }; @@ -1121,16 +1124,22 @@ static int rtp_read_cs_regs(struct adiv5_ap *ap, target_addr_t component_base, uint32_t pid0, pid1, pid2, pid3, pid4; int retval = ERROR_OK; + v->ap = ap; + v->component_base = component_base; + /* sort by offset to gain speed */ /* - * Registers DEVARCH and DEVTYPE are valid on Class 0x9 devices + * Registers DEVARCH, DEVID and DEVTYPE are valid on Class 0x9 devices * only, but are at offset above 0xf00, so can be read on any device * without triggering error. Read them for eventual use on Class 0x9. */ if (retval == ERROR_OK) retval = mem_ap_read_u32(ap, component_base + ARM_CS_C9_DEVARCH, &v->devarch); + if (retval == ERROR_OK) + retval = mem_ap_read_u32(ap, component_base + ARM_CS_C9_DEVID, &v->devid); + /* Same address as ARM_CS_C1_MEMTYPE */ if (retval == ERROR_OK) retval = mem_ap_read_u32(ap, component_base + ARM_CS_C9_DEVTYPE, &v->devtype_memtype); @@ -1473,6 +1482,19 @@ static int dap_devtype_display(struct command_invocation *cmd, uint32_t devtype) return ERROR_OK; } +/* Broken ROM tables can have circular references. Stop after a while */ +#define ROM_TABLE_MAX_DEPTH (16) + +/* TODO: these prototypes will be removed in a following patch */ +static int dap_info_mem_ap_header(struct command_invocation *cmd, + int retval, struct adiv5_ap *ap, + target_addr_t dbgbase, uint32_t apid); +static int dap_info_cs_component(struct command_invocation *cmd, + int retval, struct cs_component_vals *v, int depth); +static int dap_info_rom_table_entry(struct command_invocation *cmd, + int retval, int depth, + unsigned int offset, uint32_t romentry); + static int rtp_cs_component(struct command_invocation *cmd, struct adiv5_ap *ap, target_addr_t dbgbase, int depth); @@ -1482,11 +1504,6 @@ static int rtp_rom_loop(struct command_invocation *cmd, { assert(IS_ALIGNED(base_address, ARM_CS_ALIGN)); - char tabs[16] = ""; - - if (depth) - snprintf(tabs, sizeof(tabs), "[L%02d] ", depth); - unsigned int offset = 0; while (max_entries--) { uint32_t romentry; @@ -1494,32 +1511,29 @@ static int rtp_rom_loop(struct command_invocation *cmd, int retval = mem_ap_read_atomic_u32(ap, base_address + offset, &romentry); offset += 4; - if (retval != ERROR_OK) { + if (retval != ERROR_OK) LOG_DEBUG("Failed read ROM table entry"); - command_print(cmd, "\t%sROMTABLE[0x%x] Read error", tabs, saved_offset); - command_print(cmd, "\t\tUnable to continue"); - command_print(cmd, "\t%s\tStop parsing of ROM table", tabs); - return retval; - } - command_print(cmd, "\t%sROMTABLE[0x%x] = 0x%08" PRIx32, - tabs, saved_offset, romentry); + retval = dap_info_rom_table_entry(cmd, retval, depth, saved_offset, romentry); + if (retval != ERROR_OK) + return retval; if (romentry == 0) { - command_print(cmd, "\t%s\tEnd of ROM table", tabs); + /* End of ROM table */ break; } - if (!(romentry & ARM_CS_ROMENTRY_PRESENT)) { - command_print(cmd, "\t\tComponent not present"); + if (!(romentry & ARM_CS_ROMENTRY_PRESENT)) continue; - } /* Recurse. "romentry" is signed */ target_addr_t component_base = base_address + (int32_t)(romentry & ARM_CS_ROMENTRY_OFFSET_MASK); retval = rtp_cs_component(cmd, ap, component_base, depth + 1); - if (retval != ERROR_OK) - return retval; + if (retval != ERROR_OK) { + /* TODO: do we need to send an ABORT before continuing? */ + LOG_DEBUG("Ignore error parsing CoreSight component"); + continue; + } } return ERROR_OK; @@ -1530,81 +1544,30 @@ static int rtp_cs_component(struct command_invocation *cmd, { struct cs_component_vals v; int retval; - char tabs[16] = ""; assert(IS_ALIGNED(base_address, ARM_CS_ALIGN)); - if (depth > 16) { - command_print(cmd, "\tTables too deep"); - return ERROR_FAIL; - } - - if (depth) - snprintf(tabs, sizeof(tabs), "[L%02d] ", depth); - - command_print(cmd, "\t\tComponent base address " TARGET_ADDR_FMT, base_address); + if (depth > ROM_TABLE_MAX_DEPTH) + retval = ERROR_FAIL; + else + retval = rtp_read_cs_regs(ap, base_address, &v); - retval = rtp_read_cs_regs(ap, base_address, &v); - if (retval != ERROR_OK) { - command_print(cmd, "\t\tCan't read component, the corresponding core might be turned off"); + retval = dap_info_cs_component(cmd, retval, &v, depth); + if (retval != ERROR_OK) return ERROR_OK; /* Don't abort recursion */ - } - if (!is_valid_arm_cs_cidr(v.cid)) { - command_print(cmd, "\t\tInvalid CID 0x%08" PRIx32, v.cid); + if (!is_valid_arm_cs_cidr(v.cid)) return ERROR_OK; /* Don't abort recursion */ - } - - /* component may take multiple 4K pages */ - uint32_t size = ARM_CS_PIDR_SIZE(v.pid); - if (size > 0) - command_print(cmd, "\t\tStart address " TARGET_ADDR_FMT, base_address - 0x1000 * size); - - command_print(cmd, "\t\tPeripheral ID 0x%010" PRIx64, v.pid); const unsigned int class = ARM_CS_CIDR_CLASS(v.cid); - const unsigned int part_num = ARM_CS_PIDR_PART(v.pid); - unsigned int designer_id = ARM_CS_PIDR_DESIGNER(v.pid); - - if (v.pid & ARM_CS_PIDR_JEDEC) { - /* JEP106 code */ - command_print(cmd, "\t\tDesigner is 0x%03x, %s", - designer_id, jep106_manufacturer(designer_id)); - } else { - /* Legacy ASCII ID, clear invalid bits */ - designer_id &= 0x7f; - command_print(cmd, "\t\tDesigner ASCII code 0x%02x, %s", - designer_id, designer_id == 0x41 ? "ARM" : ""); - } - - const struct dap_part_nums *partnum = pidr_to_part_num(designer_id, part_num); - command_print(cmd, "\t\tPart is 0x%03x, %s %s", part_num, partnum->type, partnum->full); - command_print(cmd, "\t\tComponent class is 0x%x, %s", class, class_description[class]); - - if (class == ARM_CS_CLASS_0X1_ROM_TABLE) { - if (v.devtype_memtype & ARM_CS_C1_MEMTYPE_SYSMEM_MASK) - command_print(cmd, "\t\tMEMTYPE system memory present on bus"); - else - command_print(cmd, "\t\tMEMTYPE system memory not present: dedicated debug bus"); + if (class == ARM_CS_CLASS_0X1_ROM_TABLE) return rtp_rom_loop(cmd, ap, base_address, depth, 960); - } if (class == ARM_CS_CLASS_0X9_CS_COMPONENT) { - retval = dap_devtype_display(cmd, v.devtype_memtype); - if (retval != ERROR_OK) - return retval; - - /* REVISIT also show ARM_CS_C9_DEVID */ - if ((v.devarch & ARM_CS_C9_DEVARCH_PRESENT) == 0) return ERROR_OK; - unsigned int architect_id = (v.devarch & ARM_CS_C9_DEVARCH_ARCHITECT_MASK) >> ARM_CS_C9_DEVARCH_ARCHITECT_SHIFT; - unsigned int revision = (v.devarch & ARM_CS_C9_DEVARCH_REVISION_MASK) >> ARM_CS_C9_DEVARCH_REVISION_SHIFT; - command_print(cmd, "\t\tDev Arch is 0x%08" PRIx32 ", %s \"%s\" rev.%u", v.devarch, - jep106_manufacturer(architect_id), class0x9_devarch_description(v.devarch), - revision); /* quit if not ROM table */ if ((v.devarch & DEVARCH_ID_MASK) != DEVARCH_ROM_C_0X9) return ERROR_OK; @@ -1622,13 +1585,48 @@ int dap_info_command(struct command_invocation *cmd, int retval; uint32_t apid; target_addr_t dbgbase; - target_addr_t dbgaddr; + target_addr_t invalid_entry; /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */ retval = dap_get_debugbase(ap, &dbgbase, &apid); + retval = dap_info_mem_ap_header(cmd, retval, ap, dbgbase, apid); if (retval != ERROR_OK) return retval; + if (apid == 0) + return ERROR_FAIL; + + /* NOTE: a MEM-AP may have a single CoreSight component that's + * not a ROM table ... or have no such components at all. + */ + const unsigned int class = (apid & AP_REG_IDR_CLASS_MASK) >> AP_REG_IDR_CLASS_SHIFT; + + if (class == AP_REG_IDR_CLASS_MEM_AP) { + if (is_64bit_ap(ap)) + invalid_entry = 0xFFFFFFFFFFFFFFFFull; + else + invalid_entry = 0xFFFFFFFFul; + + if (dbgbase != invalid_entry && (dbgbase & 0x3) != 0x2) + rtp_cs_component(cmd, ap, dbgbase & 0xFFFFFFFFFFFFF000ull, 0); + } + + return ERROR_OK; +} + +/* Actions for command "dap info" */ + +static int dap_info_mem_ap_header(struct command_invocation *cmd, + int retval, struct adiv5_ap *ap, + target_addr_t dbgbase, uint32_t apid) +{ + target_addr_t invalid_entry; + + if (retval != ERROR_OK) { + command_print(cmd, "\t\tCan't read MEM-AP, the corresponding core might be turned off"); + return retval; + } + command_print(cmd, "AP ID register 0x%8.8" PRIx32, apid); if (apid == 0) { command_print(cmd, "No AP found at this ap 0x%x", ap->ap_num); @@ -1644,22 +1642,136 @@ int dap_info_command(struct command_invocation *cmd, if (class == AP_REG_IDR_CLASS_MEM_AP) { if (is_64bit_ap(ap)) - dbgaddr = 0xFFFFFFFFFFFFFFFFull; + invalid_entry = 0xFFFFFFFFFFFFFFFFull; else - dbgaddr = 0xFFFFFFFFul; + invalid_entry = 0xFFFFFFFFul; command_print(cmd, "MEM-AP BASE " TARGET_ADDR_FMT, dbgbase); - if (dbgbase == dbgaddr || (dbgbase & 0x3) == 0x2) { + if (dbgbase == invalid_entry || (dbgbase & 0x3) == 0x2) { command_print(cmd, "\tNo ROM table present"); } else { if (dbgbase & 0x01) command_print(cmd, "\tValid ROM table present"); else command_print(cmd, "\tROM table in legacy format"); + } + } - rtp_cs_component(cmd, ap, dbgbase & 0xFFFFFFFFFFFFF000ull, 0); + return ERROR_OK; +} + +static int dap_info_cs_component(struct command_invocation *cmd, + int retval, struct cs_component_vals *v, int depth) +{ + if (depth > ROM_TABLE_MAX_DEPTH) { + command_print(cmd, "\tTables too deep"); + return ERROR_FAIL; + } + + command_print(cmd, "\t\tComponent base address " TARGET_ADDR_FMT, v->component_base); + + if (retval != ERROR_OK) { + command_print(cmd, "\t\tCan't read component, the corresponding core might be turned off"); + return retval; + } + + if (!is_valid_arm_cs_cidr(v->cid)) { + command_print(cmd, "\t\tInvalid CID 0x%08" PRIx32, v->cid); + return ERROR_OK; /* Don't abort recursion */ + } + + /* component may take multiple 4K pages */ + uint32_t size = ARM_CS_PIDR_SIZE(v->pid); + if (size > 0) + command_print(cmd, "\t\tStart address " TARGET_ADDR_FMT, v->component_base - 0x1000 * size); + + command_print(cmd, "\t\tPeripheral ID 0x%010" PRIx64, v->pid); + + const unsigned int part_num = ARM_CS_PIDR_PART(v->pid); + unsigned int designer_id = ARM_CS_PIDR_DESIGNER(v->pid); + + if (v->pid & ARM_CS_PIDR_JEDEC) { + /* JEP106 code */ + command_print(cmd, "\t\tDesigner is 0x%03x, %s", + designer_id, jep106_manufacturer(designer_id)); + } else { + /* Legacy ASCII ID, clear invalid bits */ + designer_id &= 0x7f; + command_print(cmd, "\t\tDesigner ASCII code 0x%02x, %s", + designer_id, designer_id == 0x41 ? "ARM" : ""); + } + + const struct dap_part_nums *partnum = pidr_to_part_num(designer_id, part_num); + command_print(cmd, "\t\tPart is 0x%03x, %s %s", part_num, partnum->type, partnum->full); + + const unsigned int class = ARM_CS_CIDR_CLASS(v->cid); + command_print(cmd, "\t\tComponent class is 0x%x, %s", class, class_description[class]); + + if (class == ARM_CS_CLASS_0X1_ROM_TABLE) { + if (v->devtype_memtype & ARM_CS_C1_MEMTYPE_SYSMEM_MASK) + command_print(cmd, "\t\tMEMTYPE system memory present on bus"); + else + command_print(cmd, "\t\tMEMTYPE system memory not present: dedicated debug bus"); + return ERROR_OK; + } + + if (class == ARM_CS_CLASS_0X9_CS_COMPONENT) { + dap_devtype_display(cmd, v->devtype_memtype); + + /* REVISIT also show ARM_CS_C9_DEVID */ + + if ((v->devarch & ARM_CS_C9_DEVARCH_PRESENT) == 0) + return ERROR_OK; + + unsigned int architect_id = ARM_CS_C9_DEVARCH_ARCHITECT(v->devarch); + unsigned int revision = ARM_CS_C9_DEVARCH_REVISION(v->devarch); + command_print(cmd, "\t\tDev Arch is 0x%08" PRIx32 ", %s \"%s\" rev.%u", v->devarch, + jep106_manufacturer(architect_id), class0x9_devarch_description(v->devarch), + revision); + + if ((v->devarch & DEVARCH_ID_MASK) == DEVARCH_ROM_C_0X9) { + command_print(cmd, "\t\tType is ROM table"); + + if (v->devid & ARM_CS_C9_DEVID_SYSMEM_MASK) + command_print(cmd, "\t\tMEMTYPE system memory present on bus"); + else + command_print(cmd, "\t\tMEMTYPE system memory not present: dedicated debug bus"); } + return ERROR_OK; + } + + /* Class other than 0x1 and 0x9 */ + return ERROR_OK; +} + +static int dap_info_rom_table_entry(struct command_invocation *cmd, + int retval, int depth, + unsigned int offset, uint32_t romentry) +{ + char tabs[16] = ""; + + if (depth) + snprintf(tabs, sizeof(tabs), "[L%02d] ", depth); + + if (retval != ERROR_OK) { + command_print(cmd, "\t%sROMTABLE[0x%x] Read error", tabs, offset); + command_print(cmd, "\t\tUnable to continue"); + command_print(cmd, "\t%s\tStop parsing of ROM table", tabs); + return retval; + } + + command_print(cmd, "\t%sROMTABLE[0x%x] = 0x%08" PRIx32, + tabs, offset, romentry); + + if (romentry == 0) { + command_print(cmd, "\t%s\tEnd of ROM table", tabs); + return ERROR_OK; + } + + if (!(romentry & ARM_CS_ROMENTRY_PRESENT)) { + command_print(cmd, "\t\tComponent not present"); + return ERROR_OK; } return ERROR_OK;