X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Farm_adi_v5.h;h=746f1cb6541b25d6b89bae9912dc810e2ba08ab7;hb=249263d29da11b0ec981c2e0d520cd7dcf08939b;hp=2a0968440da8e5a94d12e211b41999b8046de398;hpb=e60c164cdb50a0aa268165e57de0a4cd0d58fcdf;p=openocd.git diff --git a/src/target/arm_adi_v5.h b/src/target/arm_adi_v5.h index 2a0968440d..746f1cb654 100644 --- a/src/target/arm_adi_v5.h +++ b/src/target/arm_adi_v5.h @@ -32,25 +32,52 @@ #include "arm_jtag.h" -#define DAP_IR_DPACC 0xA -#define DAP_IR_APACC 0xB +/* JTAG instructions/registers for JTAG-DP and SWJ-DP */ +#define JTAG_DP_ABORT 0x8 +#define JTAG_DP_DPACC 0xA +#define JTAG_DP_APACC 0xB +#define JTAG_DP_IDCODE 0xE + +/* three-bit ACK values for DPACC and APACC reads */ +#define JTAG_ACK_OK_FAULT 0x2 +#define JTAG_ACK_WAIT 0x1 + +/* three-bit ACK values for SWD access (sent LSB first) */ +#define SWD_ACK_OK 0x4 +#define SWD_ACK_WAIT 0x2 +#define SWD_ACK_FAULT 0x1 #define DPAP_WRITE 0 #define DPAP_READ 1 -/* A[3:0] for DP registers (for JTAG, stored in DPACC) */ -#define DP_ZERO 0 -#define DP_CTRL_STAT 0x4 -#define DP_SELECT 0x8 -#define DP_RDBUFF 0xC +/* A[3:0] for DP registers; A[1:0] are always zero. + * - JTAG accesses all of these via JTAG_DP_DPACC, except for + * IDCODE (JTAG_DP_IDCODE) and ABORT (JTAG_DP_ABORT). + * - SWD accesses these directly, sometimes needing SELECT.CTRLSEL + */ +#define DP_IDCODE 0 /* SWD: read */ +#define DP_ABORT 0 /* SWD: write */ +#define DP_CTRL_STAT 0x4 /* r/w */ +#define DP_WCR 0x4 /* SWD: r/w (mux CTRLSEL) */ +#define DP_RESEND 0x8 /* SWD: read */ +#define DP_SELECT 0x8 /* JTAG: r/w; SWD: write */ +#define DP_RDBUFF 0xC /* read-only */ + +/* Fields of the DP's AP ABORT register */ +#define DAPABORT (1 << 0) +#define STKCMPCLR (1 << 1) /* SWD-only */ +#define STKERRCLR (1 << 2) /* SWD-only */ +#define WDERRCLR (1 << 3) /* SWD-only */ +#define ORUNERRCLR (1 << 4) /* SWD-only */ /* Fields of the DP's CTRL/STAT register */ #define CORUNDETECT (1 << 0) #define SSTICKYORUN (1 << 1) /* 3:2 - transaction mode (e.g. pushed compare) */ +#define SSTICKYCMP (1 << 4) #define SSTICKYERR (1 << 5) -#define READOK (1 << 6) -#define WDATAERR (1 << 7) +#define READOK (1 << 6) /* SWD-only */ +#define WDATAERR (1 << 7) /* SWD-only */ /* 11:8 - mask lanes for pushed compare or verify ops */ /* 21:12 - transaction counter */ #define CDBGRSTREQ (1 << 26) @@ -111,50 +138,76 @@ struct swjdp_common struct arm_jtag *jtag_info; /* Control config */ uint32_t dp_ctrl_stat; - /* Support for several AP's in one DAP */ + + /** + * Cache for DP_SELECT bits identifying the current AP. A DAP may + * connect to multiple APs, such as one MEM-AP for general access, + * another reserved for accessing debug modules, and a JTAG-DP. + * "-1" indicates no cached value. + */ uint32_t apsel; - /* Register select cache */ - uint32_t dp_select_value; + + /** + * Cache for DP_SELECT bits identifying the current four-word AP + * register bank. This caches AP register addresss bits 7:4; JTAG + * and SWD access primitves pass address bits 3:2; bits 1:0 are zero. + * "-1" indicates no cached value. + */ + uint32_t ap_bank_value; + + /** + * Cache for (MEM-AP) AP_REG_CSW register value. This is written to + * configure an access mode, such as autoincrementing AP_REG_TAR during + * word access. "-1" indicates no cached value. + */ uint32_t ap_csw_value; + + /** + * Cache for (MEM-AP) AP_REG_TAR register value This is written to + * configure the address being read or written + * "-1" indicates no cached value. + */ uint32_t ap_tar_value; + /* information about current pending SWjDP-AHBAP transaction */ uint8_t trans_mode; uint8_t trans_rw; uint8_t ack; - /* extra tck clocks for memory bus access */ + /** + * Configures how many extra tck clocks are added after starting a + * MEM-AP access before we try to read its status (and/or result). + */ uint32_t memaccess_tck; /* Size of TAR autoincrement block, ARM ADI Specification requires at least 10 bits */ uint32_t tar_autoincr_block; }; -/* Accessor function for currently selected DAP-AP number */ +/** Accessor for currently selected DAP-AP number (0..255) */ static inline uint8_t dap_ap_get_select(struct swjdp_common *swjdp) { return (uint8_t)(swjdp ->apsel >> 24); } -/* Internal functions used in the module, partial transactions, use with caution */ -int dap_dp_write_reg(struct swjdp_common *swjdp, uint32_t value, uint8_t reg_addr); -/* int swjdp_write_apacc(struct swjdp_common *swjdp, uint32_t value, uint8_t reg_addr); */ -int dap_dp_read_reg(struct swjdp_common *swjdp, uint32_t *value, uint8_t reg_addr); -/* int swjdp_read_apacc(struct swjdp_common *swjdp, uint32_t *value, uint8_t reg_addr); */ -int dap_setup_accessport(struct swjdp_common *swjdp, uint32_t csw, uint32_t tar); -int dap_ap_select(struct swjdp_common *swjdp,uint8_t apsel); +/* AP selection applies to future AP transactions */ +void dap_ap_select(struct swjdp_common *dap,uint8_t apsel); -int dap_ap_write_reg(struct swjdp_common *swjdp, uint32_t addr, uint8_t* out_buf); -int dap_ap_write_reg_u32(struct swjdp_common *swjdp, uint32_t addr, uint32_t value); -int dap_ap_read_reg(struct swjdp_common *swjdp, uint32_t addr, uint8_t *in_buf); -int dap_ap_read_reg_u32(struct swjdp_common *swjdp, uint32_t addr, uint32_t *value); +/* AP transactions ... synchronous given TRANS_MODE_ATOMIC */ +int dap_setup_accessport(struct swjdp_common *swjdp, + uint32_t csw, uint32_t tar); +int dap_ap_write_reg_u32(struct swjdp_common *swjdp, + uint32_t addr, uint32_t value); +int dap_ap_read_reg_u32(struct swjdp_common *swjdp, + uint32_t addr, uint32_t *value); -/* External interface, partial operations must be completed with swjdp_transaction_endcheck() */ -int swjdp_transaction_endcheck(struct swjdp_common *swjdp); +/* Queued JTAG ops must be completed with jtagdp_transaction_endcheck() */ +int jtagdp_transaction_endcheck(struct swjdp_common *swjdp); -/* MEM-AP memory mapped bus single uint32_t register transfers, without endcheck */ +/* Queued MEM-AP memory mapped single word transfers */ int mem_ap_read_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t *value); int mem_ap_write_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t value); -/* MEM-AP memory mapped bus transfers, single registers, complete transactions */ +/* Synchronous MEM-AP memory mapped single word transfers */ int mem_ap_read_atomic_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t *value); int mem_ap_write_atomic_u32(struct swjdp_common *swjdp,