X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Farm_adi_v5.h;h=883ac8b5d8df582225eba60d1f67a14a00d09a43;hb=d537cce7ef49bf2f4bc81cf016f784a9adf2537a;hp=3220d8b6d27e12c260b43a6a80cd8a9d426a6241;hpb=d4b7cbff88bb5eb14fececdbd8e2a0b3e58ce6e0;p=openocd.git diff --git a/src/target/arm_adi_v5.h b/src/target/arm_adi_v5.h index 3220d8b6d2..883ac8b5d8 100644 --- a/src/target/arm_adi_v5.h +++ b/src/target/arm_adi_v5.h @@ -102,6 +102,7 @@ #define AP_REG_IDR 0xFC /* RO: Identification Register */ /* Fields of the MEM-AP's CSW register */ +#define CSW_SIZE_MASK 7 #define CSW_8BIT 0 #define CSW_16BIT 1 #define CSW_32BIT 2 @@ -111,13 +112,16 @@ #define CSW_ADDRINC_PACKED (2UL << 4) #define CSW_DEVICE_EN (1UL << 6) #define CSW_TRIN_PROG (1UL << 7) +/* all fields in bits 12 and above are implementation-defined! */ #define CSW_SPIDEN (1UL << 23) -/* 30:24 - implementation-defined! */ -#define CSW_HPROT (1UL << 25) /* ? */ -#define CSW_MASTER_DEBUG (1UL << 29) /* ? */ +#define CSW_HPROT1 (1UL << 25) /* AHB: Privileged */ +#define CSW_MASTER_DEBUG (1UL << 29) /* AHB: set HMASTER signals to AHB-AP ID */ #define CSW_SPROT (1UL << 30) #define CSW_DBGSWENABLE (1UL << 31) +/* initial value of csw_default used for MEM-AP transfers */ +#define CSW_DEFAULT (CSW_HPROT1 | CSW_MASTER_DEBUG | CSW_DBGSWENABLE) + /* Fields of the MEM-AP's IDR register */ #define IDR_REV (0xFUL << 28) #define IDR_JEP106 (0x7FFUL << 17) @@ -180,6 +184,9 @@ struct adiv5_ap { /* true if unaligned memory access is not supported by the MEM-AP */ bool unaligned_access_bad; + + /* true if tar_value is in sync with TAR register */ + bool tar_valid; }; @@ -240,6 +247,10 @@ struct adiv5_dap { * should be performed before the next access. */ bool do_reconnect; + + /** Flag saying whether to ignore the syspwrupack flag in DAP. Some devices + * do not set this bit until later in the bringup sequence */ + bool ignore_syspwrupack; }; /** @@ -250,6 +261,8 @@ struct adiv5_dap { * available until run(). */ struct dap_ops { + /** connect operation for SWD */ + int (*connect)(struct adiv5_dap *dap); /** DP register read. */ int (*queue_dp_read)(struct adiv5_dap *dap, unsigned reg, uint32_t *data); @@ -273,6 +286,9 @@ struct dap_ops { /** Executes all queued DAP operations but doesn't check * sticky error conditions */ int (*sync)(struct adiv5_dap *dap); + + /** Optional; called at OpenOCD exit */ + void (*quit)(struct adiv5_dap *dap); }; /* @@ -469,13 +485,13 @@ int mem_ap_read_buf_noincr(struct adiv5_ap *ap, int mem_ap_write_buf_noincr(struct adiv5_ap *ap, const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address); -/* Create DAP struct */ -struct adiv5_dap *dap_init(void); - /* Initialisation of the debug system, power domains and registers */ int dap_dp_init(struct adiv5_dap *dap); int mem_ap_init(struct adiv5_ap *ap); +/* Invalidate cached DP select and cached TAR and CSW of all APs */ +void dap_invalidate_cache(struct adiv5_dap *dap); + /* Probe the AP for ROM Table location */ int dap_get_debugbase(struct adiv5_ap *ap, uint32_t *dbgbase, uint32_t *apid); @@ -502,6 +518,24 @@ int dap_to_swd(struct target *target); /* Put debug link into JTAG mode */ int dap_to_jtag(struct target *target); -extern const struct command_registration dap_command_handlers[]; +extern const struct command_registration dap_instance_commands[]; + +struct arm_dap_object; +extern struct adiv5_dap *dap_instance_by_jim_obj(Jim_Interp *interp, Jim_Obj *o); +extern struct adiv5_dap *adiv5_get_dap(struct arm_dap_object *obj); +extern int dap_info_command(struct command_context *cmd_ctx, + struct adiv5_ap *ap); +extern int dap_register_commands(struct command_context *cmd_ctx); +extern const char *adiv5_dap_name(struct adiv5_dap *self); +extern const struct swd_driver *adiv5_dap_swd_driver(struct adiv5_dap *self); +extern int dap_cleanup_all(void); + +struct adiv5_private_config { + int ap_num; + struct adiv5_dap *dap; +}; + +extern int adiv5_verify_config(struct adiv5_private_config *pc); +extern int adiv5_jim_configure(struct target *target, Jim_GetOptInfo *goi); #endif /* OPENOCD_TARGET_ARM_ADI_V5_H */