X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Farm_disassembler.c;h=34d679c113b7a33355842294e914653501383725;hb=42cb62cf3b47b982d6444948b483f9c6ce32de05;hp=770c5e9c7a106c341eec250be21a29d72f047f83;hpb=838d41af29c0b703fd55ebb5c3aebcb4e0bea460;p=openocd.git

diff --git a/src/target/arm_disassembler.c b/src/target/arm_disassembler.c
index 770c5e9c7a..34d679c113 100644
--- a/src/target/arm_disassembler.c
+++ b/src/target/arm_disassembler.c
@@ -50,6 +50,7 @@
  *       except as coprocessor 10/11 operations
  *     * Most ARM instructions through ARMv6 are decoded, but some
  *       of the post-ARMv4 opcodes may not be handled yet
+ *		CPS, SDIV, UDIV, LDREX*, STREX*, QASX, ...
  *     * NEON instructions are not understood (ARMv7-A)
  *
  *  - Thumb/Thumb2 decoding
@@ -279,13 +280,13 @@ static int evaluate_ldc_stc_mcrr_mrrc(uint32_t opcode,
 		{
 			instruction->type = ARM_MCRR;
 			mnemonic = "MCRR";
-		}
-
-		/* MRRC */
-		if ((opcode & 0x0ff00000) == 0x0c500000)
-		{
+		} else if ((opcode & 0x0ff00000) == 0x0c500000) {
+			/* MRRC */
 			instruction->type = ARM_MRRC;
 			mnemonic = "MRRC";
+		} else {
+			LOG_ERROR("Unknown instruction");
+			return ERROR_FAIL;
 		}
 
 		snprintf(instruction->text, 128,
@@ -299,7 +300,7 @@ static int evaluate_ldc_stc_mcrr_mrrc(uint32_t opcode,
 	else /* LDC or STC */
 	{
 		uint8_t CRd, Rn, offset;
-		uint8_t U, N;
+		uint8_t U;
 		char *mnemonic;
 		char addressing_mode[32];
 
@@ -320,7 +321,6 @@ static int evaluate_ldc_stc_mcrr_mrrc(uint32_t opcode,
 		}
 
 		U = (opcode & 0x00800000) >> 23;
-		N = (opcode & 0x00400000) >> 22;
 
 		/* addressing modes */
 		if ((opcode & 0x01200000) == 0x01000000) /* offset */
@@ -1097,8 +1097,11 @@ static int evaluate_ldm_stm(uint32_t opcode,
 		}
 	}
 
-	snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s%s r%i%s, {%s}%s",
-			 address, opcode, mnemonic, COND(opcode), addressing_mode,
+	snprintf(instruction->text, 128,
+			"0x%8.8" PRIx32 "\t0x%8.8" PRIx32
+			"\t%s%s%s r%i%s, {%s}%s",
+			 address, opcode,
+			 mnemonic, addressing_mode, COND(opcode),
 			 Rn, (W) ? "!" : "", reg_list, (S) ? "^" : "");
 
 	return ERROR_OK;
@@ -2350,7 +2353,7 @@ static int evaluate_add_sp_pc_thumb(uint16_t opcode,
 	uint8_t Rd = (opcode >> 8) & 0x7;
 	uint8_t Rn;
 	uint32_t SP = opcode & (1 << 11);
-	char *reg_name;
+	const char *reg_name;
 
 	instruction->type = ARM_ADD;
 
@@ -3010,7 +3013,7 @@ static int t2ev_misc(uint32_t opcode, uint32_t address,
 		mnemonic = "ISB";
 		break;
 	default:
-		return ERROR_INVALID_ARGUMENTS;
+		return ERROR_COMMAND_SYNTAX_ERROR;
 	}
 	strcpy(cp, mnemonic);
 	return ERROR_OK;
@@ -3061,7 +3064,7 @@ static int t2ev_b_misc(uint32_t opcode, uint32_t address,
 	}
 
 undef:
-	return ERROR_INVALID_ARGUMENTS;
+	return ERROR_COMMAND_SYNTAX_ERROR;
 }
 
 static int t2ev_data_mod_immed(uint32_t opcode, uint32_t address,
@@ -3196,7 +3199,7 @@ static int t2ev_data_mod_immed(uint32_t opcode, uint32_t address,
 		suffix2 = ".W";
 		break;
 	default:
-		return ERROR_INVALID_ARGUMENTS;
+		return ERROR_COMMAND_SYNTAX_ERROR;
 	}
 
 	if (one)
@@ -3244,7 +3247,7 @@ static int t2ev_data_immed(uint32_t opcode, uint32_t address,
 	case 0x0c:
 		/* move constant to top 16 bits of register */
 		immed |= (opcode >> 4) & 0xf000;
-		sprintf(cp, "MOVT\tr%d, #%d\t; %#4.4x", rn, immed, immed);
+		sprintf(cp, "MOVT\tr%d, #%d\t; %#4.4x", rd, immed, immed);
 		return ERROR_OK;
 	case 0x10:
 	case 0x12:
@@ -3285,7 +3288,7 @@ static int t2ev_data_immed(uint32_t opcode, uint32_t address,
 					(int) (opcode & 0x1f) + 1 - immed);
 		return ERROR_OK;
 	default:
-		return ERROR_INVALID_ARGUMENTS;
+		return ERROR_COMMAND_SYNTAX_ERROR;
 	}
 
 	sprintf(cp, "%s\tr%d, r%d, #%d\t; %#3.3x", mnemonic,
@@ -3318,7 +3321,7 @@ static int t2ev_store_single(uint32_t opcode, uint32_t address,
 	unsigned rt = (opcode >> 12) & 0x0f;
 
 	if (rn == 0xf)
-		return ERROR_INVALID_ARGUMENTS;
+		return ERROR_COMMAND_SYNTAX_ERROR;
 
 	if (opcode & 0x0800)
 		op |= 1;
@@ -3355,7 +3358,7 @@ static int t2ev_store_single(uint32_t opcode, uint32_t address,
 		break;
 	/* error */
 	default:
-		return ERROR_INVALID_ARGUMENTS;
+		return ERROR_COMMAND_SYNTAX_ERROR;
 	}
 
 	sprintf(cp, "STR%s.W\tr%d, [r%d, r%d, LSL #%d]",
@@ -3378,7 +3381,7 @@ imm8:
 		break;
 	case 0x000:
 	case 0x200:
-		return ERROR_INVALID_ARGUMENTS;
+		return ERROR_COMMAND_SYNTAX_ERROR;
 	}
 
 	/* two indexed modes will write back rn */
@@ -3423,7 +3426,7 @@ static int t2ev_mul32(uint32_t opcode, uint32_t address,
 			(int) (opcode >> 0) & 0xf, ra);
 		break;
 	default:
-		return ERROR_INVALID_ARGUMENTS;
+		return ERROR_COMMAND_SYNTAX_ERROR;
 	}
 	return ERROR_OK;
 }
@@ -3459,7 +3462,7 @@ static int t2ev_mul64_div(uint32_t opcode, uint32_t address,
 				(int) (opcode >> 0) & 0xf);
 		break;
 	default:
-		return ERROR_INVALID_ARGUMENTS;
+		return ERROR_COMMAND_SYNTAX_ERROR;
 	}
 
 	return ERROR_OK;
@@ -3513,7 +3516,7 @@ static int t2ev_ldm_stm(uint32_t opcode, uint32_t address,
 		sprintf(cp, "LDMDB.W\tr%d%s, ", rn, t ? "!" : "");
 		break;
 	default:
-		return ERROR_INVALID_ARGUMENTS;
+		return ERROR_COMMAND_SYNTAX_ERROR;
 	}
 
 	cp = strchr(cp, 0);
@@ -3581,7 +3584,7 @@ static int t2ev_ldrex_strex(uint32_t opcode, uint32_t address,
 			mnemonic = "STREXH";
 			break;
 		default:
-			return ERROR_INVALID_ARGUMENTS;
+			return ERROR_COMMAND_SYNTAX_ERROR;
 		}
 		rd = opcode & 0xf;
 		imm = 0;
@@ -3601,12 +3604,12 @@ static int t2ev_ldrex_strex(uint32_t opcode, uint32_t address,
 			mnemonic = "LDREXH";
 			break;
 		default:
-			return ERROR_INVALID_ARGUMENTS;
+			return ERROR_COMMAND_SYNTAX_ERROR;
 		}
 		imm = 0;
 		goto ldrex;
 	}
-	return ERROR_INVALID_ARGUMENTS;
+	return ERROR_COMMAND_SYNTAX_ERROR;
 
 strex:
 	imm <<= 2;
@@ -3677,7 +3680,7 @@ static int t2ev_data_shift(uint32_t opcode, uint32_t address,
 	case 0:
 		if (rd == 0xf) {
 			if (!(opcode & (1 << 20)))
-				return ERROR_INVALID_ARGUMENTS;
+				return ERROR_COMMAND_SYNTAX_ERROR;
 			instruction->type = ARM_TST;
 			mnemonic = "TST";
 			suffix = "";
@@ -3739,7 +3742,7 @@ static int t2ev_data_shift(uint32_t opcode, uint32_t address,
 	case 4:
 		if (rd == 0xf) {
 			if (!(opcode & (1 << 20)))
-				return ERROR_INVALID_ARGUMENTS;
+				return ERROR_COMMAND_SYNTAX_ERROR;
 			instruction->type = ARM_TEQ;
 			mnemonic = "TEQ";
 			suffix = "";
@@ -3751,7 +3754,7 @@ static int t2ev_data_shift(uint32_t opcode, uint32_t address,
 	case 8:
 		if (rd == 0xf) {
 			if (!(opcode & (1 << 20)))
-				return ERROR_INVALID_ARGUMENTS;
+				return ERROR_COMMAND_SYNTAX_ERROR;
 			instruction->type = ARM_CMN;
 			mnemonic = "CMN";
 			suffix = "";
@@ -3771,7 +3774,7 @@ static int t2ev_data_shift(uint32_t opcode, uint32_t address,
 	case 0xd:
 		if (rd == 0xf) {
 			if (!(opcode & (1 << 21)))
-				return ERROR_INVALID_ARGUMENTS;
+				return ERROR_COMMAND_SYNTAX_ERROR;
 			instruction->type = ARM_CMP;
 			mnemonic = "CMP";
 			suffix = "";
@@ -3785,7 +3788,7 @@ static int t2ev_data_shift(uint32_t opcode, uint32_t address,
 		mnemonic = "RSB";
 		break;
 	default:
-		return ERROR_INVALID_ARGUMENTS;
+		return ERROR_COMMAND_SYNTAX_ERROR;
 	}
 
 	sprintf(cp, "%s%s.W\tr%d, r%d, r%d",
@@ -3854,7 +3857,7 @@ static int t2ev_data_reg(uint32_t opcode, uint32_t address,
 			mnemonic = "ROR";
 			break;
 		default:
-			return ERROR_INVALID_ARGUMENTS;
+			return ERROR_COMMAND_SYNTAX_ERROR;
 		}
 
 		instruction->type = ARM_MOV;
@@ -3895,11 +3898,11 @@ static int t2ev_data_reg(uint32_t opcode, uint32_t address,
 		case 0xa:
 		case 0xb:
 			if (opcode & (1 << 6))
-				return ERROR_INVALID_ARGUMENTS;
+				return ERROR_COMMAND_SYNTAX_ERROR;
 			if (((opcode >> 12) & 0xf) != 0xf)
-				return ERROR_INVALID_ARGUMENTS;
+				return ERROR_COMMAND_SYNTAX_ERROR;
 			if (!(opcode & (1 << 20)))
-				return ERROR_INVALID_ARGUMENTS;
+				return ERROR_COMMAND_SYNTAX_ERROR;
 
 			switch (((opcode >> 19) & 0x04)
 				| ((opcode >> 4) & 0x3)) {
@@ -3919,7 +3922,7 @@ static int t2ev_data_reg(uint32_t opcode, uint32_t address,
 				mnemonic = "CLZ";
 				break;
 			default:
-				return ERROR_INVALID_ARGUMENTS;
+				return ERROR_COMMAND_SYNTAX_ERROR;
 			}
 			sprintf(cp, "%s\tr%d, r%d",
 					mnemonic,
@@ -3927,7 +3930,7 @@ static int t2ev_data_reg(uint32_t opcode, uint32_t address,
 					(int) (opcode >> 0) & 0xf);
 			break;
 		default:
-			return ERROR_INVALID_ARGUMENTS;
+			return ERROR_COMMAND_SYNTAX_ERROR;
 		}
 	}
 
@@ -3983,7 +3986,7 @@ static int t2ev_load_word(uint32_t opcode, uint32_t address,
 		char *p1 = "]", *p2 = "";
 
 		if (!(opcode & 0x0500))
-			return ERROR_INVALID_ARGUMENTS;
+			return ERROR_COMMAND_SYNTAX_ERROR;
 
 		immed = opcode & 0x00ff;
 
@@ -4005,7 +4008,7 @@ static int t2ev_load_word(uint32_t opcode, uint32_t address,
 		return ERROR_OK;
 	}
 
-	return ERROR_INVALID_ARGUMENTS;
+	return ERROR_COMMAND_SYNTAX_ERROR;
 }
 
 static int t2ev_load_byte_hints(uint32_t opcode, uint32_t address,
@@ -4184,7 +4187,7 @@ ldrsb_literal:
 		goto ldrxb_immediate_t2;
 	}
 
-	return ERROR_INVALID_ARGUMENTS;
+	return ERROR_COMMAND_SYNTAX_ERROR;
 }
 
 static int t2ev_load_halfword(uint32_t opcode, uint32_t address,
@@ -4262,7 +4265,7 @@ ldrh_literal:
 		return ERROR_OK;
 	}
 
-	return ERROR_INVALID_ARGUMENTS;
+	return ERROR_COMMAND_SYNTAX_ERROR;
 }
 
 /*
@@ -4374,7 +4377,7 @@ int thumb2_opcode(struct target *target, uint32_t address, struct arm_instructio
 	 * instructions; not yet handled here.
 	 */
 
-	if (retval == ERROR_INVALID_ARGUMENTS) {
+	if (retval == ERROR_COMMAND_SYNTAX_ERROR) {
 		instruction->type = ARM_UNDEFINED_INSTRUCTION;
 		strcpy(cp, "UNDEFINED OPCODE");
 		return ERROR_OK;