X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Farm_disassembler.c;h=36566c9932ec725a52814100e1fbfceb5429cdec;hb=9b9092b7faa5859dd1a14489a312465782e2bef1;hp=587131bcc6200a5fc7d53389a0a51a4faece115b;hpb=b4a4d5c7310c88ef263bfaaa060b5c249d98c446;p=openocd.git

diff --git a/src/target/arm_disassembler.c b/src/target/arm_disassembler.c
index 587131bcc6..36566c9932 100644
--- a/src/target/arm_disassembler.c
+++ b/src/target/arm_disassembler.c
@@ -50,6 +50,7 @@
  *       except as coprocessor 10/11 operations
  *     * Most ARM instructions through ARMv6 are decoded, but some
  *       of the post-ARMv4 opcodes may not be handled yet
+ *		CPS, SDIV, UDIV, LDREX*, STREX*, QASX, ...
  *     * NEON instructions are not understood (ARMv7-A)
  *
  *  - Thumb/Thumb2 decoding
@@ -299,7 +300,7 @@ static int evaluate_ldc_stc_mcrr_mrrc(uint32_t opcode,
 	else /* LDC or STC */
 	{
 		uint8_t CRd, Rn, offset;
-		uint8_t U, N;
+		uint8_t U;
 		char *mnemonic;
 		char addressing_mode[32];
 
@@ -320,7 +321,6 @@ static int evaluate_ldc_stc_mcrr_mrrc(uint32_t opcode,
 		}
 
 		U = (opcode & 0x00800000) >> 23;
-		N = (opcode & 0x00400000) >> 22;
 
 		/* addressing modes */
 		if ((opcode & 0x01200000) == 0x01000000) /* offset */
@@ -2353,7 +2353,7 @@ static int evaluate_add_sp_pc_thumb(uint16_t opcode,
 	uint8_t Rd = (opcode >> 8) & 0x7;
 	uint8_t Rn;
 	uint32_t SP = opcode & (1 << 11);
-	char *reg_name;
+	const char *reg_name;
 
 	instruction->type = ARM_ADD;