X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Farm_simulator.c;h=058e3d38b8020a02e3f8d1a205b7e54bf2d2315a;hb=382148e4dd437978997d668f6ec715ddcec1c46e;hp=9ddc85be06a67339110c0de986151e85d9159af5;hpb=f97a1594119f90f63526e1fa8a95dbcba0acd192;p=openocd.git diff --git a/src/target/arm_simulator.c b/src/target/arm_simulator.c index 9ddc85be06..058e3d38b8 100644 --- a/src/target/arm_simulator.c +++ b/src/target/arm_simulator.c @@ -1,24 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + /*************************************************************************** * Copyright (C) 2006 by Dominic Rath * * Dominic.Rath@gmx.de * * * * Copyright (C) 2008 by Hongtao Zheng * * hontor@126.com * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, write to the * - * Free Software Foundation, Inc., * - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ #ifdef HAVE_CONFIG_H @@ -33,7 +20,7 @@ #include "register.h" #include -static uint32_t arm_shift(uint8_t shift, uint32_t Rm, +static uint32_t arm_shift(uint8_t shift, uint32_t rm, uint32_t shift_amount, uint8_t *carry) { uint32_t return_value = 0; @@ -41,22 +28,22 @@ static uint32_t arm_shift(uint8_t shift, uint32_t Rm, if (shift == 0x0) { /* LSL */ if ((shift_amount > 0) && (shift_amount <= 32)) { - return_value = Rm << shift_amount; - *carry = Rm >> (32 - shift_amount); + return_value = rm << shift_amount; + *carry = rm >> (32 - shift_amount); } else if (shift_amount > 32) { return_value = 0x0; *carry = 0x0; } else /* (shift_amount == 0) */ - return_value = Rm; + return_value = rm; } else if (shift == 0x1) { /* LSR */ if ((shift_amount > 0) && (shift_amount <= 32)) { - return_value = Rm >> shift_amount; - *carry = (Rm >> (shift_amount - 1)) & 1; + return_value = rm >> shift_amount; + *carry = (rm >> (shift_amount - 1)) & 1; } else if (shift_amount > 32) { return_value = 0x0; *carry = 0x0; } else /* (shift_amount == 0) */ - return_value = Rm; + return_value = rm; } else if (shift == 0x2) { /* ASR */ if ((shift_amount > 0) && (shift_amount <= 32)) { /* C right shifts of unsigned values are guaranteed to @@ -64,11 +51,11 @@ static uint32_t arm_shift(uint8_t shift, uint32_t Rm, * shift (shift in signed-bit) by adding the sign bit * manually */ - return_value = Rm >> shift_amount; - if (Rm & 0x80000000) + return_value = rm >> shift_amount; + if (rm & 0x80000000) return_value |= 0xffffffff << (32 - shift_amount); } else if (shift_amount > 32) { - if (Rm & 0x80000000) { + if (rm & 0x80000000) { return_value = 0xffffffff; *carry = 0x1; } else { @@ -76,20 +63,20 @@ static uint32_t arm_shift(uint8_t shift, uint32_t Rm, *carry = 0x0; } } else /* (shift_amount == 0) */ - return_value = Rm; + return_value = rm; } else if (shift == 0x3) { /* ROR */ if (shift_amount == 0) - return_value = Rm; + return_value = rm; else { shift_amount = shift_amount % 32; - return_value = (Rm >> shift_amount) | (Rm << (32 - shift_amount)); + return_value = (rm >> shift_amount) | (rm << (32 - shift_amount)); *carry = (return_value >> 31) & 0x1; } } else if (shift == 0x4) { /* RRX */ - return_value = Rm >> 1; + return_value = rm >> 1; if (*carry) - Rm |= 0x80000000; - *carry = Rm & 0x1; + rm |= 0x80000000; + *carry = rm & 0x1; } return return_value; @@ -113,25 +100,25 @@ static uint32_t arm_shifter_operand(struct arm_sim_interface *sim, if (variant == 0) /* 32-bit immediate */ return_value = shifter_operand.immediate.immediate; else if (variant == 1) {/* immediate shift */ - uint32_t Rm = sim->get_reg_mode(sim, shifter_operand.immediate_shift.Rm); + uint32_t rm = sim->get_reg_mode(sim, shifter_operand.immediate_shift.rm); /* adjust RM in case the PC is being read */ - if (shifter_operand.immediate_shift.Rm == 15) - Rm += 2 * instruction_size; + if (shifter_operand.immediate_shift.rm == 15) + rm += 2 * instruction_size; return_value = arm_shift(shifter_operand.immediate_shift.shift, - Rm, shifter_operand.immediate_shift.shift_imm, + rm, shifter_operand.immediate_shift.shift_imm, shifter_carry_out); } else if (variant == 2) { /* register shift */ - uint32_t Rm = sim->get_reg_mode(sim, shifter_operand.register_shift.Rm); - uint32_t Rs = sim->get_reg_mode(sim, shifter_operand.register_shift.Rs); + uint32_t rm = sim->get_reg_mode(sim, shifter_operand.register_shift.rm); + uint32_t rs = sim->get_reg_mode(sim, shifter_operand.register_shift.rs); /* adjust RM in case the PC is being read */ - if (shifter_operand.register_shift.Rm == 15) - Rm += 2 * instruction_size; + if (shifter_operand.register_shift.rm == 15) + rm += 2 * instruction_size; return_value = arm_shift(shifter_operand.immediate_shift.shift, - Rm, Rs, shifter_carry_out); + rm, rs, shifter_carry_out); } else { LOG_ERROR("BUG: shifter_operand.variant not 0, 1 or 2"); return_value = 0xffffffff; @@ -326,8 +313,8 @@ static int arm_simulate_step_core(struct target *target, sim->set_reg(sim, 15, target_address); else if (instruction.type == ARM_BL) { uint32_t old_pc = sim->get_reg(sim, 15); - int T = (sim->get_state(sim) == ARM_STATE_THUMB); - sim->set_reg_mode(sim, 14, old_pc + 4 + T); + int t = (sim->get_state(sim) == ARM_STATE_THUMB); + sim->set_reg_mode(sim, 14, old_pc + 4 + t); sim->set_reg(sim, 15, target_address); } else if (instruction.type == ARM_BX) { if (target_address & 0x1) @@ -337,8 +324,8 @@ static int arm_simulate_step_core(struct target *target, sim->set_reg(sim, 15, target_address & 0xfffffffe); } else if (instruction.type == ARM_BLX) { uint32_t old_pc = sim->get_reg(sim, 15); - int T = (sim->get_state(sim) == ARM_STATE_THUMB); - sim->set_reg_mode(sim, 14, old_pc + 4 + T); + int t = (sim->get_state(sim) == ARM_STATE_THUMB); + sim->set_reg_mode(sim, 14, old_pc + 4 + t); if (target_address & 0x1) sim->set_state(sim, ARM_STATE_THUMB); @@ -353,16 +340,16 @@ static int arm_simulate_step_core(struct target *target, /* data processing instructions, except compare instructions (CMP, CMN, TST, TEQ) */ else if (((instruction.type >= ARM_AND) && (instruction.type <= ARM_RSC)) || ((instruction.type >= ARM_ORR) && (instruction.type <= ARM_MVN))) { - uint32_t Rd, Rn, shifter_operand; - uint8_t C = sim->get_cpsr(sim, 29, 1); + uint32_t rd, rn, shifter_operand; + uint8_t c = sim->get_cpsr(sim, 29, 1); uint8_t carry_out; - Rd = 0x0; + rd = 0x0; /* ARM_MOV and ARM_MVN does not use Rn */ if ((instruction.type != ARM_MOV) && (instruction.type != ARM_MVN)) - Rn = sim->get_reg_mode(sim, instruction.info.data_proc.Rn); + rn = sim->get_reg_mode(sim, instruction.info.data_proc.rn); else - Rn = 0; + rn = 0; shifter_operand = arm_shifter_operand(sim, instruction.info.data_proc.variant, @@ -370,53 +357,53 @@ static int arm_simulate_step_core(struct target *target, &carry_out); /* adjust Rn in case the PC is being read */ - if (instruction.info.data_proc.Rn == 15) - Rn += 2 * instruction_size; + if (instruction.info.data_proc.rn == 15) + rn += 2 * instruction_size; if (instruction.type == ARM_AND) - Rd = Rn & shifter_operand; + rd = rn & shifter_operand; else if (instruction.type == ARM_EOR) - Rd = Rn ^ shifter_operand; + rd = rn ^ shifter_operand; else if (instruction.type == ARM_SUB) - Rd = Rn - shifter_operand; + rd = rn - shifter_operand; else if (instruction.type == ARM_RSB) - Rd = shifter_operand - Rn; + rd = shifter_operand - rn; else if (instruction.type == ARM_ADD) - Rd = Rn + shifter_operand; + rd = rn + shifter_operand; else if (instruction.type == ARM_ADC) - Rd = Rn + shifter_operand + (C & 1); + rd = rn + shifter_operand + (c & 1); else if (instruction.type == ARM_SBC) - Rd = Rn - shifter_operand - (C & 1) ? 0 : 1; + rd = rn - shifter_operand - (c & 1) ? 0 : 1; else if (instruction.type == ARM_RSC) - Rd = shifter_operand - Rn - (C & 1) ? 0 : 1; + rd = shifter_operand - rn - (c & 1) ? 0 : 1; else if (instruction.type == ARM_ORR) - Rd = Rn | shifter_operand; + rd = rn | shifter_operand; else if (instruction.type == ARM_BIC) - Rd = Rn & ~(shifter_operand); + rd = rn & ~(shifter_operand); else if (instruction.type == ARM_MOV) - Rd = shifter_operand; + rd = shifter_operand; else if (instruction.type == ARM_MVN) - Rd = ~shifter_operand; + rd = ~shifter_operand; else LOG_WARNING("unhandled instruction type"); if (dry_run_pc) { - if (instruction.info.data_proc.Rd == 15) - *dry_run_pc = Rd & ~1; + if (instruction.info.data_proc.rd == 15) + *dry_run_pc = rd & ~1; else *dry_run_pc = current_pc + instruction_size; return ERROR_OK; } else { - if (instruction.info.data_proc.Rd == 15) { - sim->set_reg_mode(sim, 15, Rd & ~1); - if (Rd & 1) + if (instruction.info.data_proc.rd == 15) { + sim->set_reg_mode(sim, 15, rd & ~1); + if (rd & 1) sim->set_state(sim, ARM_STATE_THUMB); else sim->set_state(sim, ARM_STATE_ARM); return ERROR_OK; } - sim->set_reg_mode(sim, instruction.info.data_proc.Rd, Rd); + sim->set_reg_mode(sim, instruction.info.data_proc.rd, rd); LOG_WARNING("no updating of flags yet"); } } @@ -431,31 +418,31 @@ static int arm_simulate_step_core(struct target *target, /* load register instructions */ else if ((instruction.type >= ARM_LDR) && (instruction.type <= ARM_LDRSH)) { uint32_t load_address = 0, modified_address = 0, load_value = 0; - uint32_t Rn = sim->get_reg_mode(sim, instruction.info.load_store.Rn); + uint32_t rn = sim->get_reg_mode(sim, instruction.info.load_store.rn); /* adjust Rn in case the PC is being read */ - if (instruction.info.load_store.Rn == 15) - Rn += 2 * instruction_size; + if (instruction.info.load_store.rn == 15) + rn += 2 * instruction_size; if (instruction.info.load_store.offset_mode == 0) { - if (instruction.info.load_store.U) - modified_address = Rn + instruction.info.load_store.offset.offset; + if (instruction.info.load_store.u) + modified_address = rn + instruction.info.load_store.offset.offset; else - modified_address = Rn - instruction.info.load_store.offset.offset; + modified_address = rn - instruction.info.load_store.offset.offset; } else if (instruction.info.load_store.offset_mode == 1) { uint32_t offset; - uint32_t Rm = sim->get_reg_mode(sim, - instruction.info.load_store.offset.reg.Rm); + uint32_t rm = sim->get_reg_mode(sim, + instruction.info.load_store.offset.reg.rm); uint8_t shift = instruction.info.load_store.offset.reg.shift; uint8_t shift_imm = instruction.info.load_store.offset.reg.shift_imm; uint8_t carry = sim->get_cpsr(sim, 29, 1); - offset = arm_shift(shift, Rm, shift_imm, &carry); + offset = arm_shift(shift, rm, shift_imm, &carry); - if (instruction.info.load_store.U) - modified_address = Rn + offset; + if (instruction.info.load_store.u) + modified_address = rn + offset; else - modified_address = Rn - offset; + modified_address = rn - offset; } else LOG_ERROR("BUG: offset_mode neither 0 (offset) nor 1 (scaled register)"); @@ -465,7 +452,7 @@ static int arm_simulate_step_core(struct target *target, * the base address register */ load_address = modified_address; - modified_address = Rn; + modified_address = rn; } else if (instruction.info.load_store.index_mode == 1) { /* pre-indexed mode * we load from the modified address, and write it @@ -477,17 +464,17 @@ static int arm_simulate_step_core(struct target *target, * we load from the unmodified address, and write the * modified address back */ - load_address = Rn; + load_address = rn; } - if ((!dry_run_pc) || (instruction.info.load_store.Rd == 15)) { + if ((!dry_run_pc) || (instruction.info.load_store.rd == 15)) { retval = target_read_u32(target, load_address, &load_value); if (retval != ERROR_OK) return retval; } if (dry_run_pc) { - if (instruction.info.load_store.Rd == 15) + if (instruction.info.load_store.rd == 15) *dry_run_pc = load_value & ~1; else *dry_run_pc = current_pc + instruction_size; @@ -496,10 +483,10 @@ static int arm_simulate_step_core(struct target *target, if ((instruction.info.load_store.index_mode == 1) || (instruction.info.load_store.index_mode == 2)) sim->set_reg_mode(sim, - instruction.info.load_store.Rn, + instruction.info.load_store.rn, modified_address); - if (instruction.info.load_store.Rd == 15) { + if (instruction.info.load_store.rd == 15) { sim->set_reg_mode(sim, 15, load_value & ~1); if (load_value & 1) sim->set_state(sim, ARM_STATE_THUMB); @@ -507,13 +494,13 @@ static int arm_simulate_step_core(struct target *target, sim->set_state(sim, ARM_STATE_ARM); return ERROR_OK; } - sim->set_reg_mode(sim, instruction.info.load_store.Rd, load_value); + sim->set_reg_mode(sim, instruction.info.load_store.rd, load_value); } } /* load multiple instruction */ else if (instruction.type == ARM_LDM) { int i; - uint32_t Rn = sim->get_reg_mode(sim, instruction.info.load_store_multiple.Rn); + uint32_t rn = sim->get_reg_mode(sim, instruction.info.load_store_multiple.rn); uint32_t load_values[16]; int bits_set = 0; @@ -524,24 +511,24 @@ static int arm_simulate_step_core(struct target *target, switch (instruction.info.load_store_multiple.addressing_mode) { case 0: /* Increment after */ - /* Rn = Rn; */ + /* rn = rn; */ break; case 1: /* Increment before */ - Rn = Rn + 4; + rn = rn + 4; break; case 2: /* Decrement after */ - Rn = Rn - (bits_set * 4) + 4; + rn = rn - (bits_set * 4) + 4; break; case 3: /* Decrement before */ - Rn = Rn - (bits_set * 4); + rn = rn - (bits_set * 4); break; } for (i = 0; i < 16; i++) { if (instruction.info.load_store_multiple.register_list & (1 << i)) { if ((!dry_run_pc) || (i == 15)) - target_read_u32(target, Rn, &load_values[i]); - Rn += 4; + target_read_u32(target, rn, &load_values[i]); + rn += 4; } } @@ -553,7 +540,7 @@ static int arm_simulate_step_core(struct target *target, } else { int update_cpsr = 0; - if (instruction.info.load_store_multiple.S) { + if (instruction.info.load_store_multiple.s) { if (instruction.info.load_store_multiple.register_list & 0x8000) update_cpsr = 1; } @@ -578,8 +565,8 @@ static int arm_simulate_step_core(struct target *target, } /* base register writeback */ - if (instruction.info.load_store_multiple.W) - sim->set_reg_mode(sim, instruction.info.load_store_multiple.Rn, Rn); + if (instruction.info.load_store_multiple.w) + sim->set_reg_mode(sim, instruction.info.load_store_multiple.rn, rn); if (instruction.info.load_store_multiple.register_list & 0x8000) @@ -593,8 +580,8 @@ static int arm_simulate_step_core(struct target *target, if (dry_run_pc) { /* STM wont affect PC (advance by instruction size */ } else { - uint32_t Rn = sim->get_reg_mode(sim, - instruction.info.load_store_multiple.Rn); + uint32_t rn = sim->get_reg_mode(sim, + instruction.info.load_store_multiple.rn); int bits_set = 0; for (i = 0; i < 16; i++) { @@ -604,30 +591,30 @@ static int arm_simulate_step_core(struct target *target, switch (instruction.info.load_store_multiple.addressing_mode) { case 0: /* Increment after */ - /* Rn = Rn; */ + /* rn = rn; */ break; case 1: /* Increment before */ - Rn = Rn + 4; + rn = rn + 4; break; case 2: /* Decrement after */ - Rn = Rn - (bits_set * 4) + 4; + rn = rn - (bits_set * 4) + 4; break; case 3: /* Decrement before */ - Rn = Rn - (bits_set * 4); + rn = rn - (bits_set * 4); break; } for (i = 0; i < 16; i++) { if (instruction.info.load_store_multiple.register_list & (1 << i)) { - target_write_u32(target, Rn, sim->get_reg_mode(sim, i)); - Rn += 4; + target_write_u32(target, rn, sim->get_reg_mode(sim, i)); + rn += 4; } } /* base register writeback */ - if (instruction.info.load_store_multiple.W) + if (instruction.info.load_store_multiple.w) sim->set_reg_mode(sim, - instruction.info.load_store_multiple.Rn, Rn); + instruction.info.load_store_multiple.rn, rn); } } else if (!dry_run_pc) {