X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Farm_simulator.c;h=1723b438deb16cba4a02bee2d111ee70ca6eb078;hb=42cb62cf3b47b982d6444948b483f9c6ce32de05;hp=0a34cfcf4967fd207e6a2a84673b85aa7b9e1af4;hpb=1cfb2287a67c1f78b76583b2e5ed83ca3560b0d5;p=openocd.git

diff --git a/src/target/arm_simulator.c b/src/target/arm_simulator.c
index 0a34cfcf49..1723b438de 100644
--- a/src/target/arm_simulator.c
+++ b/src/target/arm_simulator.c
@@ -519,7 +519,7 @@ static int arm_simulate_step_core(struct target *target,
 	/* load register instructions */
 	else if ((instruction.type >= ARM_LDR) && (instruction.type <= ARM_LDRSH))
 	{
-		uint32_t load_address = 0, modified_address = 0, load_value;
+		uint32_t load_address = 0, modified_address = 0, load_value = 0;
 		uint32_t Rn = sim->get_reg_mode(sim, instruction.info.load_store.Rn);
 
 		/* adjust Rn in case the PC is being read */