X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Farm_simulator.c;h=561b14f8f2c71bbbadf7738a0dcbae2cb0fdff95;hb=55f2fe830a541a297d6bf3906c6a28df81acbf05;hp=fd0b309cec7338cfd0740df58f021d9dd22ae456;hpb=4a5f45e87d593d6911da680cb92ffbc9b43c9486;p=openocd.git

diff --git a/src/target/arm_simulator.c b/src/target/arm_simulator.c
index fd0b309cec..561b14f8f2 100644
--- a/src/target/arm_simulator.c
+++ b/src/target/arm_simulator.c
@@ -257,6 +257,11 @@ int pass_condition(u32 cpsr, u32 opcode)
 	return 0;
 }
 
+int thumb_pass_branch_condition(u32 cpsr, u16 opcode)
+{
+	return pass_condition(cpsr, (opcode & 0x0f00) << 20); 
+}
+
 /* simulate a single step (if possible)
  * if the dry_run_pc argument is provided, no state is changed,
  * but the new pc is stored in the variable pointed at by the argument
@@ -275,26 +280,43 @@ int arm_simulate_step(target_t *target, u32 *dry_run_pc)
 		target_read_u32(target, current_pc, &opcode);
 		arm_evaluate_opcode(opcode, current_pc, &instruction);
 		instruction_size = 4;
+		
+		/* check condition code (for all instructions) */
+		if (!pass_condition(buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32), opcode))
+		{
+			if (dry_run_pc)
+			{
+				*dry_run_pc = current_pc + instruction_size;
+			}
+			else
+			{
+				buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, current_pc + instruction_size);
+			}
+			
+			return ERROR_OK;
+		}
 	}
 	else
 	{
-		/* TODO: add support for Thumb instruction set */
+		target_read_u32(target, current_pc, &opcode);
+		arm_evaluate_opcode(opcode, current_pc, &instruction);
 		instruction_size = 2;
-	}
-	
-	/* check condition code */
-	if (!pass_condition(buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32), opcode))
-	{
-		if (dry_run_pc)
-		{
-			*dry_run_pc = current_pc + instruction_size;
-		}
-		else
+		
+		/* check condition code (only for branch instructions) */
+		if ((!thumb_pass_branch_condition(buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32), opcode)) &&
+			(instruction.type == ARM_B))
 		{
-			buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, current_pc + instruction_size);
+			if (dry_run_pc)
+			{
+				*dry_run_pc = current_pc + instruction_size;
+			}
+			else
+			{
+				buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, current_pc + instruction_size);
+			}
+			
+			return ERROR_OK;
 		}
-		
-		return ERROR_OK;
 	}
 	
 	/* examine instruction type */