X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Farmv4_5.c;h=0b6b34570a6f702461ddd241ea6ad949917accb1;hb=d3f0549f08d8aac36143bca9e7f7e1308383b7c2;hp=2ee34e29c4c540b6bdc3465c8bbf4f812140487c;hpb=82d2633b5f550115e9e7c7d0520babb6680aa38f;p=openocd.git diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c index 2ee34e29c4..0b6b34570a 100644 --- a/src/target/armv4_5.c +++ b/src/target/armv4_5.c @@ -174,16 +174,16 @@ int armv4_5_mode_to_number(enum armv4_5_mode mode) { switch (mode) { - case 16: return 0; break; - case 17: return 1; break; - case 18: return 2; break; - case 19: return 3; break; - case 23: return 4; break; - case 27: return 5; break; - case 31: return 6; break; - case -1: return 0; break; /* map MODE_ANY to user mode */ + case ARMV4_5_MODE_USR: return 0; break; + case ARMV4_5_MODE_FIQ: return 1; break; + case ARMV4_5_MODE_IRQ: return 2; break; + case ARMV4_5_MODE_SVC: return 3; break; + case ARMV4_5_MODE_ABT: return 4; break; + case ARMV4_5_MODE_UND: return 5; break; + case ARMV4_5_MODE_SYS: return 6; break; + case ARMV4_5_MODE_ANY: return 0; break; /* map MODE_ANY to user mode */ default: - ERROR("invalid mode value encountered"); + LOG_ERROR("invalid mode value encountered"); return -1; } } @@ -201,7 +201,7 @@ enum armv4_5_mode armv4_5_number_to_mode(int number) case 5: return ARMV4_5_MODE_UND; break; case 6: return ARMV4_5_MODE_SYS; break; default: - ERROR("mode index out of bounds"); + LOG_ERROR("mode index out of bounds"); return -1; } }; @@ -217,22 +217,55 @@ int armv4_5_get_core_reg(reg_t *reg) return ERROR_TARGET_NOT_HALTED; } - //retval = armv4_5->armv4_5_common->full_context(target); + /* retval = armv4_5->armv4_5_common->full_context(target); */ retval = armv4_5->armv4_5_common->read_core_reg(target, armv4_5->num, armv4_5->mode); return retval; } -int armv4_5_set_core_reg(reg_t *reg, u32 value) +int armv4_5_set_core_reg(reg_t *reg, u8 *buf) { armv4_5_core_reg_t *armv4_5 = reg->arch_info; target_t *target = armv4_5->target; + armv4_5_common_t *armv4_5_target = target->arch_info; + u32 value = buf_get_u32(buf, 0, 32); if (target->state != TARGET_HALTED) { return ERROR_TARGET_NOT_HALTED; } + if (reg == &armv4_5_target->core_cache->reg_list[ARMV4_5_CPSR]) + { + if (value & 0x20) + { + /* T bit should be set */ + if (armv4_5_target->core_state == ARMV4_5_STATE_ARM) + { + /* change state to Thumb */ + LOG_DEBUG("changing to Thumb state"); + armv4_5_target->core_state = ARMV4_5_STATE_THUMB; + } + } + else + { + /* T bit should be cleared */ + if (armv4_5_target->core_state == ARMV4_5_STATE_THUMB) + { + /* change state to ARM */ + LOG_DEBUG("changing to ARM state"); + armv4_5_target->core_state = ARMV4_5_STATE_ARM; + } + } + + if (armv4_5_target->core_mode != (value & 0x1f)) + { + LOG_DEBUG("changing ARM core mode to '%s'", armv4_5_mode_strings[armv4_5_mode_to_number(value & 0x1f)]); + armv4_5_target->core_mode = value & 0x1f; + armv4_5_target->write_core_reg(target, 16, ARMV4_5_MODE_ANY, value); + } + } + buf_set_u32(reg->value, 0, 32, value); reg->dirty = 1; reg->valid = 1; @@ -259,7 +292,7 @@ reg_cache_t* armv4_5_build_reg_cache(target_t *target, armv4_5_common_t *armv4_5 int num_regs = 37; reg_cache_t *cache = malloc(sizeof(reg_cache_t)); reg_t *reg_list = malloc(sizeof(reg_t) * num_regs); - armv4_5_core_reg_t *arch_info = malloc(sizeof(reg_t) * num_regs); + armv4_5_core_reg_t *arch_info = malloc(sizeof(armv4_5_core_reg_t) * num_regs); int i; cache->name = "arm v4/5 registers"; @@ -289,18 +322,17 @@ reg_cache_t* armv4_5_build_reg_cache(target_t *target, armv4_5_common_t *armv4_5 return cache; } -int armv4_5_arch_state(struct target_s *target, char *buf, int buf_size) +int armv4_5_arch_state(struct target_s *target) { armv4_5_common_t *armv4_5 = target->arch_info; if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC) { - ERROR("BUG: called for a non-ARMv4/5 target"); + LOG_ERROR("BUG: called for a non-ARMv4/5 target"); exit(-1); } - snprintf(buf, buf_size, - "target halted in %s state due to %s, current mode: %s\ncpsr: 0x%8.8x pc: 0x%8.8x", + LOG_USER("target halted in %s state due to %s, current mode: %s\ncpsr: 0x%8.8x pc: 0x%8.8x", armv4_5_state_strings[armv4_5->core_state], target_debug_reason_strings[target->debug_reason], armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)], @@ -392,7 +424,7 @@ int handle_armv4_5_disassemble_command(struct command_context_s *cmd_ctx, char * int i; arm_instruction_t cur_instruction; u32 opcode; - int thumb; + int thumb = 0; if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC) { @@ -415,8 +447,8 @@ int handle_armv4_5_disassemble_command(struct command_context_s *cmd_ctx, char * for (i = 0; i < count; i++) { - target->type->read_memory(target, address, 4, 1, (u8*)&opcode); - evaluate_opcode(opcode, address, &cur_instruction); + target_read_u32(target, address, &opcode); + arm_evaluate_opcode(opcode, address, &cur_instruction); command_print(cmd_ctx, "%s", cur_instruction.text); address += (thumb) ? 2 : 4; } @@ -428,7 +460,7 @@ int armv4_5_register_commands(struct command_context_s *cmd_ctx) { command_t *armv4_5_cmd; - armv4_5_cmd = register_command(cmd_ctx, NULL, "armv4_5", NULL, COMMAND_ANY, NULL); + armv4_5_cmd = register_command(cmd_ctx, NULL, "armv4_5", NULL, COMMAND_ANY, "armv4/5 specific commands"); register_command(cmd_ctx, armv4_5_cmd, "reg", handle_armv4_5_reg_command, COMMAND_EXEC, "display ARM core registers"); register_command(cmd_ctx, armv4_5_cmd, "core_state", handle_armv4_5_core_state_command, COMMAND_EXEC, "display/change ARM core state "); @@ -442,11 +474,6 @@ int armv4_5_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list armv4_5_common_t *armv4_5 = target->arch_info; int i; - if (target->state != TARGET_HALTED) - { - return ERROR_TARGET_NOT_HALTED; - } - *reg_list_size = 26; *reg_list = malloc(sizeof(reg_t*) * (*reg_list_size)); @@ -477,16 +504,17 @@ int armv4_5_run_algorithm(struct target_s *target, int num_mem_params, mem_param int exit_breakpoint_size = 0; int i; int retval = ERROR_OK; + LOG_DEBUG("Running algorithm"); if (armv4_5_algorithm_info->common_magic != ARMV4_5_COMMON_MAGIC) { - ERROR("current target isn't an ARMV4/5 target"); + LOG_ERROR("current target isn't an ARMV4/5 target"); return ERROR_TARGET_INVALID; } if (target->state != TARGET_HALTED) { - WARNING("target not halted"); + LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -508,17 +536,17 @@ int armv4_5_run_algorithm(struct target_s *target, int num_mem_params, mem_param reg_t *reg = register_get_by_name(armv4_5->core_cache, reg_params[i].reg_name, 0); if (!reg) { - ERROR("BUG: register '%s' not found", reg_params[i].reg_name); + LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name); exit(-1); } if (reg->size != reg_params[i].size) { - ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name); + LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name); exit(-1); } - armv4_5_set_core_reg(reg, buf_get_u32(reg_params[i].value, 0, 32)); + armv4_5_set_core_reg(reg, reg_params[i].value); } armv4_5->core_state = armv4_5_algorithm_info->core_state; @@ -528,13 +556,13 @@ int armv4_5_run_algorithm(struct target_s *target, int num_mem_params, mem_param exit_breakpoint_size = 2; else { - ERROR("BUG: can't execute algorithms when not in ARM or Thumb state"); + LOG_ERROR("BUG: can't execute algorithms when not in ARM or Thumb state"); exit(-1); } if (armv4_5_algorithm_info->core_mode != ARMV4_5_MODE_ANY) { - DEBUG("setting core_mode: 0x%2.2x", armv4_5_algorithm_info->core_mode); + LOG_DEBUG("setting core_mode: 0x%2.2x", armv4_5_algorithm_info->core_mode); buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 5, armv4_5_algorithm_info->core_mode); armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1; armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1; @@ -542,7 +570,7 @@ int armv4_5_run_algorithm(struct target_s *target, int num_mem_params, mem_param if ((retval = breakpoint_add(target, exit_point, exit_breakpoint_size, BKPT_HARD)) != ERROR_OK) { - ERROR("can't add breakpoint to finish algorithm execution"); + LOG_ERROR("can't add breakpoint to finish algorithm execution"); return ERROR_TARGET_FAILURE; } @@ -555,7 +583,7 @@ int armv4_5_run_algorithm(struct target_s *target, int num_mem_params, mem_param target->type->poll(target); if ((timeout_ms -= 10) <= 0) { - ERROR("timeout waiting for algorithm to complete, trying to halt target"); + LOG_ERROR("timeout waiting for algorithm to complete, trying to halt target"); target->type->halt(target); timeout_ms = 1000; while (target->state != TARGET_HALTED) @@ -564,7 +592,7 @@ int armv4_5_run_algorithm(struct target_s *target, int num_mem_params, mem_param target->type->poll(target); if ((timeout_ms -= 10) <= 0) { - ERROR("target didn't reenter debug state, exiting"); + LOG_ERROR("target didn't reenter debug state, exiting"); exit(-1); } } @@ -572,6 +600,13 @@ int armv4_5_run_algorithm(struct target_s *target, int num_mem_params, mem_param } } + if ((retval != ERROR_TARGET_TIMEOUT) && + (buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32) != exit_point)) + { + LOG_WARNING("target reentered debug state, but not at the desired exit point: 0x%4.4x", + buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)); + } + breakpoint_remove(target, exit_point); for (i = 0; i < num_mem_params; i++) @@ -588,13 +623,13 @@ int armv4_5_run_algorithm(struct target_s *target, int num_mem_params, mem_param reg_t *reg = register_get_by_name(armv4_5->core_cache, reg_params[i].reg_name, 0); if (!reg) { - ERROR("BUG: register '%s' not found", reg_params[i].reg_name); + LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name); exit(-1); } if (reg->size != reg_params[i].size) { - ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name); + LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name); exit(-1); } @@ -604,7 +639,7 @@ int armv4_5_run_algorithm(struct target_s *target, int num_mem_params, mem_param for (i = 0; i <= 16; i++) { - DEBUG("restoring register %s with value 0x%8.8x", ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).name, buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).value, 0, 32)); + LOG_DEBUG("restoring register %s with value 0x%8.8x", ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).name, context[i]); buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).value, 0, 32, context[i]); ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).valid = 1; ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).dirty = 1;