X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Farmv4_5.c;h=102913b560f9d7ea143df75617301be865c3376a;hb=56e01714203406b50b40dd7738983e3b019d4df2;hp=7e5bb0a1716123d703bea9235c2ec80ba358ee72;hpb=66ee303456910f684244a20a0ac2e958d40b78cb;p=openocd.git diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c index 7e5bb0a171..102913b560 100644 --- a/src/target/armv4_5.c +++ b/src/target/armv4_5.c @@ -31,7 +31,7 @@ #include "arm_jtag.h" #include "breakpoints.h" #include "arm_disassembler.h" -#include "binarybuffer.h" +#include #include "algorithm.h" #include "register.h" @@ -89,43 +89,43 @@ static const struct { */ { .name = "User", - .psr = ARMV4_5_MODE_USR, + .psr = ARM_MODE_USR, .n_indices = ARRAY_SIZE(arm_usr_indices), .indices = arm_usr_indices, }, { .name = "FIQ", - .psr = ARMV4_5_MODE_FIQ, + .psr = ARM_MODE_FIQ, .n_indices = ARRAY_SIZE(arm_fiq_indices), .indices = arm_fiq_indices, }, { .name = "Supervisor", - .psr = ARMV4_5_MODE_SVC, + .psr = ARM_MODE_SVC, .n_indices = ARRAY_SIZE(arm_svc_indices), .indices = arm_svc_indices, }, { .name = "Abort", - .psr = ARMV4_5_MODE_ABT, + .psr = ARM_MODE_ABT, .n_indices = ARRAY_SIZE(arm_abt_indices), .indices = arm_abt_indices, }, { .name = "IRQ", - .psr = ARMV4_5_MODE_IRQ, + .psr = ARM_MODE_IRQ, .n_indices = ARRAY_SIZE(arm_irq_indices), .indices = arm_irq_indices, }, { .name = "Undefined instruction", - .psr = ARMV4_5_MODE_UND, + .psr = ARM_MODE_UND, .n_indices = ARRAY_SIZE(arm_und_indices), .indices = arm_und_indices, }, { .name = "System", - .psr = ARMV4_5_MODE_SYS, + .psr = ARM_MODE_SYS, .n_indices = ARRAY_SIZE(arm_usr_indices), .indices = arm_usr_indices, }, @@ -163,24 +163,24 @@ bool is_arm_mode(unsigned psr_mode) } /** Map PSR mode bits to linear number indexing armv4_5_core_reg_map */ -int armv4_5_mode_to_number(enum armv4_5_mode mode) +int arm_mode_to_number(enum arm_mode mode) { switch (mode) { - case ARMV4_5_MODE_ANY: + case ARM_MODE_ANY: /* map MODE_ANY to user mode */ - case ARMV4_5_MODE_USR: + case ARM_MODE_USR: return 0; - case ARMV4_5_MODE_FIQ: + case ARM_MODE_FIQ: return 1; - case ARMV4_5_MODE_IRQ: + case ARM_MODE_IRQ: return 2; - case ARMV4_5_MODE_SVC: + case ARM_MODE_SVC: return 3; - case ARMV4_5_MODE_ABT: + case ARM_MODE_ABT: return 4; - case ARMV4_5_MODE_UND: + case ARM_MODE_UND: return 5; - case ARMV4_5_MODE_SYS: + case ARM_MODE_SYS: return 6; case ARM_MODE_MON: return 7; @@ -191,32 +191,32 @@ int armv4_5_mode_to_number(enum armv4_5_mode mode) } /** Map linear number indexing armv4_5_core_reg_map to PSR mode bits. */ -enum armv4_5_mode armv4_5_number_to_mode(int number) +enum arm_mode armv4_5_number_to_mode(int number) { switch (number) { case 0: - return ARMV4_5_MODE_USR; + return ARM_MODE_USR; case 1: - return ARMV4_5_MODE_FIQ; + return ARM_MODE_FIQ; case 2: - return ARMV4_5_MODE_IRQ; + return ARM_MODE_IRQ; case 3: - return ARMV4_5_MODE_SVC; + return ARM_MODE_SVC; case 4: - return ARMV4_5_MODE_ABT; + return ARM_MODE_ABT; case 5: - return ARMV4_5_MODE_UND; + return ARM_MODE_UND; case 6: - return ARMV4_5_MODE_SYS; + return ARM_MODE_SYS; case 7: return ARM_MODE_MON; default: LOG_ERROR("mode index out of bounds %d", number); - return ARMV4_5_MODE_ANY; + return ARM_MODE_ANY; } } -char* armv4_5_state_strings[] = +const char *arm_state_strings[] = { "ARM", "Thumb", "Jazelle", "ThumbEE", }; @@ -243,68 +243,68 @@ static const struct { * (Exception modes have both CPSR and SPSR registers ...) */ unsigned cookie; - enum armv4_5_mode mode; + enum arm_mode mode; } arm_core_regs[] = { /* IMPORTANT: we guarantee that the first eight cached registers * correspond to r0..r7, and the fifteenth to PC, so that callers * don't need to map them. */ - { .name = "r0", .cookie = 0, .mode = ARMV4_5_MODE_ANY, }, - { .name = "r1", .cookie = 1, .mode = ARMV4_5_MODE_ANY, }, - { .name = "r2", .cookie = 2, .mode = ARMV4_5_MODE_ANY, }, - { .name = "r3", .cookie = 3, .mode = ARMV4_5_MODE_ANY, }, - { .name = "r4", .cookie = 4, .mode = ARMV4_5_MODE_ANY, }, - { .name = "r5", .cookie = 5, .mode = ARMV4_5_MODE_ANY, }, - { .name = "r6", .cookie = 6, .mode = ARMV4_5_MODE_ANY, }, - { .name = "r7", .cookie = 7, .mode = ARMV4_5_MODE_ANY, }, + { .name = "r0", .cookie = 0, .mode = ARM_MODE_ANY, }, + { .name = "r1", .cookie = 1, .mode = ARM_MODE_ANY, }, + { .name = "r2", .cookie = 2, .mode = ARM_MODE_ANY, }, + { .name = "r3", .cookie = 3, .mode = ARM_MODE_ANY, }, + { .name = "r4", .cookie = 4, .mode = ARM_MODE_ANY, }, + { .name = "r5", .cookie = 5, .mode = ARM_MODE_ANY, }, + { .name = "r6", .cookie = 6, .mode = ARM_MODE_ANY, }, + { .name = "r7", .cookie = 7, .mode = ARM_MODE_ANY, }, /* NOTE: regs 8..12 might be shadowed by FIQ ... flagging * them as MODE_ANY creates special cases. (ANY means * "not mapped" elsewhere; here it's "everything but FIQ".) */ - { .name = "r8", .cookie = 8, .mode = ARMV4_5_MODE_ANY, }, - { .name = "r9", .cookie = 9, .mode = ARMV4_5_MODE_ANY, }, - { .name = "r10", .cookie = 10, .mode = ARMV4_5_MODE_ANY, }, - { .name = "r11", .cookie = 11, .mode = ARMV4_5_MODE_ANY, }, - { .name = "r12", .cookie = 12, .mode = ARMV4_5_MODE_ANY, }, + { .name = "r8", .cookie = 8, .mode = ARM_MODE_ANY, }, + { .name = "r9", .cookie = 9, .mode = ARM_MODE_ANY, }, + { .name = "r10", .cookie = 10, .mode = ARM_MODE_ANY, }, + { .name = "r11", .cookie = 11, .mode = ARM_MODE_ANY, }, + { .name = "r12", .cookie = 12, .mode = ARM_MODE_ANY, }, /* NOTE all MODE_USR registers are equivalent to MODE_SYS ones */ - { .name = "sp_usr", .cookie = 13, .mode = ARMV4_5_MODE_USR, }, - { .name = "lr_usr", .cookie = 14, .mode = ARMV4_5_MODE_USR, }, + { .name = "sp_usr", .cookie = 13, .mode = ARM_MODE_USR, }, + { .name = "lr_usr", .cookie = 14, .mode = ARM_MODE_USR, }, /* guaranteed to be at index 15 */ - { .name = "pc", .cookie = 15, .mode = ARMV4_5_MODE_ANY, }, + { .name = "pc", .cookie = 15, .mode = ARM_MODE_ANY, }, - { .name = "r8_fiq", .cookie = 8, .mode = ARMV4_5_MODE_FIQ, }, - { .name = "r9_fiq", .cookie = 9, .mode = ARMV4_5_MODE_FIQ, }, - { .name = "r10_fiq", .cookie = 10, .mode = ARMV4_5_MODE_FIQ, }, - { .name = "r11_fiq", .cookie = 11, .mode = ARMV4_5_MODE_FIQ, }, - { .name = "r12_fiq", .cookie = 12, .mode = ARMV4_5_MODE_FIQ, }, + { .name = "r8_fiq", .cookie = 8, .mode = ARM_MODE_FIQ, }, + { .name = "r9_fiq", .cookie = 9, .mode = ARM_MODE_FIQ, }, + { .name = "r10_fiq", .cookie = 10, .mode = ARM_MODE_FIQ, }, + { .name = "r11_fiq", .cookie = 11, .mode = ARM_MODE_FIQ, }, + { .name = "r12_fiq", .cookie = 12, .mode = ARM_MODE_FIQ, }, - { .name = "lr_fiq", .cookie = 13, .mode = ARMV4_5_MODE_FIQ, }, - { .name = "sp_fiq", .cookie = 14, .mode = ARMV4_5_MODE_FIQ, }, + { .name = "sp_fiq", .cookie = 13, .mode = ARM_MODE_FIQ, }, + { .name = "lr_fiq", .cookie = 14, .mode = ARM_MODE_FIQ, }, - { .name = "lr_irq", .cookie = 13, .mode = ARMV4_5_MODE_IRQ, }, - { .name = "sp_irq", .cookie = 14, .mode = ARMV4_5_MODE_IRQ, }, + { .name = "sp_irq", .cookie = 13, .mode = ARM_MODE_IRQ, }, + { .name = "lr_irq", .cookie = 14, .mode = ARM_MODE_IRQ, }, - { .name = "lr_svc", .cookie = 13, .mode = ARMV4_5_MODE_SVC, }, - { .name = "sp_svc", .cookie = 14, .mode = ARMV4_5_MODE_SVC, }, + { .name = "sp_svc", .cookie = 13, .mode = ARM_MODE_SVC, }, + { .name = "lr_svc", .cookie = 14, .mode = ARM_MODE_SVC, }, - { .name = "lr_abt", .cookie = 13, .mode = ARMV4_5_MODE_ABT, }, - { .name = "sp_abt", .cookie = 14, .mode = ARMV4_5_MODE_ABT, }, + { .name = "sp_abt", .cookie = 13, .mode = ARM_MODE_ABT, }, + { .name = "lr_abt", .cookie = 14, .mode = ARM_MODE_ABT, }, - { .name = "lr_und", .cookie = 13, .mode = ARMV4_5_MODE_UND, }, - { .name = "sp_und", .cookie = 14, .mode = ARMV4_5_MODE_UND, }, + { .name = "sp_und", .cookie = 13, .mode = ARM_MODE_UND, }, + { .name = "lr_und", .cookie = 14, .mode = ARM_MODE_UND, }, - { .name = "cpsr", .cookie = 16, .mode = ARMV4_5_MODE_ANY, }, - { .name = "spsr_fiq", .cookie = 16, .mode = ARMV4_5_MODE_FIQ, }, - { .name = "spsr_irq", .cookie = 16, .mode = ARMV4_5_MODE_IRQ, }, - { .name = "spsr_svc", .cookie = 16, .mode = ARMV4_5_MODE_SVC, }, - { .name = "spsr_abt", .cookie = 16, .mode = ARMV4_5_MODE_ABT, }, - { .name = "spsr_und", .cookie = 16, .mode = ARMV4_5_MODE_UND, }, + { .name = "cpsr", .cookie = 16, .mode = ARM_MODE_ANY, }, + { .name = "spsr_fiq", .cookie = 16, .mode = ARM_MODE_FIQ, }, + { .name = "spsr_irq", .cookie = 16, .mode = ARM_MODE_IRQ, }, + { .name = "spsr_svc", .cookie = 16, .mode = ARM_MODE_SVC, }, + { .name = "spsr_abt", .cookie = 16, .mode = ARM_MODE_ABT, }, + { .name = "spsr_und", .cookie = 16, .mode = ARM_MODE_UND, }, - { .name = "lr_mon", .cookie = 13, .mode = ARM_MODE_MON, }, - { .name = "sp_mon", .cookie = 14, .mode = ARM_MODE_MON, }, + { .name = "sp_mon", .cookie = 13, .mode = ARM_MODE_MON, }, + { .name = "lr_mon", .cookie = 14, .mode = ARM_MODE_MON, }, { .name = "spsr_mon", .cookie = 16, .mode = ARM_MODE_MON, }, }; @@ -346,7 +346,7 @@ const int armv4_5_core_reg_map[8][17] = */ void arm_set_cpsr(struct arm *arm, uint32_t cpsr) { - enum armv4_5_mode mode = cpsr & 0x1f; + enum arm_mode mode = cpsr & 0x1f; int num; /* NOTE: this may be called very early, before the register @@ -362,34 +362,38 @@ void arm_set_cpsr(struct arm *arm, uint32_t cpsr) arm->core_mode = mode; /* mode_to_number() warned; set up a somewhat-sane mapping */ - num = armv4_5_mode_to_number(mode); + num = arm_mode_to_number(mode); if (num < 0) { - mode = ARMV4_5_MODE_USR; + mode = ARM_MODE_USR; num = 0; } arm->map = &armv4_5_core_reg_map[num][0]; - arm->spsr = (mode == ARMV4_5_MODE_USR || mode == ARMV4_5_MODE_SYS) + arm->spsr = (mode == ARM_MODE_USR || mode == ARM_MODE_SYS) ? NULL : arm->core_cache->reg_list + arm->map[16]; /* Older ARMs won't have the J bit */ - enum armv4_5_state state; + enum arm_state state; if (cpsr & (1 << 5)) { /* T */ if (cpsr & (1 << 24)) { /* J */ LOG_WARNING("ThumbEE -- incomplete support"); state = ARM_STATE_THUMB_EE; } else - state = ARMV4_5_STATE_THUMB; + state = ARM_STATE_THUMB; } else { if (cpsr & (1 << 24)) { /* J */ LOG_ERROR("Jazelle state handling is BROKEN!"); - state = ARMV4_5_STATE_JAZELLE; + state = ARM_STATE_JAZELLE; } else - state = ARMV4_5_STATE_ARM; + state = ARM_STATE_ARM; } arm->core_state = state; + + LOG_DEBUG("set CPSR %#8.8x: %s mode, %s state", (unsigned) cpsr, + arm_mode_name(mode), + arm_state_strings[arm->core_state]); } /** @@ -508,12 +512,12 @@ static int armv4_5_set_core_reg(struct reg *reg, uint8_t *buf) * it won't hurt since CPSR is always flushed anyway. */ if (armv4_5_target->core_mode != - (enum armv4_5_mode)(value & 0x1f)) { + (enum arm_mode)(value & 0x1f)) { LOG_DEBUG("changing ARM core mode to '%s'", arm_mode_name(value & 0x1f)); value &= ~((1 << 24) | (1 << 5)); armv4_5_target->write_core_reg(target, reg, - 16, ARMV4_5_MODE_ANY, value); + 16, ARM_MODE_ANY, value); } } else { buf_set_u32(reg->value, 0, 32, value); @@ -583,16 +587,20 @@ int armv4_5_arch_state(struct target *target) if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC) { - LOG_ERROR("BUG: called for a non-ARMv4/5 target"); + LOG_ERROR("BUG: called for a non-ARM target"); return ERROR_FAIL; } - LOG_USER("target halted in %s state due to %s, current mode: %s\ncpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "", - armv4_5_state_strings[armv4_5->core_state], - Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name, + LOG_USER("target halted in %s state due to %s, current mode: %s\n" + "cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "%s", + arm_state_strings[armv4_5->core_state], + Jim_Nvp_value2name_simple(nvp_target_debug_reason, + target->debug_reason)->name, arm_mode_name(armv4_5->core_mode), buf_get_u32(armv4_5->cpsr->value, 0, 32), - buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)); + buf_get_u32(armv4_5->core_cache->reg_list[15].value, + 0, 32), + armv4_5->is_semihosting ? ", semihosting" : ""); return ERROR_OK; } @@ -638,9 +646,9 @@ COMMAND_HANDLER(handle_armv4_5_reg_command) /* label this bank of registers (or shadows) */ switch (arm_mode_data[mode].psr) { - case ARMV4_5_MODE_SYS: + case ARM_MODE_SYS: continue; - case ARMV4_5_MODE_USR: + case ARM_MODE_USR: name = "System and User"; sep = ""; break; @@ -702,15 +710,15 @@ COMMAND_HANDLER(handle_armv4_5_core_state_command) { if (strcmp(CMD_ARGV[0], "arm") == 0) { - armv4_5->core_state = ARMV4_5_STATE_ARM; + armv4_5->core_state = ARM_STATE_ARM; } if (strcmp(CMD_ARGV[0], "thumb") == 0) { - armv4_5->core_state = ARMV4_5_STATE_THUMB; + armv4_5->core_state = ARM_STATE_THUMB; } } - command_print(CMD_CTX, "core state: %s", armv4_5_state_strings[armv4_5->core_state]); + command_print(CMD_CTX, "core state: %s", arm_state_strings[armv4_5->core_state]); return ERROR_OK; } @@ -786,6 +794,137 @@ usage: return retval; } +static int jim_mcrmrc(Jim_Interp *interp, int argc, Jim_Obj *const *argv) +{ + struct command_context *context; + struct target *target; + struct arm *arm; + int retval; + + context = Jim_GetAssocData(interp, "context"); + if (context == NULL) { + LOG_ERROR("%s: no command context", __func__); + return JIM_ERR; + } + target = get_current_target(context); + if (target == NULL) { + LOG_ERROR("%s: no current target", __func__); + return JIM_ERR; + } + if (!target_was_examined(target)) { + LOG_ERROR("%s: not yet examined", target_name(target)); + return JIM_ERR; + } + arm = target_to_arm(target); + if (!is_arm(arm)) { + LOG_ERROR("%s: not an ARM", target_name(target)); + return JIM_ERR; + } + + if ((argc < 6) || (argc > 7)) { + /* FIXME use the command name to verify # params... */ + LOG_ERROR("%s: wrong number of arguments", __func__); + return JIM_ERR; + } + + int cpnum; + uint32_t op1; + uint32_t op2; + uint32_t CRn; + uint32_t CRm; + uint32_t value; + long l; + + /* NOTE: parameter sequence matches ARM instruction set usage: + * MCR pNUM, op1, rX, CRn, CRm, op2 ; write CP from rX + * MRC pNUM, op1, rX, CRn, CRm, op2 ; read CP into rX + * The "rX" is necessarily omitted; it uses Tcl mechanisms. + */ + retval = Jim_GetLong(interp, argv[1], &l); + if (retval != JIM_OK) + return retval; + if (l & ~0xf) { + LOG_ERROR("%s: %s %d out of range", __func__, + "coprocessor", (int) l); + return JIM_ERR; + } + cpnum = l; + + retval = Jim_GetLong(interp, argv[2], &l); + if (retval != JIM_OK) + return retval; + if (l & ~0x7) { + LOG_ERROR("%s: %s %d out of range", __func__, + "op1", (int) l); + return JIM_ERR; + } + op1 = l; + + retval = Jim_GetLong(interp, argv[3], &l); + if (retval != JIM_OK) + return retval; + if (l & ~0xf) { + LOG_ERROR("%s: %s %d out of range", __func__, + "CRn", (int) l); + return JIM_ERR; + } + CRn = l; + + retval = Jim_GetLong(interp, argv[4], &l); + if (retval != JIM_OK) + return retval; + if (l & ~0xf) { + LOG_ERROR("%s: %s %d out of range", __func__, + "CRm", (int) l); + return JIM_ERR; + } + CRm = l; + + retval = Jim_GetLong(interp, argv[5], &l); + if (retval != JIM_OK) + return retval; + if (l & ~0x7) { + LOG_ERROR("%s: %s %d out of range", __func__, + "op2", (int) l); + return JIM_ERR; + } + op2 = l; + + value = 0; + + /* FIXME don't assume "mrc" vs "mcr" from the number of params; + * that could easily be a typo! Check both... + * + * FIXME change the call syntax here ... simplest to just pass + * the MRC() or MCR() instruction to be executed. That will also + * let us support the "mrc2" and "mcr2" opcodes (toggling one bit) + * if that's ever needed. + */ + if (argc == 7) { + retval = Jim_GetLong(interp, argv[6], &l); + if (retval != JIM_OK) { + return retval; + } + value = l; + + /* NOTE: parameters reordered! */ + // ARMV4_5_MCR(cpnum, op1, 0, CRn, CRm, op2) + retval = arm->mcr(target, cpnum, op1, op2, CRn, CRm, value); + if (retval != ERROR_OK) + return JIM_ERR; + } else { + /* NOTE: parameters reordered! */ + // ARMV4_5_MRC(cpnum, op1, 0, CRn, CRm, op2) + retval = arm->mrc(target, cpnum, op1, op2, CRn, CRm, &value); + if (retval != ERROR_OK) + return JIM_ERR; + + Jim_SetResult(interp, Jim_NewIntObj(interp, value)); + } + + return JIM_OK; +} + static const struct command_registration arm_exec_command_handlers[] = { { .name = "reg", @@ -807,6 +946,20 @@ static const struct command_registration arm_exec_command_handlers[] = { .usage = "
[ ['thumb']]", .help = "disassemble instructions ", }, + { + .name = "mcr", + .mode = COMMAND_EXEC, + .jim_handler = &jim_mcrmrc, + .help = "write coprocessor register", + .usage = "cpnum op1 CRn op2 CRm value", + }, + { + .name = "mrc", + .jim_handler = &jim_mcrmrc, + .help = "read coprocessor register", + .usage = "cpnum op1 CRn op2 CRm", + }, + COMMAND_REGISTRATION_DONE }; const struct command_registration arm_command_handlers[] = { @@ -875,16 +1028,23 @@ static int armv4_5_run_algorithm_completion(struct target *target, uint32_t exit return ERROR_OK; } -int armv4_5_run_algorithm_inner(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info, int (*run_it)(struct target *target, uint32_t exit_point, int timeout_ms, void *arch_info)) +int armv4_5_run_algorithm_inner(struct target *target, + int num_mem_params, struct mem_param *mem_params, + int num_reg_params, struct reg_param *reg_params, + uint32_t entry_point, uint32_t exit_point, + int timeout_ms, void *arch_info, + int (*run_it)(struct target *target, uint32_t exit_point, + int timeout_ms, void *arch_info)) { struct arm *armv4_5 = target_to_armv4_5(target); struct armv4_5_algorithm *armv4_5_algorithm_info = arch_info; - enum armv4_5_state core_state = armv4_5->core_state; + enum arm_state core_state = armv4_5->core_state; uint32_t context[17]; uint32_t cpsr; int exit_breakpoint_size = 0; int i; int retval = ERROR_OK; + LOG_DEBUG("Running algorithm"); if (armv4_5_algorithm_info->common_magic != ARMV4_5_COMMON_MAGIC) @@ -955,9 +1115,9 @@ int armv4_5_run_algorithm_inner(struct target *target, int num_mem_params, struc } armv4_5->core_state = armv4_5_algorithm_info->core_state; - if (armv4_5->core_state == ARMV4_5_STATE_ARM) + if (armv4_5->core_state == ARM_STATE_ARM) exit_breakpoint_size = 4; - else if (armv4_5->core_state == ARMV4_5_STATE_THUMB) + else if (armv4_5->core_state == ARM_STATE_THUMB) exit_breakpoint_size = 2; else { @@ -965,7 +1125,7 @@ int armv4_5_run_algorithm_inner(struct target *target, int num_mem_params, struc return ERROR_INVALID_ARGUMENTS; } - if (armv4_5_algorithm_info->core_mode != ARMV4_5_MODE_ANY) + if (armv4_5_algorithm_info->core_mode != ARM_MODE_ANY) { LOG_DEBUG("setting core_mode: 0x%2.2x", armv4_5_algorithm_info->core_mode); @@ -1114,8 +1274,8 @@ int arm_checksum_memory(struct target *target, } armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC; - armv4_5_info.core_mode = ARMV4_5_MODE_SVC; - armv4_5_info.core_state = ARMV4_5_STATE_ARM; + armv4_5_info.core_mode = ARM_MODE_SVC; + armv4_5_info.core_state = ARM_STATE_ARM; init_reg_param(®_params[0], "r0", 32, PARAM_IN_OUT); init_reg_param(®_params[1], "r1", 32, PARAM_OUT); @@ -1191,8 +1351,8 @@ int arm_blank_check_memory(struct target *target, } armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC; - armv4_5_info.core_mode = ARMV4_5_MODE_SVC; - armv4_5_info.core_state = ARMV4_5_STATE_ARM; + armv4_5_info.core_mode = ARM_MODE_SVC; + armv4_5_info.core_state = ARM_STATE_ARM; init_reg_param(®_params[0], "r0", 32, PARAM_OUT); buf_set_u32(reg_params[0].value, 0, 32, address); @@ -1241,20 +1401,43 @@ static int arm_full_context(struct target *target) return retval; } +static int arm_default_mrc(struct target *target, int cpnum, + uint32_t op1, uint32_t op2, + uint32_t CRn, uint32_t CRm, + uint32_t *value) +{ + LOG_ERROR("%s doesn't implement MRC", target_type_name(target)); + return ERROR_FAIL; +} + +static int arm_default_mcr(struct target *target, int cpnum, + uint32_t op1, uint32_t op2, + uint32_t CRn, uint32_t CRm, + uint32_t value) +{ + LOG_ERROR("%s doesn't implement MCR", target_type_name(target)); + return ERROR_FAIL; +} + int armv4_5_init_arch_info(struct target *target, struct arm *armv4_5) { target->arch_info = armv4_5; armv4_5->target = target; armv4_5->common_magic = ARMV4_5_COMMON_MAGIC; - arm_set_cpsr(armv4_5, ARMV4_5_MODE_USR); + arm_set_cpsr(armv4_5, ARM_MODE_USR); /* core_type may be overridden by subtype logic */ - armv4_5->core_type = ARMV4_5_MODE_ANY; + armv4_5->core_type = ARM_MODE_ANY; /* default full_context() has no core-specific optimizations */ if (!armv4_5->full_context && armv4_5->read_core_reg) armv4_5->full_context = arm_full_context; + if (!armv4_5->mrc) + armv4_5->mrc = arm_default_mrc; + if (!armv4_5->mcr) + armv4_5->mcr = arm_default_mcr; + return ERROR_OK; }