X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Farmv4_5.c;h=69674cbf1e319be71e24fefff161c4f32f2d86c2;hb=b2dc1af59a4cead2bd9446256ef31658b2a5de61;hp=ac7f6236ed5824ca578783349bf2b021efc88625;hpb=4617cd0f911d64a460d99d25c531ddc55f2452ca;p=openocd.git diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c index ac7f6236ed..69674cbf1e 100644 --- a/src/target/armv4_5.c +++ b/src/target/armv4_5.c @@ -21,8 +21,9 @@ * You should have received a copy of the GNU General Public License * * along with this program; if not, write to the * * Free Software Foundation, Inc., * - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * ***************************************************************************/ + #ifdef HAVE_CONFIG_H #include "config.h" #endif @@ -36,16 +37,15 @@ #include "algorithm.h" #include "register.h" - /* offsets into armv4_5 core register cache */ enum { -// ARMV4_5_CPSR = 31, +/* ARMV4_5_CPSR = 31, */ ARMV4_5_SPSR_FIQ = 32, ARMV4_5_SPSR_IRQ = 33, ARMV4_5_SPSR_SVC = 34, ARMV4_5_SPSR_ABT = 35, ARMV4_5_SPSR_UND = 36, - ARM_SPSR_MON = 39, + ARM_SPSR_MON = 41, }; static const uint8_t arm_usr_indices[17] = { @@ -73,7 +73,7 @@ static const uint8_t arm_und_indices[3] = { }; static const uint8_t arm_mon_indices[3] = { - 37, 38, ARM_SPSR_MON, + 39, 40, ARM_SPSR_MON, }; static const struct { @@ -140,6 +140,21 @@ static const struct { .n_indices = ARRAY_SIZE(arm_mon_indices), .indices = arm_mon_indices, }, + + /* These special modes are currently only supported + * by ARMv6M and ARMv7M profiles */ + { + .name = "Thread", + .psr = ARM_MODE_THREAD, + }, + { + .name = "Thread (User)", + .psr = ARM_MODE_USER_THREAD, + }, + { + .name = "Handler", + .psr = ARM_MODE_HANDLER, + }, }; /** Map PSR mode bits to the name of an ARM processor operating mode. */ @@ -167,27 +182,27 @@ bool is_arm_mode(unsigned psr_mode) int arm_mode_to_number(enum arm_mode mode) { switch (mode) { - case ARM_MODE_ANY: + case ARM_MODE_ANY: /* map MODE_ANY to user mode */ - case ARM_MODE_USR: - return 0; - case ARM_MODE_FIQ: - return 1; - case ARM_MODE_IRQ: - return 2; - case ARM_MODE_SVC: - return 3; - case ARM_MODE_ABT: - return 4; - case ARM_MODE_UND: - return 5; - case ARM_MODE_SYS: - return 6; - case ARM_MODE_MON: - return 7; - default: - LOG_ERROR("invalid mode value encountered %d", mode); - return -1; + case ARM_MODE_USR: + return 0; + case ARM_MODE_FIQ: + return 1; + case ARM_MODE_IRQ: + return 2; + case ARM_MODE_SVC: + return 3; + case ARM_MODE_ABT: + return 4; + case ARM_MODE_UND: + return 5; + case ARM_MODE_SYS: + return 6; + case ARM_MODE_MON: + return 7; + default: + LOG_ERROR("invalid mode value encountered %d", mode); + return -1; } } @@ -195,30 +210,29 @@ int arm_mode_to_number(enum arm_mode mode) enum arm_mode armv4_5_number_to_mode(int number) { switch (number) { - case 0: - return ARM_MODE_USR; - case 1: - return ARM_MODE_FIQ; - case 2: - return ARM_MODE_IRQ; - case 3: - return ARM_MODE_SVC; - case 4: - return ARM_MODE_ABT; - case 5: - return ARM_MODE_UND; - case 6: - return ARM_MODE_SYS; - case 7: - return ARM_MODE_MON; - default: - LOG_ERROR("mode index out of bounds %d", number); - return ARM_MODE_ANY; + case 0: + return ARM_MODE_USR; + case 1: + return ARM_MODE_FIQ; + case 2: + return ARM_MODE_IRQ; + case 3: + return ARM_MODE_SVC; + case 4: + return ARM_MODE_ABT; + case 5: + return ARM_MODE_UND; + case 6: + return ARM_MODE_SYS; + case 7: + return ARM_MODE_MON; + default: + LOG_ERROR("mode index out of bounds %d", number); + return ARM_MODE_ANY; } } -static const char *arm_state_strings[] = -{ +static const char *arm_state_strings[] = { "ARM", "Thumb", "Jazelle", "ThumbEE", }; @@ -244,76 +258,87 @@ static const struct { * (Exception modes have both CPSR and SPSR registers ...) */ unsigned cookie; + unsigned gdb_index; enum arm_mode mode; } arm_core_regs[] = { /* IMPORTANT: we guarantee that the first eight cached registers * correspond to r0..r7, and the fifteenth to PC, so that callers * don't need to map them. */ - { .name = "r0", .cookie = 0, .mode = ARM_MODE_ANY, }, - { .name = "r1", .cookie = 1, .mode = ARM_MODE_ANY, }, - { .name = "r2", .cookie = 2, .mode = ARM_MODE_ANY, }, - { .name = "r3", .cookie = 3, .mode = ARM_MODE_ANY, }, - { .name = "r4", .cookie = 4, .mode = ARM_MODE_ANY, }, - { .name = "r5", .cookie = 5, .mode = ARM_MODE_ANY, }, - { .name = "r6", .cookie = 6, .mode = ARM_MODE_ANY, }, - { .name = "r7", .cookie = 7, .mode = ARM_MODE_ANY, }, + { .name = "r0", .cookie = 0, .mode = ARM_MODE_ANY, .gdb_index = 0, }, + { .name = "r1", .cookie = 1, .mode = ARM_MODE_ANY, .gdb_index = 1, }, + { .name = "r2", .cookie = 2, .mode = ARM_MODE_ANY, .gdb_index = 2, }, + { .name = "r3", .cookie = 3, .mode = ARM_MODE_ANY, .gdb_index = 3, }, + { .name = "r4", .cookie = 4, .mode = ARM_MODE_ANY, .gdb_index = 4, }, + { .name = "r5", .cookie = 5, .mode = ARM_MODE_ANY, .gdb_index = 5, }, + { .name = "r6", .cookie = 6, .mode = ARM_MODE_ANY, .gdb_index = 6, }, + { .name = "r7", .cookie = 7, .mode = ARM_MODE_ANY, .gdb_index = 7, }, /* NOTE: regs 8..12 might be shadowed by FIQ ... flagging * them as MODE_ANY creates special cases. (ANY means * "not mapped" elsewhere; here it's "everything but FIQ".) */ - { .name = "r8", .cookie = 8, .mode = ARM_MODE_ANY, }, - { .name = "r9", .cookie = 9, .mode = ARM_MODE_ANY, }, - { .name = "r10", .cookie = 10, .mode = ARM_MODE_ANY, }, - { .name = "r11", .cookie = 11, .mode = ARM_MODE_ANY, }, - { .name = "r12", .cookie = 12, .mode = ARM_MODE_ANY, }, + { .name = "r8", .cookie = 8, .mode = ARM_MODE_ANY, .gdb_index = 8, }, + { .name = "r9", .cookie = 9, .mode = ARM_MODE_ANY, .gdb_index = 9, }, + { .name = "r10", .cookie = 10, .mode = ARM_MODE_ANY, .gdb_index = 10, }, + { .name = "r11", .cookie = 11, .mode = ARM_MODE_ANY, .gdb_index = 11, }, + { .name = "r12", .cookie = 12, .mode = ARM_MODE_ANY, .gdb_index = 12, }, + + /* Historical GDB mapping of indices: + * - 13-14 are sp and lr, but banked counterparts are used + * - 16-24 are left for deprecated 8 FPA + 1 FPS + * - 25 is the cpsr + */ /* NOTE all MODE_USR registers are equivalent to MODE_SYS ones */ - { .name = "sp_usr", .cookie = 13, .mode = ARM_MODE_USR, }, - { .name = "lr_usr", .cookie = 14, .mode = ARM_MODE_USR, }, + { .name = "sp_usr", .cookie = 13, .mode = ARM_MODE_USR, .gdb_index = 26, }, + { .name = "lr_usr", .cookie = 14, .mode = ARM_MODE_USR, .gdb_index = 27, }, /* guaranteed to be at index 15 */ - { .name = "pc", .cookie = 15, .mode = ARM_MODE_ANY, }, + { .name = "pc", .cookie = 15, .mode = ARM_MODE_ANY, .gdb_index = 15, }, + { .name = "r8_fiq", .cookie = 8, .mode = ARM_MODE_FIQ, .gdb_index = 28, }, + { .name = "r9_fiq", .cookie = 9, .mode = ARM_MODE_FIQ, .gdb_index = 29, }, + { .name = "r10_fiq", .cookie = 10, .mode = ARM_MODE_FIQ, .gdb_index = 30, }, + { .name = "r11_fiq", .cookie = 11, .mode = ARM_MODE_FIQ, .gdb_index = 31, }, + { .name = "r12_fiq", .cookie = 12, .mode = ARM_MODE_FIQ, .gdb_index = 32, }, + + { .name = "sp_fiq", .cookie = 13, .mode = ARM_MODE_FIQ, .gdb_index = 33, }, + { .name = "lr_fiq", .cookie = 14, .mode = ARM_MODE_FIQ, .gdb_index = 34, }, - { .name = "r8_fiq", .cookie = 8, .mode = ARM_MODE_FIQ, }, - { .name = "r9_fiq", .cookie = 9, .mode = ARM_MODE_FIQ, }, - { .name = "r10_fiq", .cookie = 10, .mode = ARM_MODE_FIQ, }, - { .name = "r11_fiq", .cookie = 11, .mode = ARM_MODE_FIQ, }, - { .name = "r12_fiq", .cookie = 12, .mode = ARM_MODE_FIQ, }, + { .name = "sp_irq", .cookie = 13, .mode = ARM_MODE_IRQ, .gdb_index = 35, }, + { .name = "lr_irq", .cookie = 14, .mode = ARM_MODE_IRQ, .gdb_index = 36, }, - { .name = "sp_fiq", .cookie = 13, .mode = ARM_MODE_FIQ, }, - { .name = "lr_fiq", .cookie = 14, .mode = ARM_MODE_FIQ, }, + { .name = "sp_svc", .cookie = 13, .mode = ARM_MODE_SVC, .gdb_index = 37, }, + { .name = "lr_svc", .cookie = 14, .mode = ARM_MODE_SVC, .gdb_index = 38, }, - { .name = "sp_irq", .cookie = 13, .mode = ARM_MODE_IRQ, }, - { .name = "lr_irq", .cookie = 14, .mode = ARM_MODE_IRQ, }, + { .name = "sp_abt", .cookie = 13, .mode = ARM_MODE_ABT, .gdb_index = 39, }, + { .name = "lr_abt", .cookie = 14, .mode = ARM_MODE_ABT, .gdb_index = 40, }, - { .name = "sp_svc", .cookie = 13, .mode = ARM_MODE_SVC, }, - { .name = "lr_svc", .cookie = 14, .mode = ARM_MODE_SVC, }, + { .name = "sp_und", .cookie = 13, .mode = ARM_MODE_UND, .gdb_index = 41, }, + { .name = "lr_und", .cookie = 14, .mode = ARM_MODE_UND, .gdb_index = 42, }, - { .name = "sp_abt", .cookie = 13, .mode = ARM_MODE_ABT, }, - { .name = "lr_abt", .cookie = 14, .mode = ARM_MODE_ABT, }, + { .name = "cpsr", .cookie = 16, .mode = ARM_MODE_ANY, .gdb_index = 25, }, + { .name = "spsr_fiq", .cookie = 16, .mode = ARM_MODE_FIQ, .gdb_index = 43, }, + { .name = "spsr_irq", .cookie = 16, .mode = ARM_MODE_IRQ, .gdb_index = 44, }, + { .name = "spsr_svc", .cookie = 16, .mode = ARM_MODE_SVC, .gdb_index = 45, }, + { .name = "spsr_abt", .cookie = 16, .mode = ARM_MODE_ABT, .gdb_index = 46, }, + { .name = "spsr_und", .cookie = 16, .mode = ARM_MODE_UND, .gdb_index = 47, }, - { .name = "sp_und", .cookie = 13, .mode = ARM_MODE_UND, }, - { .name = "lr_und", .cookie = 14, .mode = ARM_MODE_UND, }, + /* These are only used for GDB target description, banked registers are accessed instead */ + { .name = "sp", .cookie = 13, .mode = ARM_MODE_ANY, .gdb_index = 13, }, + { .name = "lr", .cookie = 14, .mode = ARM_MODE_ANY, .gdb_index = 14, }, - { .name = "cpsr", .cookie = 16, .mode = ARM_MODE_ANY, }, - { .name = "spsr_fiq", .cookie = 16, .mode = ARM_MODE_FIQ, }, - { .name = "spsr_irq", .cookie = 16, .mode = ARM_MODE_IRQ, }, - { .name = "spsr_svc", .cookie = 16, .mode = ARM_MODE_SVC, }, - { .name = "spsr_abt", .cookie = 16, .mode = ARM_MODE_ABT, }, - { .name = "spsr_und", .cookie = 16, .mode = ARM_MODE_UND, }, + /* These exist only when the Security Extension (TrustZone) is present */ + { .name = "sp_mon", .cookie = 13, .mode = ARM_MODE_MON, .gdb_index = 48, }, + { .name = "lr_mon", .cookie = 14, .mode = ARM_MODE_MON, .gdb_index = 49, }, + { .name = "spsr_mon", .cookie = 16, .mode = ARM_MODE_MON, .gdb_index = 50, }, - { .name = "sp_mon", .cookie = 13, .mode = ARM_MODE_MON, }, - { .name = "lr_mon", .cookie = 14, .mode = ARM_MODE_MON, }, - { .name = "spsr_mon", .cookie = 16, .mode = ARM_MODE_MON, }, }; /* map core mode (USR, FIQ, ...) and register number to * indices into the register cache */ -const int armv4_5_core_reg_map[8][17] = -{ +const int armv4_5_core_reg_map[8][17] = { { /* USR */ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 31 }, @@ -371,8 +396,8 @@ void arm_set_cpsr(struct arm *arm, uint32_t cpsr) arm->map = &armv4_5_core_reg_map[num][0]; arm->spsr = (mode == ARM_MODE_USR || mode == ARM_MODE_SYS) - ? NULL - : arm->core_cache->reg_list + arm->map[16]; + ? NULL + : arm->core_cache->reg_list + arm->map[16]; /* Older ARMs won't have the J bit */ enum arm_state state; @@ -393,8 +418,8 @@ void arm_set_cpsr(struct arm *arm, uint32_t cpsr) arm->core_state = state; LOG_DEBUG("set CPSR %#8.8x: %s mode, %s state", (unsigned) cpsr, - arm_mode_name(mode), - arm_state_strings[arm->core_state]); + arm_mode_name(mode), + arm_state_strings[arm->core_state]); } /** @@ -416,7 +441,11 @@ struct reg *arm_reg_current(struct arm *arm, unsigned regnum) if (regnum > 16) return NULL; - r = arm->core_cache->reg_list + arm->map[regnum]; + if (!arm->map) { + LOG_ERROR("Register map is not available yet, the target is not fully initialised"); + r = arm->core_cache->reg_list + regnum; + } else + r = arm->core_cache->reg_list + arm->map[regnum]; /* e.g. invalid CPSR said "secure monitor" mode on a core * that doesn't support it... @@ -431,18 +460,25 @@ struct reg *arm_reg_current(struct arm *arm, unsigned regnum) static const uint8_t arm_gdb_dummy_fp_value[12]; +static struct reg_feature arm_gdb_dummy_fp_features = { + .name = "net.sourceforge.openocd.fake_fpa" +}; + /** * Dummy FPA registers are required to support GDB on ARM. * Register packets require eight obsolete FPA register values. * Modern ARM cores use Vector Floating Point (VFP), if they * have any floating point support. VFP is not FPA-compatible. */ -struct reg arm_gdb_dummy_fp_reg = -{ +struct reg arm_gdb_dummy_fp_reg = { .name = "GDB dummy FPA register", .value = (uint8_t *) arm_gdb_dummy_fp_value, .valid = 1, .size = 96, + .exist = false, + .number = 16, + .feature = &arm_gdb_dummy_fp_features, + .group = "fake_fpa", }; static const uint8_t arm_gdb_dummy_fps_value[4]; @@ -451,12 +487,15 @@ static const uint8_t arm_gdb_dummy_fps_value[4]; * Dummy FPA status registers are required to support GDB on ARM. * Register packets require an obsolete FPA status register. */ -struct reg arm_gdb_dummy_fps_reg = -{ +struct reg arm_gdb_dummy_fps_reg = { .name = "GDB dummy FPA status register", .value = (uint8_t *) arm_gdb_dummy_fps_value, .valid = 1, .size = 32, + .exist = false, + .number = 24, + .feature = &arm_gdb_dummy_fp_features, + .group = "fake_fpa", }; static void arm_gdb_dummy_init(void) __attribute__ ((constructor)); @@ -470,16 +509,16 @@ static void arm_gdb_dummy_init(void) static int armv4_5_get_core_reg(struct reg *reg) { int retval; - struct arm_reg *armv4_5 = reg->arch_info; - struct target *target = armv4_5->target; + struct arm_reg *reg_arch_info = reg->arch_info; + struct target *target = reg_arch_info->target; - if (target->state != TARGET_HALTED) - { + if (target->state != TARGET_HALTED) { LOG_ERROR("Target not halted"); return ERROR_TARGET_NOT_HALTED; } - retval = armv4_5->armv4_5_common->read_core_reg(target, reg, armv4_5->num, armv4_5->mode); + retval = reg_arch_info->arm->read_core_reg(target, reg, + reg_arch_info->num, reg_arch_info->mode); if (retval == ERROR_OK) { reg->valid = 1; reg->dirty = 0; @@ -490,13 +529,12 @@ static int armv4_5_get_core_reg(struct reg *reg) static int armv4_5_set_core_reg(struct reg *reg, uint8_t *buf) { - struct arm_reg *armv4_5 = reg->arch_info; - struct target *target = armv4_5->target; + struct arm_reg *reg_arch_info = reg->arch_info; + struct target *target = reg_arch_info->target; struct arm *armv4_5_target = target_to_arm(target); uint32_t value = buf_get_u32(buf, 0, 32); - if (target->state != TARGET_HALTED) - { + if (target->state != TARGET_HALTED) { LOG_ERROR("Target not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -513,12 +551,12 @@ static int armv4_5_set_core_reg(struct reg *reg, uint8_t *buf) * it won't hurt since CPSR is always flushed anyway. */ if (armv4_5_target->core_mode != - (enum arm_mode)(value & 0x1f)) { + (enum arm_mode)(value & 0x1f)) { LOG_DEBUG("changing ARM core mode to '%s'", - arm_mode_name(value & 0x1f)); + arm_mode_name(value & 0x1f)); value &= ~((1 << 24) | (1 << 5)); armv4_5_target->write_core_reg(target, reg, - 16, ARM_MODE_ANY, value); + 16, ARM_MODE_ANY, value); } } else { buf_set_u32(reg->value, 0, 32, value); @@ -539,13 +577,13 @@ struct reg_cache *arm_build_reg_cache(struct target *target, struct arm *arm) int num_regs = ARRAY_SIZE(arm_core_regs); struct reg_cache *cache = malloc(sizeof(struct reg_cache)); struct reg *reg_list = calloc(num_regs, sizeof(struct reg)); - struct arm_reg *arch_info = calloc(num_regs, sizeof(struct arm_reg)); + struct arm_reg *reg_arch_info = calloc(num_regs, sizeof(struct arm_reg)); int i; - if (!cache || !reg_list || !arch_info) { + if (!cache || !reg_list || !reg_arch_info) { free(cache); free(reg_list); - free(arch_info); + free(reg_arch_info); return NULL; } @@ -554,25 +592,54 @@ struct reg_cache *arm_build_reg_cache(struct target *target, struct arm *arm) cache->reg_list = reg_list; cache->num_regs = 0; - for (i = 0; i < num_regs; i++) - { + for (i = 0; i < num_regs; i++) { /* Skip registers this core doesn't expose */ if (arm_core_regs[i].mode == ARM_MODE_MON - && arm->core_type != ARM_MODE_MON) + && arm->core_type != ARM_MODE_MON) continue; /* REVISIT handle Cortex-M, which only shadows R13/SP */ - arch_info[i].num = arm_core_regs[i].cookie; - arch_info[i].mode = arm_core_regs[i].mode; - arch_info[i].target = target; - arch_info[i].armv4_5_common = arm; + reg_arch_info[i].num = arm_core_regs[i].cookie; + reg_arch_info[i].mode = arm_core_regs[i].mode; + reg_arch_info[i].target = target; + reg_arch_info[i].arm = arm; - reg_list[i].name = (char *) arm_core_regs[i].name; + reg_list[i].name = arm_core_regs[i].name; + reg_list[i].number = arm_core_regs[i].gdb_index; reg_list[i].size = 32; - reg_list[i].value = &arch_info[i].value; + reg_list[i].value = reg_arch_info[i].value; reg_list[i].type = &arm_reg_type; - reg_list[i].arch_info = &arch_info[i]; + reg_list[i].arch_info = ®_arch_info[i]; + reg_list[i].exist = true; + + /* This really depends on the calling convention in use */ + reg_list[i].caller_save = false; + + /* Registers data type, as used by GDB target description */ + reg_list[i].reg_data_type = malloc(sizeof(struct reg_data_type)); + switch (arm_core_regs[i].cookie) { + case 13: + reg_list[i].reg_data_type->type = REG_TYPE_DATA_PTR; + break; + case 14: + case 15: + reg_list[i].reg_data_type->type = REG_TYPE_CODE_PTR; + break; + default: + reg_list[i].reg_data_type->type = REG_TYPE_UINT32; + break; + } + + /* let GDB shows banked registers only in "info all-reg" */ + reg_list[i].feature = malloc(sizeof(struct reg_feature)); + if (reg_list[i].number <= 15 || reg_list[i].number == 25) { + reg_list[i].feature->name = "org.gnu.gdb.arm.core"; + reg_list[i].group = "general"; + } else { + reg_list[i].feature->name = "net.sourceforge.openocd.banked"; + reg_list[i].group = "banked"; + } cache->num_regs++; } @@ -585,68 +652,62 @@ struct reg_cache *arm_build_reg_cache(struct target *target, struct arm *arm) int arm_arch_state(struct target *target) { - struct arm *armv4_5 = target_to_arm(target); + struct arm *arm = target_to_arm(target); - if (armv4_5->common_magic != ARM_COMMON_MAGIC) - { + if (arm->common_magic != ARM_COMMON_MAGIC) { LOG_ERROR("BUG: called for a non-ARM target"); return ERROR_FAIL; } LOG_USER("target halted in %s state due to %s, current mode: %s\n" - "cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "%s", - arm_state_strings[armv4_5->core_state], - debug_reason_name(target), - arm_mode_name(armv4_5->core_mode), - buf_get_u32(armv4_5->cpsr->value, 0, 32), - buf_get_u32(armv4_5->pc->value, 0, 32), - armv4_5->is_semihosting ? ", semihosting" : ""); + "cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "%s", + arm_state_strings[arm->core_state], + debug_reason_name(target), + arm_mode_name(arm->core_mode), + buf_get_u32(arm->cpsr->value, 0, 32), + buf_get_u32(arm->pc->value, 0, 32), + arm->is_semihosting ? ", semihosting" : ""); return ERROR_OK; } #define ARMV4_5_CORE_REG_MODENUM(cache, mode, num) \ - cache->reg_list[armv4_5_core_reg_map[mode][num]] + (cache->reg_list[armv4_5_core_reg_map[mode][num]]) COMMAND_HANDLER(handle_armv4_5_reg_command) { struct target *target = get_current_target(CMD_CTX); - struct arm *armv4_5 = target_to_arm(target); - unsigned num_regs; + struct arm *arm = target_to_arm(target); struct reg *regs; - if (!is_arm(armv4_5)) - { + if (!is_arm(arm)) { command_print(CMD_CTX, "current target isn't an ARM"); return ERROR_FAIL; } - if (target->state != TARGET_HALTED) - { + if (target->state != TARGET_HALTED) { command_print(CMD_CTX, "error: target must be halted for register accesses"); return ERROR_FAIL; } - if (armv4_5->core_type != ARM_MODE_ANY) - { - command_print(CMD_CTX, "Microcontroller Profile not supported - use standard reg cmd"); + if (arm->core_type != ARM_MODE_ANY) { + command_print(CMD_CTX, + "Microcontroller Profile not supported - use standard reg cmd"); return ERROR_OK; } - if (!is_arm_mode(armv4_5->core_mode)) - { + if (!is_arm_mode(arm->core_mode)) { LOG_ERROR("not a valid arm core mode - communication failure?"); return ERROR_FAIL; } - if (!armv4_5->full_context) { + if (!arm->full_context) { command_print(CMD_CTX, "error: target doesn't support %s", - CMD_NAME); + CMD_NAME); return ERROR_FAIL; } - num_regs = armv4_5->core_cache->num_regs; - regs = armv4_5->core_cache->reg_list; + regs = arm->core_cache->reg_list; for (unsigned mode = 0; mode < ARRAY_SIZE(arm_mode_data); mode++) { const char *name; @@ -655,26 +716,26 @@ COMMAND_HANDLER(handle_armv4_5_reg_command) /* label this bank of registers (or shadows) */ switch (arm_mode_data[mode].psr) { - case ARM_MODE_SYS: - continue; - case ARM_MODE_USR: - name = "System and User"; - sep = ""; - break; - case ARM_MODE_MON: - if (armv4_5->core_type != ARM_MODE_MON) + case ARM_MODE_SYS: continue; + case ARM_MODE_USR: + name = "System and User"; + sep = ""; + break; + case ARM_MODE_MON: + if (arm->core_type != ARM_MODE_MON) + continue; /* FALLTHROUGH */ - default: - name = arm_mode_data[mode].name; - shadow = "shadow "; - break; + default: + name = arm_mode_data[mode].name; + shadow = "shadow "; + break; } command_print(CMD_CTX, "%s%s mode %sregisters", - sep, name, shadow); + sep, name, shadow); /* display N rows of up to 4 registers each */ - for (unsigned i = 0; i < arm_mode_data[mode].n_indices;) { + for (unsigned i = 0; i < arm_mode_data[mode].n_indices; ) { char output[80]; int output_len = 0; @@ -689,13 +750,13 @@ COMMAND_HANDLER(handle_armv4_5_reg_command) /* REVISIT be smarter about faults... */ if (!reg->valid) - armv4_5->full_context(target); + arm->full_context(target); value = buf_get_u32(reg->value, 0, 32); output_len += snprintf(output + output_len, sizeof(output) - output_len, - "%8s: %8.8" PRIx32 " ", - reg->name, value); + "%8s: %8.8" PRIx32 " ", + reg->name, value); } command_print(CMD_CTX, "%s", output); } @@ -707,34 +768,27 @@ COMMAND_HANDLER(handle_armv4_5_reg_command) COMMAND_HANDLER(handle_armv4_5_core_state_command) { struct target *target = get_current_target(CMD_CTX); - struct arm *armv4_5 = target_to_arm(target); + struct arm *arm = target_to_arm(target); - if (!is_arm(armv4_5)) - { + if (!is_arm(arm)) { command_print(CMD_CTX, "current target isn't an ARM"); return ERROR_FAIL; } - if (armv4_5->core_type == ARM_MODE_THREAD) - { + if (arm->core_type == ARM_MODE_THREAD) { /* armv7m not supported */ command_print(CMD_CTX, "Unsupported Command"); return ERROR_OK; } - if (CMD_ARGC > 0) - { + if (CMD_ARGC > 0) { if (strcmp(CMD_ARGV[0], "arm") == 0) - { - armv4_5->core_state = ARM_STATE_ARM; - } + arm->core_state = ARM_STATE_ARM; if (strcmp(CMD_ARGV[0], "thumb") == 0) - { - armv4_5->core_state = ARM_STATE_THUMB; - } + arm->core_state = ARM_STATE_THUMB; } - command_print(CMD_CTX, "core state: %s", arm_state_strings[armv4_5->core_state]); + command_print(CMD_CTX, "core state: %s", arm_state_strings[arm->core_state]); return ERROR_OK; } @@ -743,7 +797,13 @@ COMMAND_HANDLER(handle_arm_disassemble_command) { int retval = ERROR_OK; struct target *target = get_current_target(CMD_CTX); - struct arm *arm = target ? target_to_arm(target) : NULL; + + if (target == NULL) { + LOG_ERROR("No target selected"); + return ERROR_FAIL; + } + + struct arm *arm = target_to_arm(target); uint32_t address; int count = 1; int thumb = 0; @@ -753,37 +813,34 @@ COMMAND_HANDLER(handle_arm_disassemble_command) return ERROR_FAIL; } - if (arm->core_type == ARM_MODE_THREAD) - { + if (arm->core_type == ARM_MODE_THREAD) { /* armv7m is always thumb mode */ thumb = 1; } switch (CMD_ARGC) { - case 3: - if (strcmp(CMD_ARGV[2], "thumb") != 0) - goto usage; - thumb = 1; + case 3: + if (strcmp(CMD_ARGV[2], "thumb") != 0) + goto usage; + thumb = 1; /* FALL THROUGH */ - case 2: - COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], count); + case 2: + COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], count); /* FALL THROUGH */ - case 1: - COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], address); - if (address & 0x01) { - if (!thumb) { - command_print(CMD_CTX, "Disassemble as Thumb"); - thumb = 1; + case 1: + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], address); + if (address & 0x01) { + if (!thumb) { + command_print(CMD_CTX, "Disassemble as Thumb"); + thumb = 1; + } + address &= ~1; } - address &= ~1; - } - break; - default: + break; + default: usage: - command_print(CMD_CTX, - "usage: arm disassemble
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