X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Farmv4_5.c;h=7468e389f442b68a0462009d472d9817465280ac;hb=c2ab3b4d5efba0201d88d899dc0fd310574ef5b9;hp=80c06ef31d355a7c4f5f523b928935a4066ea06c;hpb=d1bc4375e99ce52b72988494f35beca364234bae;p=openocd.git diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c index 80c06ef31d..7468e389f4 100644 --- a/src/target/armv4_5.c +++ b/src/target/armv4_5.c @@ -27,6 +27,7 @@ #include "config.h" #endif +#include "arm.h" #include "armv4_5.h" #include "arm_jtag.h" #include "breakpoints.h" @@ -89,43 +90,43 @@ static const struct { */ { .name = "User", - .psr = ARMV4_5_MODE_USR, + .psr = ARM_MODE_USR, .n_indices = ARRAY_SIZE(arm_usr_indices), .indices = arm_usr_indices, }, { .name = "FIQ", - .psr = ARMV4_5_MODE_FIQ, + .psr = ARM_MODE_FIQ, .n_indices = ARRAY_SIZE(arm_fiq_indices), .indices = arm_fiq_indices, }, { .name = "Supervisor", - .psr = ARMV4_5_MODE_SVC, + .psr = ARM_MODE_SVC, .n_indices = ARRAY_SIZE(arm_svc_indices), .indices = arm_svc_indices, }, { .name = "Abort", - .psr = ARMV4_5_MODE_ABT, + .psr = ARM_MODE_ABT, .n_indices = ARRAY_SIZE(arm_abt_indices), .indices = arm_abt_indices, }, { .name = "IRQ", - .psr = ARMV4_5_MODE_IRQ, + .psr = ARM_MODE_IRQ, .n_indices = ARRAY_SIZE(arm_irq_indices), .indices = arm_irq_indices, }, { .name = "Undefined instruction", - .psr = ARMV4_5_MODE_UND, + .psr = ARM_MODE_UND, .n_indices = ARRAY_SIZE(arm_und_indices), .indices = arm_und_indices, }, { .name = "System", - .psr = ARMV4_5_MODE_SYS, + .psr = ARM_MODE_SYS, .n_indices = ARRAY_SIZE(arm_usr_indices), .indices = arm_usr_indices, }, @@ -163,24 +164,24 @@ bool is_arm_mode(unsigned psr_mode) } /** Map PSR mode bits to linear number indexing armv4_5_core_reg_map */ -int armv4_5_mode_to_number(enum armv4_5_mode mode) +int arm_mode_to_number(enum arm_mode mode) { switch (mode) { - case ARMV4_5_MODE_ANY: + case ARM_MODE_ANY: /* map MODE_ANY to user mode */ - case ARMV4_5_MODE_USR: + case ARM_MODE_USR: return 0; - case ARMV4_5_MODE_FIQ: + case ARM_MODE_FIQ: return 1; - case ARMV4_5_MODE_IRQ: + case ARM_MODE_IRQ: return 2; - case ARMV4_5_MODE_SVC: + case ARM_MODE_SVC: return 3; - case ARMV4_5_MODE_ABT: + case ARM_MODE_ABT: return 4; - case ARMV4_5_MODE_UND: + case ARM_MODE_UND: return 5; - case ARMV4_5_MODE_SYS: + case ARM_MODE_SYS: return 6; case ARM_MODE_MON: return 7; @@ -191,32 +192,32 @@ int armv4_5_mode_to_number(enum armv4_5_mode mode) } /** Map linear number indexing armv4_5_core_reg_map to PSR mode bits. */ -enum armv4_5_mode armv4_5_number_to_mode(int number) +enum arm_mode armv4_5_number_to_mode(int number) { switch (number) { case 0: - return ARMV4_5_MODE_USR; + return ARM_MODE_USR; case 1: - return ARMV4_5_MODE_FIQ; + return ARM_MODE_FIQ; case 2: - return ARMV4_5_MODE_IRQ; + return ARM_MODE_IRQ; case 3: - return ARMV4_5_MODE_SVC; + return ARM_MODE_SVC; case 4: - return ARMV4_5_MODE_ABT; + return ARM_MODE_ABT; case 5: - return ARMV4_5_MODE_UND; + return ARM_MODE_UND; case 6: - return ARMV4_5_MODE_SYS; + return ARM_MODE_SYS; case 7: return ARM_MODE_MON; default: LOG_ERROR("mode index out of bounds %d", number); - return ARMV4_5_MODE_ANY; + return ARM_MODE_ANY; } } -char* armv4_5_state_strings[] = +static const char *arm_state_strings[] = { "ARM", "Thumb", "Jazelle", "ThumbEE", }; @@ -243,65 +244,65 @@ static const struct { * (Exception modes have both CPSR and SPSR registers ...) */ unsigned cookie; - enum armv4_5_mode mode; + enum arm_mode mode; } arm_core_regs[] = { /* IMPORTANT: we guarantee that the first eight cached registers * correspond to r0..r7, and the fifteenth to PC, so that callers * don't need to map them. */ - { .name = "r0", .cookie = 0, .mode = ARMV4_5_MODE_ANY, }, - { .name = "r1", .cookie = 1, .mode = ARMV4_5_MODE_ANY, }, - { .name = "r2", .cookie = 2, .mode = ARMV4_5_MODE_ANY, }, - { .name = "r3", .cookie = 3, .mode = ARMV4_5_MODE_ANY, }, - { .name = "r4", .cookie = 4, .mode = ARMV4_5_MODE_ANY, }, - { .name = "r5", .cookie = 5, .mode = ARMV4_5_MODE_ANY, }, - { .name = "r6", .cookie = 6, .mode = ARMV4_5_MODE_ANY, }, - { .name = "r7", .cookie = 7, .mode = ARMV4_5_MODE_ANY, }, + { .name = "r0", .cookie = 0, .mode = ARM_MODE_ANY, }, + { .name = "r1", .cookie = 1, .mode = ARM_MODE_ANY, }, + { .name = "r2", .cookie = 2, .mode = ARM_MODE_ANY, }, + { .name = "r3", .cookie = 3, .mode = ARM_MODE_ANY, }, + { .name = "r4", .cookie = 4, .mode = ARM_MODE_ANY, }, + { .name = "r5", .cookie = 5, .mode = ARM_MODE_ANY, }, + { .name = "r6", .cookie = 6, .mode = ARM_MODE_ANY, }, + { .name = "r7", .cookie = 7, .mode = ARM_MODE_ANY, }, /* NOTE: regs 8..12 might be shadowed by FIQ ... flagging * them as MODE_ANY creates special cases. (ANY means * "not mapped" elsewhere; here it's "everything but FIQ".) */ - { .name = "r8", .cookie = 8, .mode = ARMV4_5_MODE_ANY, }, - { .name = "r9", .cookie = 9, .mode = ARMV4_5_MODE_ANY, }, - { .name = "r10", .cookie = 10, .mode = ARMV4_5_MODE_ANY, }, - { .name = "r11", .cookie = 11, .mode = ARMV4_5_MODE_ANY, }, - { .name = "r12", .cookie = 12, .mode = ARMV4_5_MODE_ANY, }, + { .name = "r8", .cookie = 8, .mode = ARM_MODE_ANY, }, + { .name = "r9", .cookie = 9, .mode = ARM_MODE_ANY, }, + { .name = "r10", .cookie = 10, .mode = ARM_MODE_ANY, }, + { .name = "r11", .cookie = 11, .mode = ARM_MODE_ANY, }, + { .name = "r12", .cookie = 12, .mode = ARM_MODE_ANY, }, /* NOTE all MODE_USR registers are equivalent to MODE_SYS ones */ - { .name = "sp_usr", .cookie = 13, .mode = ARMV4_5_MODE_USR, }, - { .name = "lr_usr", .cookie = 14, .mode = ARMV4_5_MODE_USR, }, + { .name = "sp_usr", .cookie = 13, .mode = ARM_MODE_USR, }, + { .name = "lr_usr", .cookie = 14, .mode = ARM_MODE_USR, }, /* guaranteed to be at index 15 */ - { .name = "pc", .cookie = 15, .mode = ARMV4_5_MODE_ANY, }, + { .name = "pc", .cookie = 15, .mode = ARM_MODE_ANY, }, - { .name = "r8_fiq", .cookie = 8, .mode = ARMV4_5_MODE_FIQ, }, - { .name = "r9_fiq", .cookie = 9, .mode = ARMV4_5_MODE_FIQ, }, - { .name = "r10_fiq", .cookie = 10, .mode = ARMV4_5_MODE_FIQ, }, - { .name = "r11_fiq", .cookie = 11, .mode = ARMV4_5_MODE_FIQ, }, - { .name = "r12_fiq", .cookie = 12, .mode = ARMV4_5_MODE_FIQ, }, + { .name = "r8_fiq", .cookie = 8, .mode = ARM_MODE_FIQ, }, + { .name = "r9_fiq", .cookie = 9, .mode = ARM_MODE_FIQ, }, + { .name = "r10_fiq", .cookie = 10, .mode = ARM_MODE_FIQ, }, + { .name = "r11_fiq", .cookie = 11, .mode = ARM_MODE_FIQ, }, + { .name = "r12_fiq", .cookie = 12, .mode = ARM_MODE_FIQ, }, - { .name = "sp_fiq", .cookie = 13, .mode = ARMV4_5_MODE_FIQ, }, - { .name = "lr_fiq", .cookie = 14, .mode = ARMV4_5_MODE_FIQ, }, + { .name = "sp_fiq", .cookie = 13, .mode = ARM_MODE_FIQ, }, + { .name = "lr_fiq", .cookie = 14, .mode = ARM_MODE_FIQ, }, - { .name = "sp_irq", .cookie = 13, .mode = ARMV4_5_MODE_IRQ, }, - { .name = "lr_irq", .cookie = 14, .mode = ARMV4_5_MODE_IRQ, }, + { .name = "sp_irq", .cookie = 13, .mode = ARM_MODE_IRQ, }, + { .name = "lr_irq", .cookie = 14, .mode = ARM_MODE_IRQ, }, - { .name = "sp_svc", .cookie = 13, .mode = ARMV4_5_MODE_SVC, }, - { .name = "lr_svc", .cookie = 14, .mode = ARMV4_5_MODE_SVC, }, + { .name = "sp_svc", .cookie = 13, .mode = ARM_MODE_SVC, }, + { .name = "lr_svc", .cookie = 14, .mode = ARM_MODE_SVC, }, - { .name = "sp_abt", .cookie = 13, .mode = ARMV4_5_MODE_ABT, }, - { .name = "lr_abt", .cookie = 14, .mode = ARMV4_5_MODE_ABT, }, + { .name = "sp_abt", .cookie = 13, .mode = ARM_MODE_ABT, }, + { .name = "lr_abt", .cookie = 14, .mode = ARM_MODE_ABT, }, - { .name = "sp_und", .cookie = 13, .mode = ARMV4_5_MODE_UND, }, - { .name = "lr_und", .cookie = 14, .mode = ARMV4_5_MODE_UND, }, + { .name = "sp_und", .cookie = 13, .mode = ARM_MODE_UND, }, + { .name = "lr_und", .cookie = 14, .mode = ARM_MODE_UND, }, - { .name = "cpsr", .cookie = 16, .mode = ARMV4_5_MODE_ANY, }, - { .name = "spsr_fiq", .cookie = 16, .mode = ARMV4_5_MODE_FIQ, }, - { .name = "spsr_irq", .cookie = 16, .mode = ARMV4_5_MODE_IRQ, }, - { .name = "spsr_svc", .cookie = 16, .mode = ARMV4_5_MODE_SVC, }, - { .name = "spsr_abt", .cookie = 16, .mode = ARMV4_5_MODE_ABT, }, - { .name = "spsr_und", .cookie = 16, .mode = ARMV4_5_MODE_UND, }, + { .name = "cpsr", .cookie = 16, .mode = ARM_MODE_ANY, }, + { .name = "spsr_fiq", .cookie = 16, .mode = ARM_MODE_FIQ, }, + { .name = "spsr_irq", .cookie = 16, .mode = ARM_MODE_IRQ, }, + { .name = "spsr_svc", .cookie = 16, .mode = ARM_MODE_SVC, }, + { .name = "spsr_abt", .cookie = 16, .mode = ARM_MODE_ABT, }, + { .name = "spsr_und", .cookie = 16, .mode = ARM_MODE_UND, }, { .name = "sp_mon", .cookie = 13, .mode = ARM_MODE_MON, }, { .name = "lr_mon", .cookie = 14, .mode = ARM_MODE_MON, }, @@ -346,7 +347,7 @@ const int armv4_5_core_reg_map[8][17] = */ void arm_set_cpsr(struct arm *arm, uint32_t cpsr) { - enum armv4_5_mode mode = cpsr & 0x1f; + enum arm_mode mode = cpsr & 0x1f; int num; /* NOTE: this may be called very early, before the register @@ -362,38 +363,38 @@ void arm_set_cpsr(struct arm *arm, uint32_t cpsr) arm->core_mode = mode; /* mode_to_number() warned; set up a somewhat-sane mapping */ - num = armv4_5_mode_to_number(mode); + num = arm_mode_to_number(mode); if (num < 0) { - mode = ARMV4_5_MODE_USR; + mode = ARM_MODE_USR; num = 0; } arm->map = &armv4_5_core_reg_map[num][0]; - arm->spsr = (mode == ARMV4_5_MODE_USR || mode == ARMV4_5_MODE_SYS) + arm->spsr = (mode == ARM_MODE_USR || mode == ARM_MODE_SYS) ? NULL : arm->core_cache->reg_list + arm->map[16]; /* Older ARMs won't have the J bit */ - enum armv4_5_state state; + enum arm_state state; if (cpsr & (1 << 5)) { /* T */ if (cpsr & (1 << 24)) { /* J */ LOG_WARNING("ThumbEE -- incomplete support"); state = ARM_STATE_THUMB_EE; } else - state = ARMV4_5_STATE_THUMB; + state = ARM_STATE_THUMB; } else { if (cpsr & (1 << 24)) { /* J */ LOG_ERROR("Jazelle state handling is BROKEN!"); - state = ARMV4_5_STATE_JAZELLE; + state = ARM_STATE_JAZELLE; } else - state = ARMV4_5_STATE_ARM; + state = ARM_STATE_ARM; } arm->core_state = state; LOG_DEBUG("set CPSR %#8.8x: %s mode, %s state", (unsigned) cpsr, arm_mode_name(mode), - armv4_5_state_strings[arm->core_state]); + arm_state_strings[arm->core_state]); } /** @@ -491,7 +492,7 @@ static int armv4_5_set_core_reg(struct reg *reg, uint8_t *buf) { struct arm_reg *armv4_5 = reg->arch_info; struct target *target = armv4_5->target; - struct arm *armv4_5_target = target_to_armv4_5(target); + struct arm *armv4_5_target = target_to_arm(target); uint32_t value = buf_get_u32(buf, 0, 32); if (target->state != TARGET_HALTED) @@ -512,12 +513,12 @@ static int armv4_5_set_core_reg(struct reg *reg, uint8_t *buf) * it won't hurt since CPSR is always flushed anyway. */ if (armv4_5_target->core_mode != - (enum armv4_5_mode)(value & 0x1f)) { + (enum arm_mode)(value & 0x1f)) { LOG_DEBUG("changing ARM core mode to '%s'", arm_mode_name(value & 0x1f)); value &= ~((1 << 24) | (1 << 5)); armv4_5_target->write_core_reg(target, reg, - 16, ARMV4_5_MODE_ANY, value); + 16, ARM_MODE_ANY, value); } } else { buf_set_u32(reg->value, 0, 32, value); @@ -533,7 +534,7 @@ static const struct reg_arch_type arm_reg_type = { .set = armv4_5_set_core_reg, }; -struct reg_cache* armv4_5_build_reg_cache(struct target *target, struct arm *armv4_5_common) +struct reg_cache *arm_build_reg_cache(struct target *target, struct arm *arm) { int num_regs = ARRAY_SIZE(arm_core_regs); struct reg_cache *cache = malloc(sizeof(struct reg_cache)); @@ -557,7 +558,7 @@ struct reg_cache* armv4_5_build_reg_cache(struct target *target, struct arm *arm { /* Skip registers this core doesn't expose */ if (arm_core_regs[i].mode == ARM_MODE_MON - && armv4_5_common->core_type != ARM_MODE_MON) + && arm->core_type != ARM_MODE_MON) continue; /* REVISIT handle Cortex-M, which only shadows R13/SP */ @@ -565,7 +566,7 @@ struct reg_cache* armv4_5_build_reg_cache(struct target *target, struct arm *arm arch_info[i].num = arm_core_regs[i].cookie; arch_info[i].mode = arm_core_regs[i].mode; arch_info[i].target = target; - arch_info[i].armv4_5_common = armv4_5_common; + arch_info[i].armv4_5_common = arm; reg_list[i].name = (char *) arm_core_regs[i].name; reg_list[i].size = 32; @@ -576,27 +577,30 @@ struct reg_cache* armv4_5_build_reg_cache(struct target *target, struct arm *arm cache->num_regs++; } - armv4_5_common->cpsr = reg_list + ARMV4_5_CPSR; - armv4_5_common->core_cache = cache; + arm->pc = reg_list + 15; + arm->cpsr = reg_list + ARMV4_5_CPSR; + arm->core_cache = cache; return cache; } -int armv4_5_arch_state(struct target *target) +int arm_arch_state(struct target *target) { - struct arm *armv4_5 = target_to_armv4_5(target); + struct arm *armv4_5 = target_to_arm(target); - if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC) + if (armv4_5->common_magic != ARM_COMMON_MAGIC) { - LOG_ERROR("BUG: called for a non-ARMv4/5 target"); + LOG_ERROR("BUG: called for a non-ARM target"); return ERROR_FAIL; } - LOG_USER("target halted in %s state due to %s, current mode: %s\ncpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "", - armv4_5_state_strings[armv4_5->core_state], - Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name, - arm_mode_name(armv4_5->core_mode), - buf_get_u32(armv4_5->cpsr->value, 0, 32), - buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)); + LOG_USER("target halted in %s state due to %s, current mode: %s\n" + "cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "%s", + arm_state_strings[armv4_5->core_state], + debug_reason_name(target), + arm_mode_name(armv4_5->core_mode), + buf_get_u32(armv4_5->cpsr->value, 0, 32), + buf_get_u32(armv4_5->pc->value, 0, 32), + armv4_5->is_semihosting ? ", semihosting" : ""); return ERROR_OK; } @@ -607,8 +611,7 @@ int armv4_5_arch_state(struct target *target) COMMAND_HANDLER(handle_armv4_5_reg_command) { struct target *target = get_current_target(CMD_CTX); - struct arm *armv4_5 = target_to_armv4_5(target); - unsigned num_regs; + struct arm *armv4_5 = target_to_arm(target); struct reg *regs; if (!is_arm(armv4_5)) @@ -623,8 +626,17 @@ COMMAND_HANDLER(handle_armv4_5_reg_command) return ERROR_FAIL; } + if (armv4_5->core_type != ARM_MODE_ANY) + { + command_print(CMD_CTX, "Microcontroller Profile not supported - use standard reg cmd"); + return ERROR_OK; + } + if (!is_arm_mode(armv4_5->core_mode)) + { + LOG_ERROR("not a valid arm core mode - communication failure?"); return ERROR_FAIL; + } if (!armv4_5->full_context) { command_print(CMD_CTX, "error: target doesn't support %s", @@ -632,7 +644,6 @@ COMMAND_HANDLER(handle_armv4_5_reg_command) return ERROR_FAIL; } - num_regs = armv4_5->core_cache->num_regs; regs = armv4_5->core_cache->reg_list; for (unsigned mode = 0; mode < ARRAY_SIZE(arm_mode_data); mode++) { @@ -642,9 +653,9 @@ COMMAND_HANDLER(handle_armv4_5_reg_command) /* label this bank of registers (or shadows) */ switch (arm_mode_data[mode].psr) { - case ARMV4_5_MODE_SYS: + case ARM_MODE_SYS: continue; - case ARMV4_5_MODE_USR: + case ARM_MODE_USR: name = "System and User"; sep = ""; break; @@ -694,7 +705,7 @@ COMMAND_HANDLER(handle_armv4_5_reg_command) COMMAND_HANDLER(handle_armv4_5_core_state_command) { struct target *target = get_current_target(CMD_CTX); - struct arm *armv4_5 = target_to_armv4_5(target); + struct arm *armv4_5 = target_to_arm(target); if (!is_arm(armv4_5)) { @@ -702,28 +713,41 @@ COMMAND_HANDLER(handle_armv4_5_core_state_command) return ERROR_FAIL; } + if (armv4_5->core_type == ARM_MODE_THREAD) + { + /* armv7m not supported */ + command_print(CMD_CTX, "Unsupported Command"); + return ERROR_OK; + } + if (CMD_ARGC > 0) { if (strcmp(CMD_ARGV[0], "arm") == 0) { - armv4_5->core_state = ARMV4_5_STATE_ARM; + armv4_5->core_state = ARM_STATE_ARM; } if (strcmp(CMD_ARGV[0], "thumb") == 0) { - armv4_5->core_state = ARMV4_5_STATE_THUMB; + armv4_5->core_state = ARM_STATE_THUMB; } } - command_print(CMD_CTX, "core state: %s", armv4_5_state_strings[armv4_5->core_state]); + command_print(CMD_CTX, "core state: %s", arm_state_strings[armv4_5->core_state]); return ERROR_OK; } -COMMAND_HANDLER(handle_armv4_5_disassemble_command) +COMMAND_HANDLER(handle_arm_disassemble_command) { int retval = ERROR_OK; struct target *target = get_current_target(CMD_CTX); - struct arm *arm = target ? target_to_arm(target) : NULL; + + if (target == NULL) { + LOG_ERROR("No target selected"); + return ERROR_FAIL; + } + + struct arm *arm = target_to_arm(target); uint32_t address; int count = 1; int thumb = 0; @@ -733,6 +757,12 @@ COMMAND_HANDLER(handle_armv4_5_disassemble_command) return ERROR_FAIL; } + if (arm->core_type == ARM_MODE_THREAD) + { + /* armv7m is always thumb mode */ + thumb = 1; + } + switch (CMD_ARGC) { case 3: if (strcmp(CMD_ARGV[2], "thumb") != 0) @@ -754,10 +784,8 @@ COMMAND_HANDLER(handle_armv4_5_disassemble_command) break; default: usage: - command_print(CMD_CTX, - "usage: arm disassemble
[