X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Farmv4_5.c;h=a2f055753bfa1d176af1e90209dd9f3af9a27ac7;hb=80a94681de4c304ed8d550d4da547cdc523d2207;hp=e31c77e49be1236d92be624b22ecff23ce804bca;hpb=d2d4f776d8e24e8e651d1c896c90c15c38633172;p=openocd.git

diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index e31c77e49b..a2f055753b 100644
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -21,7 +21,7 @@
  *   You should have received a copy of the GNU General Public License     *
  *   along with this program; if not, write to the                         *
  *   Free Software Foundation, Inc.,                                       *
- *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
+ *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
  ***************************************************************************/
 
 #ifdef HAVE_CONFIG_H
@@ -140,6 +140,21 @@ static const struct {
 		.n_indices = ARRAY_SIZE(arm_mon_indices),
 		.indices = arm_mon_indices,
 	},
+
+	/* These special modes are currently only supported
+	 * by ARMv6M and ARMv7M profiles */
+	{
+		.name = "Thread",
+		.psr = ARM_MODE_THREAD,
+	},
+	{
+		.name = "Thread (User)",
+		.psr = ARM_MODE_USER_THREAD,
+	},
+	{
+		.name = "Handler",
+		.psr = ARM_MODE_HANDLER,
+	},
 };
 
 /** Map PSR mode bits to the name of an ARM processor operating mode. */
@@ -414,7 +429,11 @@ struct reg *arm_reg_current(struct arm *arm, unsigned regnum)
 	if (regnum > 16)
 		return NULL;
 
-	r = arm->core_cache->reg_list + arm->map[regnum];
+	if (!arm->map) {
+		LOG_ERROR("Register map is not available yet, the target is not fully initialised");
+		r = arm->core_cache->reg_list + regnum;
+	} else
+		r = arm->core_cache->reg_list + arm->map[regnum];
 
 	/* e.g. invalid CPSR said "secure monitor" mode on a core
 	 * that doesn't support it...
@@ -1002,13 +1021,13 @@ static const struct command_registration arm_exec_command_handlers[] = {
 		.mode = COMMAND_EXEC,
 		.jim_handler = &jim_mcrmrc,
 		.help = "write coprocessor register",
-		.usage = "cpnum op1 CRn op2 CRm value",
+		.usage = "cpnum op1 CRn CRm op2 value",
 	},
 	{
 		.name = "mrc",
 		.jim_handler = &jim_mcrmrc,
 		.help = "read coprocessor register",
-		.usage = "cpnum op1 CRn op2 CRm",
+		.usage = "cpnum op1 CRn CRm op2",
 	},
 	{
 		"semihosting",
@@ -1032,7 +1051,8 @@ const struct command_registration arm_command_handlers[] = {
 };
 
 int arm_get_gdb_reg_list(struct target *target,
-	struct reg **reg_list[], int *reg_list_size)
+	struct reg **reg_list[], int *reg_list_size,
+	enum target_register_class reg_class)
 {
 	struct arm *arm = target_to_arm(target);
 	int i;