X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Farmv4_5.h;h=250d95bbdfc8de990d428e2c0b74bf368e717221;hb=3271e6d4d598f7221be339ec8449c25904538a4e;hp=bacdb72e656a36cb89cdb33a0b34aed68a656add;hpb=0a1b7dcfc40385f09b5eb088cd97d6ff25a5816d;p=openocd.git

diff --git a/src/target/armv4_5.h b/src/target/armv4_5.h
index bacdb72e65..250d95bbdf 100644
--- a/src/target/armv4_5.h
+++ b/src/target/armv4_5.h
@@ -21,8 +21,9 @@
  *   You should have received a copy of the GNU General Public License     *
  *   along with this program; if not, write to the                         *
  *   Free Software Foundation, Inc.,                                       *
- *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
+ *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
  ***************************************************************************/
+
 #ifndef ARMV4_5_H
 #define ARMV4_5_H
 
@@ -42,7 +43,7 @@ enum arm_mode armv4_5_number_to_mode(int number);
 extern const int armv4_5_core_reg_map[8][17];
 
 #define ARMV4_5_CORE_REG_MODE(cache, mode, num) \
-		cache->reg_list[armv4_5_core_reg_map[arm_mode_to_number(mode)][num]]
+		(cache->reg_list[armv4_5_core_reg_map[arm_mode_to_number(mode)][num]])
 
 /* offset into armv4_5 core register cache -- OBSOLETE, DO NOT USE! */
 enum { ARMV4_5_CPSR = 31, };