X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Farmv4_5.h;h=f04a41137fdeb0dd54103ee730bb4db1fc0885e7;hb=4cb9b179059bb40badde110da5641dcbbd636a29;hp=47996de4f0f243d413d3d99fda793baee9181901;hpb=78ecef2aed5fcdc25ec669d6cc28b1bc495b0ff6;p=openocd.git

diff --git a/src/target/armv4_5.h b/src/target/armv4_5.h
index 47996de4f0..f04a41137f 100644
--- a/src/target/armv4_5.h
+++ b/src/target/armv4_5.h
@@ -23,7 +23,7 @@
 #include "register.h"
 #include "target.h"
 
-enum armv4_5_mode
+typedef enum armv4_5_mode
 {
 	ARMV4_5_MODE_USR = 16, 
 	ARMV4_5_MODE_FIQ = 17, 
@@ -33,16 +33,16 @@ enum armv4_5_mode
 	ARMV4_5_MODE_UND = 27,
 	ARMV4_5_MODE_SYS = 31,
 	ARMV4_5_MODE_ANY = -1
-};
+} armv4_5_mode_t;
 
 extern char* armv4_5_mode_strings[];
 
-enum armv4_5_state
+typedef enum armv4_5_state
 {
 	ARMV4_5_STATE_ARM,
 	ARMV4_5_STATE_THUMB,
 	ARMV4_5_STATE_JAZELLE,
-};
+} armv4_5_state_t;
 
 extern char* armv4_5_state_strings[];
 
@@ -98,7 +98,7 @@ extern reg_cache_t* armv4_5_build_reg_cache(target_t *target, armv4_5_common_t *
 extern enum armv4_5_mode armv4_5_number_to_mode(int number);
 extern int armv4_5_mode_to_number(enum armv4_5_mode mode);
 
-extern int armv4_5_arch_state(struct target_s *target, char *buf, int buf_size);
+extern int armv4_5_arch_state(struct target_s *target);
 extern int armv4_5_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_size);
 extern int armv4_5_invalidate_core_regs(target_t *target);
 
@@ -213,6 +213,11 @@ extern int armv4_5_invalidate_core_regs(target_t *target);
  */
 #define ARMV4_5_MCR(CP, op1, Rd, CRn, CRm, op2) (0xee000010 | (CRm) | ((op2) << 5) | ((CP) << 8) | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21)) 
 
+/* Breakpoint instruction (ARMv5)
+ * Im: 16-bit immediate
+ */
+#define ARMV5_BKPT(Im) (0xe1200070 | ((Im & 0xfff0) << 8) | (Im & 0xf))
+
 
 /* Thumb mode instructions
  */
@@ -266,4 +271,9 @@ extern int armv4_5_invalidate_core_regs(target_t *target);
  */
 #define ARMV4_5_T_B(Imm)	((0xe000 | (Imm)) | ((0xe000 | (Imm)) << 16))
 
+/* Breakpoint instruction (ARMv5) (Thumb state)
+ * Im: 8-bit immediate
+ */
+#define ARMV5_T_BKPT(Im) ((0xbe00 | Im) | ((0xbe00 | Im) << 16))
+
 #endif /* ARMV4_5_H */