X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Farmv4_5_mmu.c;h=4088fd22cd4cbe0d9a9f97d4bf080ff02a33065e;hb=a585bdf7269ce5c861c83ee3294ba1f074e9c877;hp=b888933c5a8487f75981fae55d16e86a395bfdcd;hpb=3acb107b9ae4e3d38d3fcfd29b455ebcfb444696;p=openocd.git diff --git a/src/target/armv4_5_mmu.c b/src/target/armv4_5_mmu.c index b888933c5a..4088fd22cd 100644 --- a/src/target/armv4_5_mmu.c +++ b/src/target/armv4_5_mmu.c @@ -21,45 +21,41 @@ #include "config.h" #endif -#include "arm7_9_common.h" #include "log.h" -#include "command.h" #include "armv4_5_mmu.h" -#include "target.h" -#include -u32 armv4mmu_translate_va(target_t *target, armv4_5_mmu_common_t *armv4_5_mmu, u32 va, int *type, u32 *cb, int *domain, u32 *ap); -int armv4_5_mmu_read_physical(target_t *target, armv4_5_mmu_common_t *armv4_5_mmu, u32 address, u32 size, u32 count, u8 *buffer); -int armv4_5_mmu_write_physical(target_t *target, armv4_5_mmu_common_t *armv4_5_mmu, u32 address, u32 size, u32 count, u8 *buffer); +uint32_t armv4mmu_translate_va(target_t *target, armv4_5_mmu_common_t *armv4_5_mmu, uint32_t va, int *type, uint32_t *cb, int *domain, uint32_t *ap); char* armv4_5_mmu_page_type_names[] = { "section", "large page", "small page", "tiny page" }; -u32 armv4_5_mmu_translate_va(target_t *target, armv4_5_mmu_common_t *armv4_5_mmu, u32 va, int *type, u32 *cb, int *domain, u32 *ap) +uint32_t armv4_5_mmu_translate_va(target_t *target, armv4_5_mmu_common_t *armv4_5_mmu, uint32_t va, int *type, uint32_t *cb, int *domain, uint32_t *ap) { - u32 first_lvl_descriptor = 0x0; - u32 second_lvl_descriptor = 0x0; - u32 ttb = armv4_5_mmu->get_ttb(target); + uint32_t first_lvl_descriptor = 0x0; + uint32_t second_lvl_descriptor = 0x0; + uint32_t ttb = armv4_5_mmu->get_ttb(target); armv4_5_mmu_read_physical(target, armv4_5_mmu, (ttb & 0xffffc000) | ((va & 0xfff00000) >> 18), - 4, 1, (u8*)&first_lvl_descriptor); - first_lvl_descriptor = target_buffer_get_u32(target, (u8*)&first_lvl_descriptor); + 4, 1, (uint8_t*)&first_lvl_descriptor); + first_lvl_descriptor = target_buffer_get_u32(target, (uint8_t*)&first_lvl_descriptor); - DEBUG("1st lvl desc: %8.8x", first_lvl_descriptor); + LOG_DEBUG("1st lvl desc: %8.8" PRIx32 "", first_lvl_descriptor); if ((first_lvl_descriptor & 0x3) == 0) { *type = -1; + LOG_ERROR("Address translation failure"); return ERROR_TARGET_TRANSLATION_FAULT; } if (!armv4_5_mmu->has_tiny_pages && ((first_lvl_descriptor & 0x3) == 3)) { *type = -1; + LOG_ERROR("Address translation failure"); return ERROR_TARGET_TRANSLATION_FAULT; } @@ -80,23 +76,24 @@ u32 armv4_5_mmu_translate_va(target_t *target, armv4_5_mmu_common_t *armv4_5_mmu /* coarse page table */ armv4_5_mmu_read_physical(target, armv4_5_mmu, (first_lvl_descriptor & 0xfffffc00) | ((va & 0x000ff000) >> 10), - 4, 1, (u8*)&second_lvl_descriptor); + 4, 1, (uint8_t*)&second_lvl_descriptor); } else if ((first_lvl_descriptor & 0x3) == 3) { /* fine page table */ armv4_5_mmu_read_physical(target, armv4_5_mmu, (first_lvl_descriptor & 0xfffff000) | ((va & 0x000ffc00) >> 8), - 4, 1, (u8*)&second_lvl_descriptor); + 4, 1, (uint8_t*)&second_lvl_descriptor); } - - second_lvl_descriptor = target_buffer_get_u32(target, (u8*)&second_lvl_descriptor); - - DEBUG("2nd lvl desc: %8.8x", second_lvl_descriptor); + + second_lvl_descriptor = target_buffer_get_u32(target, (uint8_t*)&second_lvl_descriptor); + + LOG_DEBUG("2nd lvl desc: %8.8" PRIx32 "", second_lvl_descriptor); if ((second_lvl_descriptor & 0x3) == 0) { *type = -1; + LOG_ERROR("Address translation failure"); return ERROR_TARGET_TRANSLATION_FAULT; } @@ -129,10 +126,11 @@ u32 armv4_5_mmu_translate_va(target_t *target, armv4_5_mmu_common_t *armv4_5_mmu /* should not happen */ *type = -1; + LOG_ERROR("Address translation failure"); return ERROR_TARGET_TRANSLATION_FAULT; } -int armv4_5_mmu_read_physical(target_t *target, armv4_5_mmu_common_t *armv4_5_mmu, u32 address, u32 size, u32 count, u8 *buffer) +int armv4_5_mmu_read_physical(target_t *target, armv4_5_mmu_common_t *armv4_5_mmu, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) { int retval; @@ -152,7 +150,7 @@ int armv4_5_mmu_read_physical(target_t *target, armv4_5_mmu_common_t *armv4_5_mm return retval; } -int armv4_5_mmu_write_physical(target_t *target, armv4_5_mmu_common_t *armv4_5_mmu, u32 address, u32 size, u32 count, u8 *buffer) +int armv4_5_mmu_write_physical(target_t *target, armv4_5_mmu_common_t *armv4_5_mmu, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) { int retval; @@ -161,209 +159,13 @@ int armv4_5_mmu_write_physical(target_t *target, armv4_5_mmu_common_t *armv4_5_m /* disable MMU and data (or unified) cache */ armv4_5_mmu->disable_mmu_caches(target, 1, 1, 0); - + retval = armv4_5_mmu->write_memory(target, address, size, count, buffer); /* reenable MMU / cache */ armv4_5_mmu->enable_mmu_caches(target, armv4_5_mmu->mmu_enabled, armv4_5_mmu->armv4_5_cache.d_u_cache_enabled, armv4_5_mmu->armv4_5_cache.i_cache_enabled); - - return retval; -} - -int armv4_5_mmu_handle_virt2phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc, target_t *target, armv4_5_mmu_common_t *armv4_5_mmu) -{ - u32 va; - u32 pa; - int type; - u32 cb; - int domain; - u32 ap; - - if (target->state != TARGET_HALTED) - { - command_print(cmd_ctx, "target must be stopped for \"virt2phys\" command"); - return ERROR_OK; - } - - if (argc == 0) - { - command_print(cmd_ctx, "usage: virt2phys "); - return ERROR_OK; - } - - if (argc == 1) - { - va = strtoul(args[0], NULL, 0); - pa = armv4_5_mmu_translate_va(target, armv4_5_mmu, va, &type, &cb, &domain, &ap); - if (type == -1) - { - switch (pa) - { - case ERROR_TARGET_TRANSLATION_FAULT: - command_print(cmd_ctx, "no valid translation for 0x%8.8x", va); - break; - default: - command_print(cmd_ctx, "unknown translation error"); - } - return ERROR_OK; - } - - command_print(cmd_ctx, "0x%8.8x -> 0x%8.8x, type: %s, cb: %i, domain: %i, ap: %2.2x", - va, pa, armv4_5_mmu_page_type_names[type], cb, domain, ap); - } - - return ERROR_OK; -} - -int armv4_5_mmu_handle_md_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc, target_t *target, armv4_5_mmu_common_t *armv4_5_mmu) -{ - int count = 1; - int size = 4; - u32 address = 0; - int i; - - char output[128]; - int output_len; - - int retval; - - u8 *buffer; - - if (target->state != TARGET_HALTED) - { - command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd); - return ERROR_OK; - } - - if (argc < 1) - return ERROR_OK; - - if (argc == 2) - count = strtoul(args[1], NULL, 0); - address = strtoul(args[0], NULL, 0); - - switch (cmd[2]) - { - case 'w': - size = 4; - break; - case 'h': - size = 2; - break; - case 'b': - size = 1; - break; - default: - return ERROR_OK; - } - - buffer = calloc(count, size); - if ((retval = armv4_5_mmu_read_physical(target, armv4_5_mmu, address, size, count, buffer)) != ERROR_OK) - { - switch (retval) - { - case ERROR_TARGET_UNALIGNED_ACCESS: - command_print(cmd_ctx, "error: address not aligned"); - break; - case ERROR_TARGET_NOT_HALTED: - command_print(cmd_ctx, "error: target must be halted for memory accesses"); - break; - case ERROR_TARGET_DATA_ABORT: - command_print(cmd_ctx, "error: access caused data abort, system possibly corrupted"); - break; - default: - command_print(cmd_ctx, "error: unknown error"); - } - } - - output_len = 0; - - for (i = 0; i < count; i++) - { - if (i%8 == 0) - output_len += snprintf(output + output_len, 128 - output_len, "0x%8.8x: ", address + (i*size)); - - switch (size) - { - case 4: - output_len += snprintf(output + output_len, 128 - output_len, "%8.8x ", target_buffer_get_u32(target, &buffer[i*4])); - break; - case 2: - output_len += snprintf(output + output_len, 128 - output_len, "%4.4x ", target_buffer_get_u16(target, &buffer[i*2])); - break; - case 1: - output_len += snprintf(output + output_len, 128 - output_len, "%2.2x ", buffer[i*1]); - break; - } - - if ((i % 8 == 7) || (i == count - 1)) - { - command_print(cmd_ctx, output); - output_len = 0; - } - } - - free(buffer); - - return ERROR_OK; -} - -int armv4_5_mmu_handle_mw_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc, target_t *target, armv4_5_mmu_common_t *armv4_5_mmu) -{ - u32 address = 0; - u32 value = 0; - int retval; - u8 value_buf[4]; - - if (target->state != TARGET_HALTED) - { - command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd); - return ERROR_OK; - } - - if (argc < 2) - return ERROR_OK; - - address = strtoul(args[0], NULL, 0); - value = strtoul(args[1], NULL, 0); - - switch (cmd[2]) - { - case 'w': - target_buffer_set_u32(target, value_buf, value); - retval = armv4_5_mmu_write_physical(target, armv4_5_mmu, address, 4, 1, value_buf); - break; - case 'h': - target_buffer_set_u16(target, value_buf, value); - retval = armv4_5_mmu_write_physical(target, armv4_5_mmu, address, 2, 1, value_buf); - break; - case 'b': - value_buf[0] = value; - retval = armv4_5_mmu_write_physical(target, armv4_5_mmu, address, 1, 1, value_buf); - break; - default: - return ERROR_OK; - } - - switch (retval) - { - case ERROR_TARGET_UNALIGNED_ACCESS: - command_print(cmd_ctx, "error: address not aligned"); - break; - case ERROR_TARGET_DATA_ABORT: - command_print(cmd_ctx, "error: access caused data abort, system possibly corrupted"); - break; - case ERROR_TARGET_NOT_HALTED: - command_print(cmd_ctx, "error: target must be halted for memory accesses"); - break; - case ERROR_OK: - break; - default: - command_print(cmd_ctx, "error: unknown error"); - } - - return ERROR_OK; + return retval; }