X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Farmv7a.c;h=5d3976f57522ca111aa657a77003103aee57be0e;hb=6eee0729d79eab496d1d4368a2bae7e4e2d19876;hp=3d94329fd29558f7110a156dcbc6e2452fbfd1f1;hpb=66ee303456910f684244a20a0ac2e958d40b78cb;p=openocd.git

diff --git a/src/target/armv7a.c b/src/target/armv7a.c
index 3d94329fd2..5d3976f575 100644
--- a/src/target/armv7a.c
+++ b/src/target/armv7a.c
@@ -20,14 +20,14 @@
 #include "config.h"
 #endif
 
-#include "replacements.h"
+#include <helper/replacements.h>
 
 #include "armv7a.h"
 #include "arm_disassembler.h"
 
 #include "register.h"
-#include "binarybuffer.h"
-#include "command.h"
+#include <helper/binarybuffer.h>
+#include <helper/command.h>
 
 #include <stdlib.h>
 #include <string.h>
@@ -38,17 +38,48 @@ static void armv7a_show_fault_registers(struct target *target)
 {
 	uint32_t dfsr, ifsr, dfar, ifar;
 	struct armv7a_common *armv7a = target_to_armv7a(target);
-
-	armv7a->read_cp15(target, 0, 0, 5, 0, &dfsr);
-	armv7a->read_cp15(target, 0, 1, 5, 0, &ifsr);
-	armv7a->read_cp15(target, 0, 0, 6, 0, &dfar);
-	armv7a->read_cp15(target, 0, 2, 6, 0, &ifar);
+	struct arm_dpm *dpm = armv7a->armv4_5_common.dpm;
+	int retval;
+
+	retval = dpm->prepare(dpm);
+	if (retval != ERROR_OK)
+		return;
+
+	/* ARMV4_5_MRC(cpnum, op1, r0, CRn, CRm, op2) */
+
+	/* c5/c0 - {data, instruction} fault status registers */
+	retval = dpm->instr_read_data_r0(dpm,
+			ARMV4_5_MRC(15, 0, 0, 5, 0, 0),
+			&dfsr);
+	if (retval != ERROR_OK)
+		goto done;
+
+	retval = dpm->instr_read_data_r0(dpm,
+			ARMV4_5_MRC(15, 0, 0, 5, 0, 1),
+			&ifsr);
+	if (retval != ERROR_OK)
+		goto done;
+
+	/* c6/c0 - {data, instruction} fault address registers */
+	retval = dpm->instr_read_data_r0(dpm,
+			ARMV4_5_MRC(15, 0, 0, 6, 0, 0),
+			&dfar);
+	if (retval != ERROR_OK)
+		goto done;
+
+	retval = dpm->instr_read_data_r0(dpm,
+			ARMV4_5_MRC(15, 0, 0, 6, 0, 2),
+			&ifar);
+	if (retval != ERROR_OK)
+		goto done;
 
 	LOG_USER("Data fault registers        DFSR: %8.8" PRIx32
 			", DFAR: %8.8" PRIx32, dfsr, dfar);
 	LOG_USER("Instruction fault registers IFSR: %8.8" PRIx32
 			", IFAR: %8.8" PRIx32, ifsr, ifar);
 
+done:
+	/* (void) */ dpm->finish(dpm);
 }
 
 int armv7a_arch_state(struct target *target)
@@ -82,6 +113,9 @@ int armv7a_arch_state(struct target *target)
 
 	if (armv4_5->core_mode == ARMV4_5_MODE_ABT)
 		armv7a_show_fault_registers(target);
+	else if (target->debug_reason == DBG_REASON_WATCHPOINT)
+		LOG_USER("Watchpoint triggered at PC %#08x",
+				(unsigned) armv7a->dpm.wp_pc);
 
 	return ERROR_OK;
 }