X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Farmv7a.h;h=7b6219821832c4c4f2569055db39c3bee2783bd3;hb=480ba8ca88e3f12bb60498b35de5fc4b74d0511d;hp=cf938809a221781a986bf4d004a78532d64c0032;hpb=fac9be64d9444138c77ffe45078a85e063593a38;p=openocd.git diff --git a/src/target/armv7a.h b/src/target/armv7a.h index cf938809a2..7b62198218 100644 --- a/src/target/armv7a.h +++ b/src/target/armv7a.h @@ -48,7 +48,7 @@ struct armv7a_l2x_cache { }; struct armv7a_cachesize { - /* cache dimensionning */ + /* cache dimensioning */ uint32_t linelen; uint32_t associativity; uint32_t nsets; @@ -108,6 +108,8 @@ struct armv7a_common { struct adiv5_ap *debug_ap; /* mdir */ uint8_t multi_processor_system; + uint8_t multi_threading_processor; + uint8_t level2_id; uint8_t cluster_id; uint8_t cpu_id; bool is_armv7r; @@ -176,6 +178,9 @@ static inline bool is_armv7a(struct armv7a_common *armv7a) /* See ARMv7a arch spec section C10.8 */ #define CPUDBG_AUTHSTATUS 0xFB8 +/* See ARMv7a arch spec DDI 0406C C11.10 */ +#define CPUDBG_ID_PFR1 0xD24 + /* Masks for Vector Catch register */ #define DBG_VCR_FIQ_MASK ((1 << 31) | (1 << 7)) #define DBG_VCR_IRQ_MASK ((1 << 30) | (1 << 6)) @@ -183,14 +188,14 @@ static inline bool is_armv7a(struct armv7a_common *armv7a) #define DBG_VCR_PREF_ABORT_MASK ((1 << 27) | (1 << 3)) #define DBG_VCR_SVC_MASK ((1 << 26) | (1 << 2)) +/* Masks for Multiprocessor Affinity Register */ +#define MPIDR_MP_EXT (1UL << 31) + int armv7a_arch_state(struct target *target); int armv7a_identify_cache(struct target *target); int armv7a_init_arch_info(struct target *target, struct armv7a_common *armv7a); -int armv7a_mmu_translate_va_pa(struct target *target, uint32_t va, - uint32_t *val, int meminfo); -int armv7a_mmu_translate_va(struct target *target, uint32_t va, uint32_t *val); -int armv7a_handle_cache_info_command(struct command_context *cmd_ctx, +int armv7a_handle_cache_info_command(struct command_invocation *cmd, struct armv7a_cache_common *armv7a_cache); int armv7a_read_ttbcr(struct target *target);