X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Farmv7a.h;h=cb7eb01ff838ad21b35effb6a111e70fd835ce71;hb=a6c4eb03455f6e97fc25183aae249d6ccdcbfb0f;hp=d1834cced970f7071217a64e53d6f85e80d4c9dd;hpb=cd440bd32a120a9b4c2d703d3d16dd52f16edab2;p=openocd.git diff --git a/src/target/armv7a.h b/src/target/armv7a.h index d1834cced9..cb7eb01ff8 100644 --- a/src/target/armv7a.h +++ b/src/target/armv7a.h @@ -63,21 +63,27 @@ struct armv7a_cachesize { uint32_t way_shift; }; -struct armv7a_cache_common { - int ctype; +/* information about one architecture cache at any level */ +struct armv7a_arch_cache { + int ctype; /* cache type, CLIDR encoding */ struct armv7a_cachesize d_u_size; /* data cache */ struct armv7a_cachesize i_size; /* instruction cache */ +}; + +/* common cache information */ +struct armv7a_cache_common { + int info; /* -1 invalid, else valid */ + int loc; /* level of coherency */ uint32_t dminline; /* minimum d-cache linelen */ uint32_t iminline; /* minimum i-cache linelen */ + struct armv7a_arch_cache arch[6]; /* cache info, L1 - L7 */ int i_cache_enabled; int d_u_cache_enabled; int auto_cache_enabled; /* openocd automatic * cache handling */ - /* l2 external unified cache if some */ - void *l2_cache; + /* outer unified cache if some */ + void *outer_cache; int (*flush_all_data_cache)(struct target *target); - int (*display_cache_info)(struct command_context *cmd_ctx, - struct armv7a_cache_common *armv7a_cache); }; struct armv7a_mmu_common { @@ -86,7 +92,6 @@ struct armv7a_mmu_common { uint32_t ttbcr; /* cache for ttbcr register */ uint32_t ttbr_mask[2]; uint32_t ttbr_range[2]; - uint32_t os_border; int (*read_physical_memory)(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer); @@ -99,8 +104,6 @@ struct armv7a_common { int common_magic; struct reg_cache *core_cache; - struct adiv5_dap dap; - /* Core Debug Unit */ struct arm_dpm dpm; uint32_t debug_base; @@ -166,6 +169,7 @@ target_to_armv7a(struct target *target) /* See ARMv7a arch spec section C10.7 */ #define CPUDBG_DSCCR 0x028 +#define CPUDBG_DSMCR 0x02C /* See ARMv7a arch spec section C10.8 */ #define CPUDBG_AUTHSTATUS 0xFB8