X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Farmv7a.h;h=da8ccdf4ed242e900eccbc6db5d68c1f05f8b227;hb=ddea03304310e1342ee127fc7e6507bbfb237ae4;hp=f31a7af84ad97400720dbc98b1f181609ccab7c6;hpb=f320b1228932e33292207d89778125c03379de5d;p=openocd.git

diff --git a/src/target/armv7a.h b/src/target/armv7a.h
index f31a7af84a..da8ccdf4ed 100644
--- a/src/target/armv7a.h
+++ b/src/target/armv7a.h
@@ -19,19 +19,11 @@
 #ifndef ARMV7A_H
 #define ARMV7A_H
 
-#include "arm_adi_v5.h"
-#include "armv4_5.h"
+#include <target/arm_adi_v5.h>
+#include <target/armv4_5.h>
 #include "armv4_5_mmu.h"
 #include "armv4_5_cache.h"
-
-
-typedef enum armv7a_state
-{
-	ARMV7A_STATE_ARM,
-	ARMV7A_STATE_THUMB,
-	ARMV7A_STATE_JAZELLE,
-	ARMV7A_STATE_THUMBEE,
-} armv7a_state_t;
+#include <target/arm_dpm.h>
 
 enum
 {
@@ -39,16 +31,6 @@ enum
 	ARM_CPSR = 16
 }
 ;
-/* offsets into armv4_5 core register cache */
-enum
-{
-	ARMV7A_CPSR = 31,
-	ARMV7A_SPSR_FIQ = 32,
-	ARMV7A_SPSR_IRQ = 33,
-	ARMV7A_SPSR_SVC = 34,
-	ARMV7A_SPSR_ABT = 35,
-	ARMV7A_SPSR_UND = 36
-};
 
 #define ARMV7_COMMON_MAGIC 0x0A450999
 
@@ -64,28 +46,21 @@ enum
 
 struct armv7a_common
 {
+	struct arm armv4_5_common;
 	int common_magic;
 	struct reg_cache *core_cache;
-	enum armv7a_state core_state;
 
 	/* arm adp debug port */
 	struct swjdp_common swjdp_info;
 
 	/* Core Debug Unit */
+	struct arm_dpm dpm;
 	uint32_t debug_base;
 	uint8_t debug_ap;
 	uint8_t memory_ap;
 
 	/* Cache and Memory Management Unit */
 	struct armv4_5_mmu_common armv4_5_mmu;
-	struct arm armv4_5_common;
-
-	int (*read_cp15)(struct target *target,
-			uint32_t op1, uint32_t op2,
-			uint32_t CRn, uint32_t CRm, uint32_t *value);
-	int (*write_cp15)(struct target *target,
-			uint32_t op1, uint32_t op2,
-			uint32_t CRn, uint32_t CRm, uint32_t value);
 
 	int (*examine_debug_reason)(struct target *target);
 	void (*post_debug_entry)(struct target *target);
@@ -102,12 +77,59 @@ target_to_armv7a(struct target *target)
 			armv4_5_common);
 }
 
+/* register offsets from armv7a.debug_base */
+
+/* See ARMv7a arch spec section C10.2 */
+#define CPUDBG_DIDR		0x000
+
+/* See ARMv7a arch spec section C10.3 */
+#define CPUDBG_WFAR		0x018
+/* PCSR at 0x084 -or- 0x0a0 -or- both ... based on flags in DIDR */
+#define CPUDBG_DSCR		0x088
+#define CPUDBG_DRCR		0x090
+#define CPUDBG_PRCR		0x310
+#define CPUDBG_PRSR		0x314
+
+/* See ARMv7a arch spec section C10.4 */
+#define CPUDBG_DTRRX		0x080
+#define CPUDBG_ITR		0x084
+#define CPUDBG_DTRTX		0x08c
+
+/* See ARMv7a arch spec section C10.5 */
+#define CPUDBG_BVR_BASE		0x100
+#define CPUDBG_BCR_BASE		0x140
+#define CPUDBG_WVR_BASE		0x180
+#define CPUDBG_WCR_BASE		0x1C0
+#define CPUDBG_VCR		0x01C
+
+/* See ARMv7a arch spec section C10.6 */
+#define CPUDBG_OSLAR		0x300
+#define CPUDBG_OSLSR		0x304
+#define CPUDBG_OSSRR		0x308
+#define CPUDBG_ECR		0x024
+
+/* See ARMv7a arch spec section C10.7 */
+#define CPUDBG_DSCCR		0x028
+
+/* See ARMv7a arch spec section C10.8 */
+#define CPUDBG_AUTHSTATUS	0xFB8
+
+/* DSCR bit numbers (See ARMv7a arch spec section 12.4.5) */
+#define DSCR_CORE_HALTED	0
+#define DSCR_CORE_RESTARTED	1
+#define DSCR_EXT_INT_EN		13
+#define DSCR_HALT_DBG_MODE	14
+#define DSCR_MON_DBG_MODE	15
+#define DSCR_INSTR_COMP		24
+#define DSCR_DTR_TX_FULL	29
+#define DSCR_DTR_RX_FULL	30
+
 struct armv7a_algorithm
 {
 	int common_magic;
 
 	enum armv4_5_mode core_mode;
-	enum armv7a_state core_state;
+	enum armv4_5_state core_state;
 };
 
 struct armv7a_core_reg
@@ -121,7 +143,8 @@ struct armv7a_core_reg
 int armv7a_arch_state(struct target *target);
 struct reg_cache *armv7a_build_reg_cache(struct target *target,
 		struct armv7a_common *armv7a_common);
-int armv7a_register_commands(struct command_context *cmd_ctx);
 int armv7a_init_arch_info(struct target *target, struct armv7a_common *armv7a);
 
+extern const struct command_registration armv7a_command_handlers[];
+
 #endif /* ARMV4_5_H */