X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Farmv7a_cache_l2x.c;h=c26d051734cb14543949512dd7fd7f117fd5f2c0;hb=7819834ace37ca7f5d1b834c761dfcb9964ef845;hp=13156193848275511bb1cfa51f4f8c83c4e38d17;hpb=cd440bd32a120a9b4c2d703d3d16dd52f16edab2;p=openocd.git
diff --git a/src/target/armv7a_cache_l2x.c b/src/target/armv7a_cache_l2x.c
index 1315619384..c26d051734 100644
--- a/src/target/armv7a_cache_l2x.c
+++ b/src/target/armv7a_cache_l2x.c
@@ -11,6 +11,9 @@
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program. If not, see . *
***************************************************************************/
#ifdef HAVE_CONFIG_H
@@ -24,12 +27,13 @@
#include
#include "target.h"
#include "target_type.h"
+#include "smp.h"
static int arm7a_l2x_sanity_check(struct target *target)
{
struct armv7a_common *armv7a = target_to_armv7a(target);
struct armv7a_l2x_cache *l2x_cache = (struct armv7a_l2x_cache *)
- (armv7a->armv7a_mmu.armv7a_cache.l2_cache);
+ (armv7a->armv7a_mmu.armv7a_cache.outer_cache);
if (target->state != TARGET_HALTED) {
LOG_ERROR("%s: target not halted", __func__);
@@ -46,11 +50,11 @@ static int arm7a_l2x_sanity_check(struct target *target)
/*
* clean and invalidate complete l2x cache
*/
-static int arm7a_l2x_flush_all_data(struct target *target)
+int arm7a_l2x_flush_all_data(struct target *target)
{
struct armv7a_common *armv7a = target_to_armv7a(target);
struct armv7a_l2x_cache *l2x_cache = (struct armv7a_l2x_cache *)
- (armv7a->armv7a_mmu.armv7a_cache.l2_cache);
+ (armv7a->armv7a_mmu.armv7a_cache.outer_cache);
uint32_t l2_way_val;
int retval;
@@ -60,17 +64,17 @@ static int arm7a_l2x_flush_all_data(struct target *target)
l2_way_val = (1 << l2x_cache->way) - 1;
- return target_write_phys_memory(target,
+ return target_write_phys_u32(target,
l2x_cache->base + L2X0_CLEAN_INV_WAY,
- 4, 1, (uint8_t *)&l2_way_val);
+ l2_way_val);
}
-int armv7a_l2x_cache_flush_virt(struct target *target, uint32_t virt,
+int armv7a_l2x_cache_flush_virt(struct target *target, target_addr_t virt,
uint32_t size)
{
struct armv7a_common *armv7a = target_to_armv7a(target);
struct armv7a_l2x_cache *l2x_cache = (struct armv7a_l2x_cache *)
- (armv7a->armv7a_mmu.armv7a_cache.l2_cache);
+ (armv7a->armv7a_mmu.armv7a_cache.outer_cache);
/* FIXME: different controllers have different linelen? */
uint32_t i, linelen = 32;
int retval;
@@ -80,16 +84,15 @@ int armv7a_l2x_cache_flush_virt(struct target *target, uint32_t virt,
return retval;
for (i = 0; i < size; i += linelen) {
- uint32_t pa, offs = virt + i;
+ target_addr_t pa, offs = virt + i;
/* FIXME: use less verbose virt2phys? */
retval = target->type->virt2phys(target, offs, &pa);
if (retval != ERROR_OK)
goto done;
- retval = target_write_phys_memory(target,
- l2x_cache->base + L2X0_CLEAN_INV_LINE_PA,
- 4, 1, (uint8_t *)&pa);
+ retval = target_write_phys_u32(target,
+ l2x_cache->base + L2X0_CLEAN_INV_LINE_PA, pa);
if (retval != ERROR_OK)
goto done;
}
@@ -101,12 +104,12 @@ done:
return retval;
}
-static int armv7a_l2x_cache_inval_virt(struct target *target, uint32_t virt,
+static int armv7a_l2x_cache_inval_virt(struct target *target, target_addr_t virt,
uint32_t size)
{
struct armv7a_common *armv7a = target_to_armv7a(target);
struct armv7a_l2x_cache *l2x_cache = (struct armv7a_l2x_cache *)
- (armv7a->armv7a_mmu.armv7a_cache.l2_cache);
+ (armv7a->armv7a_mmu.armv7a_cache.outer_cache);
/* FIXME: different controllers have different linelen */
uint32_t i, linelen = 32;
int retval;
@@ -116,16 +119,15 @@ static int armv7a_l2x_cache_inval_virt(struct target *target, uint32_t virt,
return retval;
for (i = 0; i < size; i += linelen) {
- uint32_t pa, offs = virt + i;
+ target_addr_t pa, offs = virt + i;
/* FIXME: use less verbose virt2phys? */
retval = target->type->virt2phys(target, offs, &pa);
if (retval != ERROR_OK)
goto done;
- retval = target_write_phys_memory(target,
- l2x_cache->base + L2X0_INV_LINE_PA,
- 4, 1, (uint8_t *)&pa);
+ retval = target_write_phys_u32(target,
+ l2x_cache->base + L2X0_INV_LINE_PA, pa);
if (retval != ERROR_OK)
goto done;
}
@@ -137,12 +139,12 @@ done:
return retval;
}
-static int armv7a_l2x_cache_clean_virt(struct target *target, uint32_t virt,
+static int armv7a_l2x_cache_clean_virt(struct target *target, target_addr_t virt,
unsigned int size)
{
struct armv7a_common *armv7a = target_to_armv7a(target);
struct armv7a_l2x_cache *l2x_cache = (struct armv7a_l2x_cache *)
- (armv7a->armv7a_mmu.armv7a_cache.l2_cache);
+ (armv7a->armv7a_mmu.armv7a_cache.outer_cache);
/* FIXME: different controllers have different linelen */
uint32_t i, linelen = 32;
int retval;
@@ -152,16 +154,15 @@ static int armv7a_l2x_cache_clean_virt(struct target *target, uint32_t virt,
return retval;
for (i = 0; i < size; i += linelen) {
- uint32_t pa, offs = virt + i;
+ target_addr_t pa, offs = virt + i;
/* FIXME: use less verbose virt2phys? */
retval = target->type->virt2phys(target, offs, &pa);
if (retval != ERROR_OK)
goto done;
- retval = target_write_phys_memory(target,
- l2x_cache->base + L2X0_CLEAN_LINE_PA,
- 4, 1, (uint8_t *)&pa);
+ retval = target_write_phys_u32(target,
+ l2x_cache->base + L2X0_CLEAN_LINE_PA, pa);
if (retval != ERROR_OK)
goto done;
}
@@ -173,19 +174,19 @@ done:
return retval;
}
-static int arm7a_handle_l2x_cache_info_command(struct command_context *cmd_ctx,
+static int arm7a_handle_l2x_cache_info_command(struct command_invocation *cmd,
struct armv7a_cache_common *armv7a_cache)
{
struct armv7a_l2x_cache *l2x_cache = (struct armv7a_l2x_cache *)
- (armv7a_cache->l2_cache);
+ (armv7a_cache->outer_cache);
- if (armv7a_cache->ctype == -1) {
- command_print(cmd_ctx, "cache not yet identified");
+ if (armv7a_cache->info == -1) {
+ command_print(cmd, "cache not yet identified");
return ERROR_OK;
}
- command_print(cmd_ctx,
- "L2 unified cache Base Address 0x%" PRIx32 ", %" PRId32 " ways",
+ command_print(cmd,
+ "L2 unified cache Base Address 0x%" PRIx32 ", %" PRIu32 " ways",
l2x_cache->base, l2x_cache->way);
return ERROR_OK;
@@ -194,11 +195,10 @@ static int arm7a_handle_l2x_cache_info_command(struct command_context *cmd_ctx,
static int armv7a_l2x_cache_init(struct target *target, uint32_t base, uint32_t way)
{
struct armv7a_l2x_cache *l2x_cache;
- struct target_list *head = target->head;
- struct target *curr;
+ struct target_list *head;
struct armv7a_common *armv7a = target_to_armv7a(target);
- if (armv7a->armv7a_mmu.armv7a_cache.l2_cache) {
+ if (armv7a->armv7a_mmu.armv7a_cache.outer_cache) {
LOG_ERROR("L2 cache was already initialised\n");
return ERROR_FAIL;
}
@@ -206,21 +206,20 @@ static int armv7a_l2x_cache_init(struct target *target, uint32_t base, uint32_t
l2x_cache = calloc(1, sizeof(struct armv7a_l2x_cache));
l2x_cache->base = base;
l2x_cache->way = way;
- armv7a->armv7a_mmu.armv7a_cache.l2_cache = l2x_cache;
+ armv7a->armv7a_mmu.armv7a_cache.outer_cache = l2x_cache;
/* initialize all targets in this cluster (smp target)
* l2 cache must be configured after smp declaration */
- while (head != (struct target_list *)NULL) {
- curr = head->target;
+ foreach_smp_target(head, target->smp_targets) {
+ struct target *curr = head->target;
if (curr != target) {
armv7a = target_to_armv7a(curr);
- if (armv7a->armv7a_mmu.armv7a_cache.l2_cache) {
+ if (armv7a->armv7a_mmu.armv7a_cache.outer_cache) {
LOG_ERROR("smp target : cache l2 already initialized\n");
return ERROR_FAIL;
}
- armv7a->armv7a_mmu.armv7a_cache.l2_cache = l2x_cache;
+ armv7a->armv7a_mmu.armv7a_cache.outer_cache = l2x_cache;
}
- head = head->next;
}
return ERROR_OK;
}
@@ -235,7 +234,7 @@ COMMAND_HANDLER(arm7a_l2x_cache_info_command)
if (retval)
return retval;
- return arm7a_handle_l2x_cache_info_command(CMD_CTX,
+ return arm7a_handle_l2x_cache_info_command(CMD,
&armv7a->armv7a_mmu.armv7a_cache);
}
@@ -249,7 +248,8 @@ COMMAND_HANDLER(arm7a_l2x_cache_flush_all_command)
COMMAND_HANDLER(arm7a_l2x_cache_flush_virt_cmd)
{
struct target *target = get_current_target(CMD_CTX);
- uint32_t virt, size;
+ target_addr_t virt;
+ uint32_t size;
if (CMD_ARGC == 0 || CMD_ARGC > 2)
return ERROR_COMMAND_SYNTAX_ERROR;
@@ -259,7 +259,7 @@ COMMAND_HANDLER(arm7a_l2x_cache_flush_virt_cmd)
else
size = 1;
- COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], virt);
+ COMMAND_PARSE_ADDRESS(CMD_ARGV[0], virt);
return armv7a_l2x_cache_flush_virt(target, virt, size);
}
@@ -267,7 +267,8 @@ COMMAND_HANDLER(arm7a_l2x_cache_flush_virt_cmd)
COMMAND_HANDLER(arm7a_l2x_cache_inval_virt_cmd)
{
struct target *target = get_current_target(CMD_CTX);
- uint32_t virt, size;
+ target_addr_t virt;
+ uint32_t size;
if (CMD_ARGC == 0 || CMD_ARGC > 2)
return ERROR_COMMAND_SYNTAX_ERROR;
@@ -277,7 +278,7 @@ COMMAND_HANDLER(arm7a_l2x_cache_inval_virt_cmd)
else
size = 1;
- COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], virt);
+ COMMAND_PARSE_ADDRESS(CMD_ARGV[0], virt);
return armv7a_l2x_cache_inval_virt(target, virt, size);
}
@@ -285,7 +286,8 @@ COMMAND_HANDLER(arm7a_l2x_cache_inval_virt_cmd)
COMMAND_HANDLER(arm7a_l2x_cache_clean_virt_cmd)
{
struct target *target = get_current_target(CMD_CTX);
- uint32_t virt, size;
+ target_addr_t virt;
+ uint32_t size;
if (CMD_ARGC == 0 || CMD_ARGC > 2)
return ERROR_COMMAND_SYNTAX_ERROR;
@@ -295,7 +297,7 @@ COMMAND_HANDLER(arm7a_l2x_cache_clean_virt_cmd)
else
size = 1;
- COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], virt);
+ COMMAND_PARSE_ADDRESS(CMD_ARGV[0], virt);
return armv7a_l2x_cache_clean_virt(target, virt, size);
}
@@ -309,7 +311,7 @@ COMMAND_HANDLER(armv7a_l2x_cache_conf_cmd)
if (CMD_ARGC != 2)
return ERROR_COMMAND_SYNTAX_ERROR;
- /* command_print(CMD_CTX, "%s %s", CMD_ARGV[0], CMD_ARGV[1]); */
+ /* command_print(CMD, "%s %s", CMD_ARGV[0], CMD_ARGV[1]); */
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], base);
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], way);
@@ -322,14 +324,14 @@ static const struct command_registration arm7a_l2x_cache_commands[] = {
.name = "conf",
.handler = armv7a_l2x_cache_conf_cmd,
.mode = COMMAND_ANY,
- .help = "configure l2x cache ",
+ .help = "configure l2x cache",
.usage = " ",
},
{
.name = "info",
.handler = arm7a_l2x_cache_info_command,
.mode = COMMAND_ANY,
- .help = "print cache realted information",
+ .help = "print cache related information",
.usage = "",
},
{