X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Farmv7m.c;h=b862cf38f1145d0d7446cdbf40103327829ff0b5;hb=e2b6de3d66bae70cb08fea17f5b66ee875dbb636;hp=f79305f2e081be7370294b8b4d6868a440f82b51;hpb=d47e1b8f362379d8a2307f49e2b42115a3f40524;p=openocd.git diff --git a/src/target/armv7m.c b/src/target/armv7m.c index f79305f2e0..b862cf38f1 100644 --- a/src/target/armv7m.c +++ b/src/target/armv7m.c @@ -42,12 +42,7 @@ char* armv7m_mode_strings[] = { - "Handler", "Thread" -}; - -char* armv7m_state_strings[] = -{ - "Thumb", "Debug" + "Thread", "Thread (User)", "Handler", }; char* armv7m_exception_strings[] = @@ -62,22 +57,10 @@ char* armv7m_core_reg_list[] = "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", "xPSR", "msp", "psp", - /* Registers accessed through MSR instructions */ - /* "apsr", "iapsr", "ipsr", "epsr", */ + /* Registers accessed through special reg 20 */ "primask", "basepri", "faultmask", "control" }; -char* armv7m_core_dbgreg_list[] = -{ - /* Registers accessed through core debug */ - "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", - "sp", "lr", "pc", - "xPSR", "msp", "psp", - /* Registers accessed through MSR instructions */ - /* "dbg_apsr", "iapsr", "ipsr", "epsr", */ - "primask", "basepri", "faultmask", "dbg_control" -}; - u8 armv7m_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; reg_t armv7m_gdb_dummy_fp_reg = @@ -92,6 +75,15 @@ reg_t armv7m_gdb_dummy_fps_reg = "GDB dummy floating-point status register", armv7m_gdb_dummy_fps_value, 0, 1, 32, NULL, 0, NULL, 0 }; +#ifdef ARMV7_GDB_HACKS +u8 armv7m_gdb_dummy_cpsr_value[] = {0, 0, 0, 0}; + +reg_t armv7m_gdb_dummy_cpsr_reg = +{ + "GDB dummy cpsr register", armv7m_gdb_dummy_cpsr_value, 0, 1, 32, NULL, 0, NULL, 0 +}; +#endif + armv7m_core_reg_t armv7m_core_reg_list_arch_info[] = { /* CORE_GP are accesible using the core debug registers */ @@ -116,74 +108,15 @@ armv7m_core_reg_t armv7m_core_reg_list_arch_info[] = {17, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, /* MSP */ {18, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, /* PSP */ - /* CORE_SP are accesible using MSR and MRS instructions */ -#if 0 - {0x00, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* APSR */ - {0x01, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* IAPSR */ - {0x05, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* IPSR */ - {0x06, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* EPSR */ -#endif - - {0x10, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* PRIMASK */ - {0x11, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* BASEPRI */ - {0x13, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* FAULTMASK */ - {0x14, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL} /* CONTROL */ + /* CORE_SP are accesible using coreregister 20 */ + {19, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* PRIMASK */ + {20, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* BASEPRI */ + {21, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* FAULTMASK */ + {22, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL} /* CONTROL */ }; int armv7m_core_reg_arch_type = -1; -/* Keep different contexts for the process being debugged and debug algorithms */ -enum armv7m_runcontext armv7m_get_context(target_t *target) -{ - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - - if (armv7m->process_context == armv7m->core_cache) - return ARMV7M_PROCESS_CONTEXT; - if (armv7m->debug_context == armv7m->core_cache) - return ARMV7M_DEBUG_CONTEXT; - - LOG_ERROR("Invalid runcontext"); - exit(-1); -} - -int armv7m_use_context(target_t *target, enum armv7m_runcontext new_ctx) -{ - int i; - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - - if ((target->state != TARGET_HALTED) && (target->state != TARGET_RESET)) - { - LOG_WARNING("target not halted, switch context "); - return ERROR_TARGET_NOT_HALTED; - } - - if (new_ctx == armv7m_get_context(target)) - return ERROR_OK; - - switch (new_ctx) - { - case ARMV7M_PROCESS_CONTEXT: - armv7m->core_cache = armv7m->process_context; - break; - case ARMV7M_DEBUG_CONTEXT: - armv7m->core_cache = armv7m->debug_context; - break; - default: - LOG_ERROR("Invalid runcontext"); - exit(-1); - } - /* Mark registers in new context as dirty to force reload when run */ - - for (i = 0; i < armv7m->core_cache->num_regs; i++) - { - armv7m->core_cache->reg_list[i].dirty = 1; - } - - return ERROR_OK; -} - int armv7m_restore_context(target_t *target) { int i; @@ -275,7 +208,7 @@ int armv7m_read_core_reg(struct target_s *target, int num) buf_set_u32(armv7m->core_cache->reg_list[num].value, 0, 32, reg_value); armv7m->core_cache->reg_list[num].valid = 1; armv7m->core_cache->reg_list[num].dirty = 0; - + return ERROR_OK; } @@ -333,7 +266,7 @@ int armv7m_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_ for (i = 0; i < 16; i++) { - (*reg_list)[i] = &armv7m->process_context->reg_list[i]; + (*reg_list)[i] = &armv7m->core_cache->reg_list[i]; } for (i = 16; i < 24; i++) @@ -342,11 +275,18 @@ int armv7m_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_ } (*reg_list)[24] = &armv7m_gdb_dummy_fps_reg; + +#ifdef ARMV7_GDB_HACKS + /* use dummy cpsr reg otherwise gdb may try and set the thumb bit */ + (*reg_list)[25] = &armv7m_gdb_dummy_cpsr_reg; /* ARMV7M is always in thumb mode, try to make GDB understand this * if it does not support this arch */ - armv7m->process_context->reg_list[15].value[0] |= 1; - (*reg_list)[25] = &armv7m->process_context->reg_list[ARMV7M_xPSR]; + armv7m->core_cache->reg_list[15].value[0] |= 1; +#else + (*reg_list)[25] = &armv7m->core_cache->reg_list[ARMV7M_xPSR]; +#endif + return ERROR_OK; } @@ -355,10 +295,12 @@ int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_ /* get pointers to arch-specific information */ armv7m_common_t *armv7m = target->arch_info; armv7m_algorithm_t *armv7m_algorithm_info = arch_info; + enum armv7m_mode core_mode = armv7m->core_mode; int retval = ERROR_OK; u32 pc; int i; - + u32 context[ARMV7NUMCOREREGS]; + if (armv7m_algorithm_info->common_magic != ARMV7M_COMMON_MAGIC) { LOG_ERROR("current target isn't an ARMV7M target"); @@ -373,7 +315,12 @@ int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_ /* refresh core register cache */ /* Not needed if core register cache is always consistent with target process state */ - armv7m_use_context(target, ARMV7M_DEBUG_CONTEXT); + for (i = 0; i < ARMV7NUMCOREREGS; i++) + { + if (!armv7m->core_cache->reg_list[i].valid) + armv7m->read_core_reg(target, i); + context[i] = buf_get_u32(armv7m->core_cache->reg_list[i].value, 0, 32); + } for (i = 0; i < num_mem_params; i++) { @@ -401,6 +348,14 @@ int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_ armv7m_set_core_reg(reg, reg_params[i].value); } + if (armv7m_algorithm_info->core_mode != ARMV7M_MODE_ANY) + { + LOG_DEBUG("setting core_mode: 0x%2.2x", armv7m_algorithm_info->core_mode); + buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_CONTROL].value, 0, 1, armv7m_algorithm_info->core_mode); + armv7m->core_cache->reg_list[ARMV7M_CONTROL].dirty = 1; + armv7m->core_cache->reg_list[ARMV7M_CONTROL].valid = 1; + } + /* ARMV7M always runs in Thumb state */ if ((retval = breakpoint_add(target, exit_point, 2, BKPT_SOFT)) != ERROR_OK) { @@ -410,22 +365,22 @@ int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_ /* This code relies on the target specific resume() and poll()->debug_entry() sequence to write register values to the processor and the read them back */ - target->type->resume(target, 0, entry_point, 1, 1); - target->type->poll(target); + target_resume(target, 0, entry_point, 1, 1); + target_poll(target); while (target->state != TARGET_HALTED) { usleep(5000); - target->type->poll(target); + target_poll(target); if ((timeout_ms -= 5) <= 0) { LOG_ERROR("timeout waiting for algorithm to complete, trying to halt target"); - target->type->halt(target); + target_halt(target); timeout_ms = 1000; while (target->state != TARGET_HALTED) { usleep(10000); - target->type->poll(target); + target_poll(target); if ((timeout_ms -= 10) <= 0) { LOG_ERROR("target didn't reenter debug state, exiting"); @@ -452,7 +407,7 @@ int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_ { if (reg_params[i].direction != PARAM_OUT) { - reg_t *reg = register_get_by_name(armv7m->debug_context, reg_params[i].reg_name, 0); + reg_t *reg = register_get_by_name(armv7m->core_cache, reg_params[i].reg_name, 0); if (!reg) { @@ -470,6 +425,16 @@ int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_ } } + for (i = ARMV7NUMCOREREGS-1; i >= 0; i--) + { + LOG_DEBUG("restoring register %s with value 0x%8.8x", armv7m->core_cache->reg_list[i].name, context[i]); + buf_set_u32(armv7m->core_cache->reg_list[i].value, 0, 32, context[i]); + armv7m->core_cache->reg_list[i].valid = 1; + armv7m->core_cache->reg_list[i].dirty = 1; + } + + armv7m->core_mode = core_mode; + return retval; } @@ -478,13 +443,12 @@ int armv7m_arch_state(struct target_s *target) /* get pointers to arch-specific information */ armv7m_common_t *armv7m = target->arch_info; - LOG_USER("target halted in %s state due to %s, current mode: %s %s\nxPSR: 0x%8.8x pc: 0x%8.8x", - armv7m_state_strings[armv7m->core_state], - target_debug_reason_strings[target->debug_reason], - armv7m_mode_strings[armv7m->core_mode], - armv7m_exception_string(armv7m->exception_number), - buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32), - buf_get_u32(armv7m->core_cache->reg_list[15].value, 0, 32)); + LOG_USER("target halted due to %s, current mode: %s %s\nxPSR: 0x%8.8x pc: 0x%8.8x", + target_debug_reason_strings[target->debug_reason], + armv7m_mode_strings[armv7m->core_mode], + armv7m_exception_string(armv7m->exception_number), + buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32), + buf_get_u32(armv7m->core_cache->reg_list[15].value, 0, 32)); return ERROR_OK; } @@ -511,7 +475,6 @@ reg_cache_t *armv7m_build_reg_cache(target_t *target) cache->num_regs = num_regs; (*cache_p) = cache; armv7m->core_cache = cache; - armv7m->process_context = cache; for (i = 0; i < num_regs; i++) { @@ -528,30 +491,6 @@ reg_cache_t *armv7m_build_reg_cache(target_t *target) reg_list[i].arch_type = armv7m_core_reg_arch_type; reg_list[i].arch_info = &arch_info[i]; } - - /* Build the debug context cache*/ - cache = malloc(sizeof(reg_cache_t)); - reg_list = malloc(sizeof(reg_t) * num_regs); - - cache->name = "arm v7m debug registers"; - cache->next = NULL; - cache->reg_list = reg_list; - cache->num_regs = num_regs; - armv7m->debug_context = cache; - armv7m->process_context->next = cache; - - for (i = 0; i < num_regs; i++) - { - reg_list[i].name = armv7m_core_dbgreg_list[i]; - reg_list[i].size = 32; - reg_list[i].value = calloc(1, 4); - reg_list[i].dirty = 0; - reg_list[i].valid = 0; - reg_list[i].bitfield_desc = NULL; - reg_list[i].num_bitfields = 0; - reg_list[i].arch_type = armv7m_core_reg_arch_type; - reg_list[i].arch_info = &arch_info[i]; - } return cache; } @@ -568,7 +507,6 @@ int armv7m_init_arch_info(target_t *target, armv7m_common_t *armv7m) /* register arch-specific functions */ target->arch_info = armv7m; - armv7m->core_state = ARMV7M_STATE_THUMB; armv7m->read_core_reg = armv7m_read_core_reg; armv7m->write_core_reg = armv7m_write_core_reg; @@ -631,7 +569,6 @@ int armv7m_checksum_memory(struct target_s *target, u32 address, u32 count, u32* armv7m_info.common_magic = ARMV7M_COMMON_MAGIC; armv7m_info.core_mode = ARMV7M_MODE_ANY; - armv7m_info.core_state = ARMV7M_STATE_THUMB; init_reg_param(®_params[0], "r0", 32, PARAM_IN_OUT); init_reg_param(®_params[1], "r1", 32, PARAM_OUT); @@ -659,3 +596,64 @@ int armv7m_checksum_memory(struct target_s *target, u32 address, u32 count, u32* return ERROR_OK; } +int armv7m_blank_check_memory(struct target_s *target, u32 address, u32 count, u32* blank) +{ + working_area_t *erase_check_algorithm; + reg_param_t reg_params[3]; + armv7m_algorithm_t armv7m_info; + int retval; + int i; + + u16 erase_check_code[] = + { + /* loop: */ + 0xF810, 0x3B01, /* ldrb r3, [r0], #1 */ + 0xEA02, 0x0203, /* and r2, r2, r3 */ + 0x3901, /* subs r1, r1, #1 */ + 0xD1F9, /* bne loop */ + /* end: */ + 0xE7FE, /* b end */ + }; + + /* make sure we have a working area */ + if (target_alloc_working_area(target, sizeof(erase_check_code), &erase_check_algorithm) != ERROR_OK) + { + return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; + } + + /* convert flash writing code into a buffer in target endianness */ + for (i = 0; i < (sizeof(erase_check_code)/sizeof(u16)); i++) + target_write_u16(target, erase_check_algorithm->address + i*sizeof(u16), erase_check_code[i]); + + armv7m_info.common_magic = ARMV7M_COMMON_MAGIC; + armv7m_info.core_mode = ARMV7M_MODE_ANY; + + init_reg_param(®_params[0], "r0", 32, PARAM_OUT); + buf_set_u32(reg_params[0].value, 0, 32, address); + + init_reg_param(®_params[1], "r1", 32, PARAM_OUT); + buf_set_u32(reg_params[1].value, 0, 32, count); + + init_reg_param(®_params[2], "r2", 32, PARAM_IN_OUT); + buf_set_u32(reg_params[2].value, 0, 32, 0xff); + + if ((retval = target->type->run_algorithm(target, 0, NULL, 3, reg_params, + erase_check_algorithm->address, erase_check_algorithm->address + (sizeof(erase_check_code)-2), 10000, &armv7m_info)) != ERROR_OK) + { + destroy_reg_param(®_params[0]); + destroy_reg_param(®_params[1]); + destroy_reg_param(®_params[2]); + target_free_working_area(target, erase_check_algorithm); + return 0; + } + + *blank = buf_get_u32(reg_params[2].value, 0, 32); + + destroy_reg_param(®_params[0]); + destroy_reg_param(®_params[1]); + destroy_reg_param(®_params[2]); + + target_free_working_area(target, erase_check_algorithm); + + return ERROR_OK; +}