X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Farmv7m.h;h=9ac121ac316be0a058132b6252bb658c91c4281d;hb=HEAD;hp=17e3ff382f05b9bc0fafddb2ba6ace5ea097cf81;hpb=16e17ab1b33c8d40cc28bf621fc7995366a28a8a;p=openocd.git diff --git a/src/target/armv7m.h b/src/target/armv7m.h index 17e3ff382f..2878dd1c76 100644 --- a/src/target/armv7m.h +++ b/src/target/armv7m.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + /*************************************************************************** * Copyright (C) 2005 by Dominic Rath * * Dominic.Rath@gmx.de * @@ -7,213 +9,343 @@ * * * Copyright (C) 2008 by Spencer Oliver * * spen@spen-soft.co.uk * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, write to the * - * Free Software Foundation, Inc., * - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ -#ifndef ARMV7M_COMMON_H -#define ARMV7M_COMMON_H - -#include "arm_adi_v5.h" -/* define for enabling armv7 gdb workarounds */ -#if 1 -#define ARMV7_GDB_HACKS -#endif - -enum armv7m_mode -{ - ARMV7M_MODE_THREAD = 0, - ARMV7M_MODE_USER_THREAD = 1, - ARMV7M_MODE_HANDLER = 2, - ARMV7M_MODE_ANY = -1 +#ifndef OPENOCD_TARGET_ARMV7M_H +#define OPENOCD_TARGET_ARMV7M_H + +#include "arm.h" +#include "armv7m_trace.h" + +struct adiv5_ap; + +extern const int armv7m_psp_reg_map[]; +extern const int armv7m_msp_reg_map[]; + +const char *armv7m_exception_string(int number); + +/* Cortex-M DCRSR.REGSEL selectors */ +enum { + ARMV7M_REGSEL_R0, + ARMV7M_REGSEL_R1, + ARMV7M_REGSEL_R2, + ARMV7M_REGSEL_R3, + + ARMV7M_REGSEL_R4, + ARMV7M_REGSEL_R5, + ARMV7M_REGSEL_R6, + ARMV7M_REGSEL_R7, + + ARMV7M_REGSEL_R8, + ARMV7M_REGSEL_R9, + ARMV7M_REGSEL_R10, + ARMV7M_REGSEL_R11, + + ARMV7M_REGSEL_R12, + ARMV7M_REGSEL_R13, + ARMV7M_REGSEL_R14, + ARMV7M_REGSEL_PC = 15, + + ARMV7M_REGSEL_XPSR = 16, + ARMV7M_REGSEL_MSP, + ARMV7M_REGSEL_PSP, + + ARMV8M_REGSEL_MSP_NS = 0x18, + ARMV8M_REGSEL_PSP_NS, + ARMV8M_REGSEL_MSP_S, + ARMV8M_REGSEL_PSP_S, + ARMV8M_REGSEL_MSPLIM_S, + ARMV8M_REGSEL_PSPLIM_S, + ARMV8M_REGSEL_MSPLIM_NS, + ARMV8M_REGSEL_PSPLIM_NS, + + ARMV7M_REGSEL_PMSK_BPRI_FLTMSK_CTRL = 0x14, + ARMV8M_REGSEL_PMSK_BPRI_FLTMSK_CTRL_S = 0x22, + ARMV8M_REGSEL_PMSK_BPRI_FLTMSK_CTRL_NS = 0x23, + ARMV7M_REGSEL_FPSCR = 0x21, + + /* 32bit Floating-point registers */ + ARMV7M_REGSEL_S0 = 0x40, + ARMV7M_REGSEL_S1, + ARMV7M_REGSEL_S2, + ARMV7M_REGSEL_S3, + ARMV7M_REGSEL_S4, + ARMV7M_REGSEL_S5, + ARMV7M_REGSEL_S6, + ARMV7M_REGSEL_S7, + ARMV7M_REGSEL_S8, + ARMV7M_REGSEL_S9, + ARMV7M_REGSEL_S10, + ARMV7M_REGSEL_S11, + ARMV7M_REGSEL_S12, + ARMV7M_REGSEL_S13, + ARMV7M_REGSEL_S14, + ARMV7M_REGSEL_S15, + ARMV7M_REGSEL_S16, + ARMV7M_REGSEL_S17, + ARMV7M_REGSEL_S18, + ARMV7M_REGSEL_S19, + ARMV7M_REGSEL_S20, + ARMV7M_REGSEL_S21, + ARMV7M_REGSEL_S22, + ARMV7M_REGSEL_S23, + ARMV7M_REGSEL_S24, + ARMV7M_REGSEL_S25, + ARMV7M_REGSEL_S26, + ARMV7M_REGSEL_S27, + ARMV7M_REGSEL_S28, + ARMV7M_REGSEL_S29, + ARMV7M_REGSEL_S30, + ARMV7M_REGSEL_S31, }; -extern char* armv7m_mode_strings[]; +/* offsets into armv7m core register cache */ +enum { + /* for convenience, the first set of indices match + * the Cortex-M DCRSR.REGSEL selectors + */ + ARMV7M_R0 = ARMV7M_REGSEL_R0, + ARMV7M_R1 = ARMV7M_REGSEL_R1, + ARMV7M_R2 = ARMV7M_REGSEL_R2, + ARMV7M_R3 = ARMV7M_REGSEL_R3, + + ARMV7M_R4 = ARMV7M_REGSEL_R4, + ARMV7M_R5 = ARMV7M_REGSEL_R5, + ARMV7M_R6 = ARMV7M_REGSEL_R6, + ARMV7M_R7 = ARMV7M_REGSEL_R7, + + ARMV7M_R8 = ARMV7M_REGSEL_R8, + ARMV7M_R9 = ARMV7M_REGSEL_R9, + ARMV7M_R10 = ARMV7M_REGSEL_R10, + ARMV7M_R11 = ARMV7M_REGSEL_R11, + + ARMV7M_R12 = ARMV7M_REGSEL_R12, + ARMV7M_R13 = ARMV7M_REGSEL_R13, + ARMV7M_R14 = ARMV7M_REGSEL_R14, + ARMV7M_PC = ARMV7M_REGSEL_PC, + + ARMV7M_XPSR = ARMV7M_REGSEL_XPSR, + ARMV7M_MSP = ARMV7M_REGSEL_MSP, + ARMV7M_PSP = ARMV7M_REGSEL_PSP, + + /* following indices are arbitrary, do not match DCRSR.REGSEL selectors */ + + /* A block of container and contained registers follows: + * THE ORDER IS IMPORTANT to the end of the block ! */ + /* working register for packing/unpacking special regs, hidden from gdb */ + ARMV7M_PMSK_BPRI_FLTMSK_CTRL, + + /* WARNING: If you use armv7m_write_core_reg() on one of 4 following + * special registers, the new data go to ARMV7M_PMSK_BPRI_FLTMSK_CTRL + * cache only and are not flushed to CPU HW register. + * To trigger write to CPU HW register, add + * armv7m_write_core_reg(,,ARMV7M_PMSK_BPRI_FLTMSK_CTRL,); + */ + ARMV7M_PRIMASK, + ARMV7M_BASEPRI, + ARMV7M_FAULTMASK, + ARMV7M_CONTROL, + /* The end of block of container and contained registers */ + + /* ARMv8-M specific registers */ + ARMV8M_MSP_NS, + ARMV8M_PSP_NS, + ARMV8M_MSP_S, + ARMV8M_PSP_S, + ARMV8M_MSPLIM_S, + ARMV8M_PSPLIM_S, + ARMV8M_MSPLIM_NS, + ARMV8M_PSPLIM_NS, + + /* A block of container and contained registers follows: + * THE ORDER IS IMPORTANT to the end of the block ! */ + ARMV8M_PMSK_BPRI_FLTMSK_CTRL_S, + ARMV8M_PRIMASK_S, + ARMV8M_BASEPRI_S, + ARMV8M_FAULTMASK_S, + ARMV8M_CONTROL_S, + /* The end of block of container and contained registers */ + + /* A block of container and contained registers follows: + * THE ORDER IS IMPORTANT to the end of the block ! */ + ARMV8M_PMSK_BPRI_FLTMSK_CTRL_NS, + ARMV8M_PRIMASK_NS, + ARMV8M_BASEPRI_NS, + ARMV8M_FAULTMASK_NS, + ARMV8M_CONTROL_NS, + /* The end of block of container and contained registers */ + + /* 64bit Floating-point registers */ + ARMV7M_D0, + ARMV7M_D1, + ARMV7M_D2, + ARMV7M_D3, + ARMV7M_D4, + ARMV7M_D5, + ARMV7M_D6, + ARMV7M_D7, + ARMV7M_D8, + ARMV7M_D9, + ARMV7M_D10, + ARMV7M_D11, + ARMV7M_D12, + ARMV7M_D13, + ARMV7M_D14, + ARMV7M_D15, + + /* Floating-point status register */ + ARMV7M_FPSCR, + + /* for convenience add registers' block delimiters */ + ARMV7M_LAST_REG, + ARMV7M_CORE_FIRST_REG = ARMV7M_R0, + ARMV7M_CORE_LAST_REG = ARMV7M_XPSR, + ARMV7M_FPU_FIRST_REG = ARMV7M_D0, + ARMV7M_FPU_LAST_REG = ARMV7M_FPSCR, + ARMV8M_FIRST_REG = ARMV8M_MSP_NS, + ARMV8M_LAST_REG = ARMV8M_CONTROL_NS, +}; -enum armv7m_regtype -{ - ARMV7M_REGISTER_CORE_GP, - ARMV7M_REGISTER_CORE_SP, - ARMV7M_REGISTER_MEMMAP +enum { + FP_NONE = 0, + FPV4_SP, + FPV5_SP, + FPV5_DP, + FPV5_MVE_I, + FPV5_MVE_F, }; -extern char* armv7m_exception_strings[]; +#define ARMV7M_NUM_CORE_REGS (ARMV7M_CORE_LAST_REG - ARMV7M_CORE_FIRST_REG + 1) -extern char *armv7m_exception_string(int number); +#define ARMV7M_COMMON_MAGIC 0x2A452A45U -/* offsets into armv7m core register cache */ -enum -{ - ARMV7M_PC = 15, - ARMV7M_xPSR = 16, - ARMV7M_MSP, - ARMV7M_PSP, - - /* FIXME the register numbers here are core-specific. Cortex-M3 - * through r1p1 only defines registers up to PSP; see ARM DDI 0337E. - * - * It's r2p0 (see ARM DDI 0337G) which defines the register that's - * called SPEC20 here, with four single-byte fields with CONTROL - * (highest byte), FAULTMASK, BASEPRI, and PRIMASK (lowest byte). - */ - ARMV7M_SPEC20 = 20, - ARMV7NUMCOREREGS -}; +struct armv7m_common { + unsigned int common_magic; -#define ARMV7M_COMMON_MAGIC 0x2A452A45 + struct arm arm; -typedef struct armv7m_common_s -{ - int common_magic; - reg_cache_t *core_cache; - enum armv7m_mode core_mode; int exception_number; - swjdp_common_t swjdp_info; - bool has_spec20; + /* AP this processor is connected to in the DAP */ + struct adiv5_ap *debug_ap; - /* Direct processor core register read and writes */ - int (*load_core_reg_u32)(struct target_s *target, enum armv7m_regtype type, uint32_t num, uint32_t *value); - int (*store_core_reg_u32)(struct target_s *target, enum armv7m_regtype type, uint32_t num, uint32_t value); - /* register cache to processor synchronization */ - int (*read_core_reg)(struct target_s *target, int num); - int (*write_core_reg)(struct target_s *target, int num); + int fp_feature; + uint32_t demcr; - int (*examine_debug_reason)(target_t *target); - void (*pre_debug_entry)(target_t *target); - void (*post_debug_entry)(target_t *target); + /* hla_target uses a high level adapter that does not support all functions */ + bool is_hla_target; - void (*pre_restore_context)(target_t *target); - void (*post_restore_context)(target_t *target); + struct armv7m_trace_config trace_config; - void *arch_info; -} armv7m_common_t; + /* Direct processor core register read and writes */ + int (*load_core_reg_u32)(struct target *target, uint32_t regsel, uint32_t *value); + int (*store_core_reg_u32)(struct target *target, uint32_t regsel, uint32_t value); -typedef struct armv7m_algorithm_s -{ - int common_magic; + int (*examine_debug_reason)(struct target *target); + int (*post_debug_entry)(struct target *target); - enum armv7m_mode core_mode; -} armv7m_algorithm_t; + void (*pre_restore_context)(struct target *target); +}; -typedef struct armv7m_core_reg_s +static inline bool is_armv7m(const struct armv7m_common *armv7m) +{ + return armv7m->common_magic == ARMV7M_COMMON_MAGIC; +} + +/** + * @returns the pointer to the target specific struct + * without matching a magic number. + * Use in target specific service routines, where the correct + * type of arch_info is certain. + */ +static inline struct armv7m_common * +target_to_armv7m(struct target *target) +{ + return container_of(target->arch_info, struct armv7m_common, arm); +} + +/** + * @returns the pointer to the target specific struct + * or NULL if the magic number does not match. + * Use in a flash driver or any place where mismatch of the arch_info + * type can happen. + */ +static inline struct armv7m_common * +target_to_armv7m_safe(struct target *target) { - uint32_t num; - enum armv7m_regtype type; - enum armv7m_mode mode; - target_t *target; - armv7m_common_t *armv7m_common; -} armv7m_core_reg_t; + if (!target) + return NULL; -extern reg_cache_t *armv7m_build_reg_cache(target_t *target); -extern enum armv7m_mode armv7m_number_to_mode(int number); -extern int armv7m_mode_to_number(enum armv7m_mode mode); + if (!target->arch_info) + return NULL; -extern int armv7m_arch_state(struct target_s *target); -extern int armv7m_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_size); + /* Check the parent type first to prevent peeking memory too far + * from arch_info pointer */ + if (!is_arm(target_to_arm(target))) + return NULL; -extern int armv7m_register_commands(struct command_context_s *cmd_ctx); -extern int armv7m_init_arch_info(target_t *target, armv7m_common_t *armv7m); + struct armv7m_common *armv7m = target_to_armv7m(target); + if (!is_armv7m(armv7m)) + return NULL; -extern int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info); + return armv7m; +} -extern int armv7m_invalidate_core_regs(target_t *target); +struct armv7m_algorithm { + unsigned int common_magic; -extern int armv7m_restore_context(target_t *target); + enum arm_mode core_mode; -extern int armv7m_checksum_memory(struct target_s *target, uint32_t address, uint32_t count, uint32_t* checksum); -extern int armv7m_blank_check_memory(struct target_s *target, uint32_t address, uint32_t count, uint32_t* blank); + uint32_t context[ARMV7M_LAST_REG]; /* ARMV7M_NUM_REGS */ +}; -/* Thumb mode instructions - */ +struct reg_cache *armv7m_build_reg_cache(struct target *target); +void armv7m_free_reg_cache(struct target *target); -/* Move to Register from Special Register (Thumb mode) 32 bit Thumb2 instruction - * Rd: destination register - * SYSm: source special register - */ -#define ARMV7M_T_MRS(Rd, SYSm) ((0xF3EF) | ((0x8000 | (Rd << 8) | SYSm) << 16)) +enum armv7m_mode armv7m_number_to_mode(int number); +int armv7m_mode_to_number(enum armv7m_mode mode); -/* Move from Register from Special Register (Thumb mode) 32 bit Thumb2 instruction - * Rd: source register - * SYSm: destination special register - */ -#define ARMV7M_T_MSR(SYSm, Rn) ((0xF380 | (Rn << 8)) | ((0x8800 | SYSm) << 16)) +int armv7m_arch_state(struct target *target); +int armv7m_get_gdb_reg_list(struct target *target, + struct reg **reg_list[], int *reg_list_size, + enum target_register_class reg_class); -/* Change Processor State. The instruction modifies the PRIMASK and FAULTMASK - * special-purpose register values (Thumb mode) 16 bit Thumb2 instruction - * Rd: source register - * IF: - */ -#define I_FLAG 2 -#define F_FLAG 1 -#define ARMV7M_T_CPSID(IF) ((0xB660 | (1 << 8) | (IF&0x3)) | ((0xB660 | (1 << 8) | (IF&0x3)) << 16)) -#define ARMV7M_T_CPSIE(IF) ((0xB660 | (0 << 8) | (IF&0x3)) | ((0xB660 | (0 << 8) | (IF&0x3)) << 16)) +int armv7m_init_arch_info(struct target *target, struct armv7m_common *armv7m); -/* Breakpoint (Thumb mode) v5 onwards - * Im: immediate value used by debugger - */ -#define ARMV7M_T_BKPT(Im) ((0xBE00 | Im) | ((0xBE00 | Im) << 16)) +int armv7m_run_algorithm(struct target *target, + int num_mem_params, struct mem_param *mem_params, + int num_reg_params, struct reg_param *reg_params, + target_addr_t entry_point, target_addr_t exit_point, + unsigned int timeout_ms, void *arch_info); -/* Store register (Thumb mode) - * Rd: source register - * Rn: base register - */ -#define ARMV7M_T_STR(Rd, Rn) ((0x6000 | Rd | (Rn << 3)) | ((0x6000 | Rd | (Rn << 3)) << 16)) +int armv7m_start_algorithm(struct target *target, + int num_mem_params, struct mem_param *mem_params, + int num_reg_params, struct reg_param *reg_params, + target_addr_t entry_point, target_addr_t exit_point, + void *arch_info); -/* Load register (Thumb state) - * Rd: destination register - * Rn: base register - */ -#define ARMV7M_T_LDR(Rd, Rn) ((0x6800 | (Rn << 3) | Rd) | ((0x6800 | (Rn << 3) | Rd) << 16)) +int armv7m_wait_algorithm(struct target *target, + int num_mem_params, struct mem_param *mem_params, + int num_reg_params, struct reg_param *reg_params, + target_addr_t exit_point, unsigned int timeout_ms, + void *arch_info); -/* Load multiple (Thumb state) - * Rn: base register - * List: for each bit in list: store register - */ -#define ARMV7M_T_LDMIA(Rn, List) ((0xc800 | (Rn << 8) | List) | ((0xc800 | (Rn << 8) | List) << 16)) +int armv7m_invalidate_core_regs(struct target *target); -/* Load register with PC relative addressing - * Rd: register to load - */ -#define ARMV7M_T_LDR_PCREL(Rd) ((0x4800 | (Rd << 8)) | ((0x4800 | (Rd << 8)) << 16)) +int armv7m_restore_context(struct target *target); -/* Move hi register (Thumb mode) - * Rd: destination register - * Rm: source register - */ -#define ARMV7M_T_MOV(Rd, Rm) ((0x4600 | (Rd & 0x7) | ((Rd & 0x8) << 4) | ((Rm & 0x7) << 3) | ((Rm & 0x8) << 3)) | ((0x4600 | (Rd & 0x7) | ((Rd & 0x8) << 4) | ((Rm & 0x7) << 3) | ((Rm & 0x8) << 3)) << 16)) +uint32_t armv7m_map_id_to_regsel(unsigned int arm_reg_id); -/* No operation (Thumb mode) - */ -#define ARMV7M_T_NOP (0x46c0 | (0x46c0 << 16)) +bool armv7m_map_reg_packing(unsigned int arm_reg_id, + unsigned int *reg32_id, uint32_t *offset); -/* Move immediate to register (Thumb state) - * Rd: destination register - * Im: 8-bit immediate value - */ -#define ARMV7M_T_MOV_IM(Rd, Im) ((0x2000 | (Rd << 8) | Im) | ((0x2000 | (Rd << 8) | Im) << 16)) +int armv7m_checksum_memory(struct target *target, + target_addr_t address, uint32_t count, uint32_t *checksum); +int armv7m_blank_check_memory(struct target *target, + struct target_memory_check_block *blocks, int num_blocks, uint8_t erased_value); -/* Branch and Exchange - * Rm: register containing branch target - */ -#define ARMV7M_T_BX(Rm) ((0x4700 | (Rm << 3)) | ((0x4700 | (Rm << 3)) << 16)) +int armv7m_maybe_skip_bkpt_inst(struct target *target, bool *inst_found); -/* Branch (Thumb state) - * Imm: Branch target - */ -#define ARMV7M_T_B(Imm) ((0xe000 | Imm) | ((0xe000 | Imm) << 16)) +extern const struct command_registration armv7m_command_handlers[]; -#endif /* ARMV7M_H */ +#endif /* OPENOCD_TARGET_ARMV7M_H */