X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Farmv8_cache.c;h=7f610c953536714f3e36eecbce102929bb4f282c;hb=9981093ce076a388700b2f307a9dc79e14a6e0f1;hp=f496c3cf0519cb14c90d63cb2eba74d5855c94e0;hpb=b69750fd0ded4ee19861673106761627d88734e4;p=openocd.git

diff --git a/src/target/armv8_cache.c b/src/target/armv8_cache.c
index f496c3cf05..7f610c9535 100644
--- a/src/target/armv8_cache.c
+++ b/src/target/armv8_cache.c
@@ -49,8 +49,9 @@ static int armv8_i_cache_sanity_check(struct armv8_common *armv8)
 	return ERROR_TARGET_INVALID;
 }
 
-static int armv8_cache_d_inner_flush_level(struct arm_dpm *dpm, struct armv8_cachesize *size, int cl)
+static int armv8_cache_d_inner_flush_level(struct armv8_common *armv8, struct armv8_cachesize *size, int cl)
 {
+	struct arm_dpm *dpm = armv8->arm.dpm;
 	int retval = ERROR_OK;
 	int32_t c_way, c_index = size->index;
 
@@ -65,7 +66,7 @@ static int armv8_cache_d_inner_flush_level(struct arm_dpm *dpm, struct armv8_cac
 			 * line by Set/Way.
 			 */
 			retval = dpm->instr_write_data_r0(dpm,
-					ARMV8_SYS(SYSTEM_DCCISW, 0), value);
+					armv8_opcode(armv8, ARMV8_OPC_DCCISW), value);
 			if (retval != ERROR_OK)
 				goto done;
 			c_way -= 1;
@@ -97,7 +98,7 @@ static int armv8_cache_d_inner_clean_inval_all(struct armv8_common *armv8)
 		if (cache->arch[cl].ctype < CACHE_LEVEL_HAS_D_CACHE)
 			continue;
 
-		armv8_cache_d_inner_flush_level(dpm, &cache->arch[cl].d_u_size, cl);
+		armv8_cache_d_inner_flush_level(armv8, &cache->arch[cl].d_u_size, cl);
 	}
 
 	retval = dpm->finish(dpm);
@@ -133,7 +134,7 @@ int armv8_cache_d_inner_flush_virt(struct armv8_common *armv8, target_addr_t va,
 		/* DC CIVAC */
 		/* Aarch32: DCCIMVAC: ARMV4_5_MCR(15, 0, 0, 7, 14, 1) */
 		retval = dpm->instr_write_data_r0_64(dpm,
-				ARMV8_SYS(SYSTEM_DCCIVAC, 0), va_line);
+				armv8_opcode(armv8, ARMV8_OPC_DCCIVAC), va_line);
 		if (retval != ERROR_OK)
 			goto done;
 		va_line += linelen;
@@ -171,7 +172,7 @@ int armv8_cache_i_inner_inval_virt(struct armv8_common *armv8, target_addr_t va,
 	while (va_line < va_end) {
 		/* IC IVAU - Invalidate instruction cache by VA to PoU. */
 		retval = dpm->instr_write_data_r0_64(dpm,
-				ARMV8_SYS(SYSTEM_ICIVAU, 0), va_line);
+				armv8_opcode(armv8, ARMV8_OPC_ICIVAU), va_line);
 		if (retval != ERROR_OK)
 			goto done;
 		va_line += linelen;
@@ -266,17 +267,18 @@ static int  armv8_flush_all_data(struct target *target)
 
 static int get_cache_info(struct arm_dpm *dpm, int cl, int ct, uint32_t *cache_reg)
 {
+	struct armv8_common *armv8 = dpm->arm->arch_info;
 	int retval = ERROR_OK;
 
 	/*  select cache level */
 	retval = dpm->instr_write_data_r0(dpm,
-			ARMV8_MSR_GP(SYSTEM_CSSELR, 0),
+			armv8_opcode(armv8, WRITE_REG_CSSELR),
 			(cl << 1) | (ct == 1 ? 1 : 0));
 	if (retval != ERROR_OK)
 		goto done;
 
 	retval = dpm->instr_read_data_r0(dpm,
-			ARMV8_MRS(SYSTEM_CCSIDR, 0),
+			armv8_opcode(armv8, READ_REG_CCSIDR),
 			cache_reg);
  done:
 	return retval;
@@ -319,7 +321,8 @@ int armv8_identify_cache(struct armv8_common *armv8)
 		goto done;
 
 	/* retrieve CTR */
-	retval = dpm->instr_read_data_r0(dpm, ARMV8_MRS(SYSTEM_CTR, 0), &ctr);
+	retval = dpm->instr_read_data_r0(dpm,
+			armv8_opcode(armv8, READ_REG_CTR), &ctr);
 	if (retval != ERROR_OK)
 		goto done;
 
@@ -329,7 +332,8 @@ int armv8_identify_cache(struct armv8_common *armv8)
 		 ctr, cache->iminline, cache->dminline);
 
 	/*  retrieve CLIDR */
-	retval = dpm->instr_read_data_r0(dpm, ARMV8_MRS(SYSTEM_CLIDR, 0), &clidr);
+	retval = dpm->instr_read_data_r0(dpm,
+			armv8_opcode(armv8, READ_REG_CLIDR), &clidr);
 	if (retval != ERROR_OK)
 		goto done;
 
@@ -338,7 +342,8 @@ int armv8_identify_cache(struct armv8_common *armv8)
 
 	/*  retrieve selected cache for later restore
 	 *  MRC p15, 2,<Rd>, c0, c0, 0; Read CSSELR */
-	retval = dpm->instr_read_data_r0(dpm, ARMV8_MRS(SYSTEM_CSSELR, 0), &csselr);
+	retval = dpm->instr_read_data_r0(dpm,
+			armv8_opcode(armv8, READ_REG_CSSELR), &csselr);
 	if (retval != ERROR_OK)
 		goto done;
 
@@ -396,7 +401,8 @@ int armv8_identify_cache(struct armv8_common *armv8)
 	}
 
 	/*  restore selected cache  */
-	dpm->instr_write_data_r0(dpm, ARMV8_MSR_GP(SYSTEM_CSSELR, 0), csselr);
+	dpm->instr_write_data_r0(dpm,
+			armv8_opcode(armv8, WRITE_REG_CSSELR), csselr);
 	if (retval != ERROR_OK)
 		goto done;