X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Farmv8_opcodes.h;h=3fda29668a27dac00376d34d08198db0249f4dfa;hb=de58a6d1b7407afe92a4d1b6e62b7fa886426443;hp=b489d57df329265b1be4c4b9f2882c7f91cde2e7;hpb=62c2eb4b284e0a3deb2aad7163354200bd93e634;p=openocd.git

diff --git a/src/target/armv8_opcodes.h b/src/target/armv8_opcodes.h
index b489d57df3..3fda29668a 100644
--- a/src/target/armv8_opcodes.h
+++ b/src/target/armv8_opcodes.h
@@ -17,11 +17,6 @@
 
 #include "arm_opcodes.h"
 
-/* ARM V8 Move from system register to general purpose register
- * R = 1: SPSR R = 0: CPSR
- * Rn: target register
- */
-#define SYSTEM_CUREL			0b1100001000010010
 #define SYSTEM_CUREL_MASK		0xC0
 #define SYSTEM_CUREL_SHIFT		6
 #define SYSTEM_CUREL_EL0		0x0
@@ -47,6 +42,10 @@
 #define SYSTEM_ELR_EL2			0b1110001000000001
 #define SYSTEM_ELR_EL3			0b1111001000000001
 
+#define SYSTEM_SCTLR_EL1	0b1100000010000000
+#define SYSTEM_SCTLR_EL2	0b1110000010000000
+#define SYSTEM_SCTLR_EL3	0b1111000010000000
+
 #define SYSTEM_FPCR			0b1101101000100000
 #define SYSTEM_FPSR			0b1101101000100001
 #define SYSTEM_DAIF			0b1101101000010001
@@ -135,6 +134,8 @@
 
 #define ARMV8_DSB_SY				0xd5033F9F
 #define ARMV8_DSB_SY_T1				0xf3bf8f4f
+#define ARMV8_ISB				0xd5033fdf
+#define ARMV8_ISB_SY_T1				0xf3bf8f6f
 
 #define ARMV8_MRS(System, Rt)	(0xd5300000 | ((System) << 5) | (Rt))
 /* ARM V8 Move to system register. */
@@ -151,12 +152,29 @@
 
 #define ARMV8_BKPT(Im) (0xD4200000 | ((Im & 0xffff) << 5))
 #define ARMV8_HLT(Im) (0x0D4400000 | ((Im & 0xffff) << 5))
+#define ARMV8_HLT_A1(Im) (0xE1000070 | ((Im & 0xFFF0) << 4) | (Im & 0xF))
 
 #define ARMV8_MOVFSP_64(Rt) ((1 << 31) | 0x11000000 | (0x1f << 5) | (Rt))
 #define ARMV8_MOVTSP_64(Rt) ((1 << 31) | 0x11000000 | (Rt << 5) | (0x1F))
 #define ARMV8_MOVFSP_32(Rt) (0x11000000 | (0x1f << 5) | (Rt))
 #define ARMV8_MOVTSP_32(Rt) (0x11000000 | (Rt << 5) | (0x1F))
 
+#define ARMV8_LDRB_IP(Rd, Rn) (0x38401400 | (Rn << 5) | Rd)
+#define ARMV8_LDRH_IP(Rd, Rn) (0x78402400 | (Rn << 5) | Rd)
+#define ARMV8_LDRW_IP(Rd, Rn) (0xb8404400 | (Rn << 5) | Rd)
+
+#define ARMV8_STRB_IP(Rd, Rn) (0x38001400 | (Rn << 5) | Rd)
+#define ARMV8_STRH_IP(Rd, Rn) (0x78002400 | (Rn << 5) | Rd)
+#define ARMV8_STRW_IP(Rd, Rn) (0xb8004400 | (Rn << 5) | Rd)
+
+#define ARMV8_MOV_GPR_VFP(Rd, Rn, Index) (0x4e083c00 | (Index << 20) | (Rn << 5) | Rd)
+#define ARMV8_MOV_VFP_GPR(Rd, Rn, Index) (0x4e081c00 | (Index << 20) | (Rn << 5) | Rd)
+
+#define ARMV8_MRS_FPCR(Rt)	(0xd53b4400 | (Rt))
+#define ARMV8_MRS_FPSR(Rt)	(0xd53b4420 | (Rt))
+#define ARMV8_MSR_FPCR(Rt)	(0xd51b4400 | (Rt))
+#define ARMV8_MSR_FPSR(Rt)	(0xd51b4420 | (Rt))
+
 #define ARMV8_SYS(System, Rt) (0xD5080000 | ((System) << 5) | Rt)
 
 enum armv8_opcode {
@@ -173,6 +191,17 @@ enum armv8_opcode {
 	ARMV8_OPC_DSB_SY,
 	ARMV8_OPC_DCPS,
 	ARMV8_OPC_DRPS,
+	ARMV8_OPC_ISB_SY,
+	ARMV8_OPC_DCCISW,
+	ARMV8_OPC_DCCIVAC,
+	ARMV8_OPC_ICIVAU,
+	ARMV8_OPC_HLT,
+	ARMV8_OPC_STRB_IP,
+	ARMV8_OPC_STRH_IP,
+	ARMV8_OPC_STRW_IP,
+	ARMV8_OPC_LDRB_IP,
+	ARMV8_OPC_LDRH_IP,
+	ARMV8_OPC_LDRW_IP,
 	ARMV8_OPC_NUM,
 };