X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Fcortex_a.c;h=862fd554f87db89938a07d61c8e520e630191b30;hb=c527882121e3cc3d7cba5360c20928317c19a5cf;hp=0c2247ef588eb8ffa356f4088334e20653ffbf30;hpb=4668bd264cfe64c3e3ddd0f75cb5bf2e5e85f717;p=openocd.git diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c index 0c2247ef58..862fd554f8 100755 --- a/src/target/cortex_a.c +++ b/src/target/cortex_a.c @@ -87,7 +87,7 @@ static int cortex_a8_restore_cp15_control_reg(struct target* target) { cortex_a8->cp15_control_reg_curr = cortex_a8->cp15_control_reg; //LOG_INFO("cp15_control_reg: %8.8" PRIx32, cortex_a8->cp15_control_reg); - retval = armv7a->armv4_5_common.mcr(target, 15, + retval = armv7a->arm.mcr(target, 15, 0, 0, /* op1, op2 */ 1, 0, /* CRn, CRm */ cortex_a8->cp15_control_reg); @@ -103,22 +103,22 @@ static int cortex_a8_check_address(struct target *target, uint32_t address) struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target); uint32_t os_border = armv7a->armv7a_mmu.os_border; if ((address < os_border) && - (armv7a->armv4_5_common.core_mode == ARM_MODE_SVC)){ + (armv7a->arm.core_mode == ARM_MODE_SVC)) { LOG_ERROR("%x access in userspace and target in supervisor",address); return ERROR_FAIL; } if ((address >= os_border) && - ( cortex_a8->curr_mode != ARM_MODE_SVC)){ - dpm_modeswitch(&armv7a->dpm, ARM_MODE_SVC); - cortex_a8->curr_mode = ARM_MODE_SVC; + (cortex_a8->curr_mode != ARM_MODE_SVC)) { + dpm_modeswitch(&armv7a->dpm, ARM_MODE_SVC); + cortex_a8->curr_mode = ARM_MODE_SVC; LOG_INFO("%x access in kernel space and target not in supervisor", address); return ERROR_OK; } if ((address < os_border) && - (cortex_a8->curr_mode == ARM_MODE_SVC)){ - dpm_modeswitch(&armv7a->dpm, ARM_MODE_ANY); - cortex_a8->curr_mode = ARM_MODE_ANY; + (cortex_a8->curr_mode == ARM_MODE_SVC)) { + dpm_modeswitch(&armv7a->dpm, ARM_MODE_ANY); + cortex_a8->curr_mode = ARM_MODE_ANY; } return ERROR_OK; } @@ -141,7 +141,7 @@ static int cortex_a8_mmu_modify(struct target *target, int enable) if (!(cortex_a8->cp15_control_reg_curr & 0x1U)) { cortex_a8->cp15_control_reg_curr |= 0x1U; - retval = armv7a->armv4_5_common.mcr(target, 15, + retval = armv7a->arm.mcr(target, 15, 0, 0, /* op1, op2 */ 1, 0, /* CRn, CRm */ cortex_a8->cp15_control_reg_curr); @@ -160,7 +160,7 @@ static int cortex_a8_mmu_modify(struct target *target, int enable) if ( (cortex_a8->cp15_control_reg_curr & 0x1U)) { cortex_a8->cp15_control_reg_curr &= ~0x1U; - retval = armv7a->armv4_5_common.mcr(target, 15, + retval = armv7a->arm.mcr(target, 15, 0, 0, /* op1, op2 */ 1, 0, /* CRn, CRm */ cortex_a8->cp15_control_reg_curr); @@ -175,7 +175,7 @@ static int cortex_a8_mmu_modify(struct target *target, int enable) static int cortex_a8_init_debug_access(struct target *target) { struct armv7a_common *armv7a = target_to_armv7a(target); - struct adiv5_dap *swjdp = armv7a->armv4_5_common.dap; + struct adiv5_dap *swjdp = armv7a->arm.dap; int retval; uint32_t dummy; @@ -223,7 +223,7 @@ static int cortex_a8_exec_opcode(struct target *target, uint32_t dscr; int retval; struct armv7a_common *armv7a = target_to_armv7a(target); - struct adiv5_dap *swjdp = armv7a->armv4_5_common.dap; + struct adiv5_dap *swjdp = armv7a->arm.dap; dscr = dscr_p ? *dscr_p : 0; @@ -285,7 +285,7 @@ static int cortex_a8_read_regs_through_mem(struct target *target, uint32_t addre { int retval = ERROR_OK; struct armv7a_common *armv7a = target_to_armv7a(target); - struct adiv5_dap *swjdp = armv7a->armv4_5_common.dap; + struct adiv5_dap *swjdp = armv7a->arm.dap; retval = cortex_a8_dap_read_coreregister_u32(target, regfile, 0); if (retval != ERROR_OK) @@ -310,7 +310,7 @@ static int cortex_a8_dap_read_coreregister_u32(struct target *target, uint8_t reg = regnum&0xFF; uint32_t dscr = 0; struct armv7a_common *armv7a = target_to_armv7a(target); - struct adiv5_dap *swjdp = armv7a->armv4_5_common.dap; + struct adiv5_dap *swjdp = armv7a->arm.dap; if (reg > 17) return retval; @@ -380,7 +380,7 @@ static int cortex_a8_dap_write_coreregister_u32(struct target *target, uint8_t Rd = regnum&0xFF; uint32_t dscr; struct armv7a_common *armv7a = target_to_armv7a(target); - struct adiv5_dap *swjdp = armv7a->armv4_5_common.dap; + struct adiv5_dap *swjdp = armv7a->arm.dap; LOG_DEBUG("register %i, value 0x%08" PRIx32, regnum, value); @@ -464,7 +464,7 @@ static int cortex_a8_dap_write_memap_register_u32(struct target *target, uint32_ { int retval; struct armv7a_common *armv7a = target_to_armv7a(target); - struct adiv5_dap *swjdp = armv7a->armv4_5_common.dap; + struct adiv5_dap *swjdp = armv7a->arm.dap; retval = mem_ap_sel_write_atomic_u32(swjdp, swjdp_debugap, address, value); @@ -490,14 +490,14 @@ static inline struct cortex_a8_common *dpm_to_a8(struct arm_dpm *dpm) static int cortex_a8_write_dcc(struct cortex_a8_common *a8, uint32_t data) { LOG_DEBUG("write DCC 0x%08" PRIx32, data); - return mem_ap_sel_write_u32(a8->armv7a_common.armv4_5_common.dap, + return mem_ap_sel_write_u32(a8->armv7a_common.arm.dap, swjdp_debugap,a8->armv7a_common.debug_base + CPUDBG_DTRRX, data); } static int cortex_a8_read_dcc(struct cortex_a8_common *a8, uint32_t *data, uint32_t *dscr_p) { - struct adiv5_dap *swjdp = a8->armv7a_common.armv4_5_common.dap; + struct adiv5_dap *swjdp = a8->armv7a_common.arm.dap; uint32_t dscr = DSCR_INSTR_COMP; int retval; @@ -534,7 +534,7 @@ static int cortex_a8_read_dcc(struct cortex_a8_common *a8, uint32_t *data, static int cortex_a8_dpm_prepare(struct arm_dpm *dpm) { struct cortex_a8_common *a8 = dpm_to_a8(dpm); - struct adiv5_dap *swjdp = a8->armv7a_common.armv4_5_common.dap; + struct adiv5_dap *swjdp = a8->armv7a_common.arm.dap; uint32_t dscr; int retval; @@ -561,7 +561,7 @@ static int cortex_a8_dpm_prepare(struct arm_dpm *dpm) LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32, dscr); /* Clear DCCRX */ retval = cortex_a8_exec_opcode( - a8->armv7a_common.armv4_5_common.target, + a8->armv7a_common.arm.target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0), &dscr); if (retval != ERROR_OK) @@ -589,7 +589,7 @@ static int cortex_a8_instr_write_data_dcc(struct arm_dpm *dpm, return retval; return cortex_a8_exec_opcode( - a8->armv7a_common.armv4_5_common.target, + a8->armv7a_common.arm.target, opcode, &dscr); } @@ -607,7 +607,7 @@ static int cortex_a8_instr_write_data_r0(struct arm_dpm *dpm, /* DCCRX to R0, "MCR p14, 0, R0, c0, c5, 0", 0xEE000E15 */ retval = cortex_a8_exec_opcode( - a8->armv7a_common.armv4_5_common.target, + a8->armv7a_common.arm.target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0), &dscr); if (retval != ERROR_OK) @@ -615,7 +615,7 @@ static int cortex_a8_instr_write_data_r0(struct arm_dpm *dpm, /* then the opcode, taking data from R0 */ retval = cortex_a8_exec_opcode( - a8->armv7a_common.armv4_5_common.target, + a8->armv7a_common.arm.target, opcode, &dscr); @@ -642,7 +642,7 @@ static int cortex_a8_instr_read_data_dcc(struct arm_dpm *dpm, /* the opcode, writing data to DCC */ retval = cortex_a8_exec_opcode( - a8->armv7a_common.armv4_5_common.target, + a8->armv7a_common.arm.target, opcode, &dscr); if (retval != ERROR_OK) @@ -661,7 +661,7 @@ static int cortex_a8_instr_read_data_r0(struct arm_dpm *dpm, /* the opcode, writing data to R0 */ retval = cortex_a8_exec_opcode( - a8->armv7a_common.armv4_5_common.target, + a8->armv7a_common.arm.target, opcode, &dscr); if (retval != ERROR_OK) @@ -669,7 +669,7 @@ static int cortex_a8_instr_read_data_r0(struct arm_dpm *dpm, /* write R0 to DCC */ retval = cortex_a8_exec_opcode( - a8->armv7a_common.armv4_5_common.target, + a8->armv7a_common.arm.target, ARMV4_5_MCR(14, 0, 0, 0, 5, 0), &dscr); if (retval != ERROR_OK) @@ -743,7 +743,7 @@ static int cortex_a8_dpm_setup(struct cortex_a8_common *a8, uint32_t didr) struct arm_dpm *dpm = &a8->armv7a_common.dpm; int retval; - dpm->arm = &a8->armv7a_common.armv4_5_common; + dpm->arm = &a8->armv7a_common.arm; dpm->didr = didr; dpm->prepare = cortex_a8_dpm_prepare; @@ -824,7 +824,7 @@ static int cortex_a8_poll(struct target *target) uint32_t dscr; struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target); struct armv7a_common *armv7a = &cortex_a8->armv7a_common; - struct adiv5_dap *swjdp = armv7a->armv4_5_common.dap; + struct adiv5_dap *swjdp = armv7a->arm.dap; enum target_state prev_target_state = target->state; // toggle to another core is done by gdb as follow // maint packet J core_id @@ -907,7 +907,7 @@ static int cortex_a8_halt(struct target *target) int retval = ERROR_OK; uint32_t dscr; struct armv7a_common *armv7a = target_to_armv7a(target); - struct adiv5_dap *swjdp = armv7a->armv4_5_common.dap; + struct adiv5_dap *swjdp = armv7a->arm.dap; /* * Tell the core to be halted by writing DRCR with 0x1 @@ -958,7 +958,7 @@ static int cortex_a8_internal_restore(struct target *target, int current, uint32_t *address, int handle_breakpoints, int debug_execution) { struct armv7a_common *armv7a = target_to_armv7a(target); - struct arm *armv4_5 = &armv7a->armv4_5_common; + struct arm *arm = &armv7a->arm; int retval; uint32_t resume_pc; @@ -987,7 +987,7 @@ static int cortex_a8_internal_restore(struct target *target, int current, #endif /* current = 1: continue on current pc, otherwise continue at
*/ - resume_pc = buf_get_u32(armv4_5->pc->value, 0, 32); + resume_pc = buf_get_u32(arm->pc->value, 0, 32); if (!current) resume_pc = *address; else @@ -996,7 +996,7 @@ static int cortex_a8_internal_restore(struct target *target, int current, /* Make sure that the Armv7 gdb thumb fixups does not * kill the return address */ - switch (armv4_5->core_state) + switch (arm->core_state) { case ARM_STATE_ARM: resume_pc &= 0xFFFFFFFC; @@ -1013,9 +1013,9 @@ static int cortex_a8_internal_restore(struct target *target, int current, return ERROR_FAIL; } LOG_DEBUG("resume pc = 0x%08" PRIx32, resume_pc); - buf_set_u32(armv4_5->pc->value, 0, 32, resume_pc); - armv4_5->pc->dirty = 1; - armv4_5->pc->valid = 1; + buf_set_u32(arm->pc->value, 0, 32, resume_pc); + arm->pc->dirty = 1; + arm->pc->valid = 1; /* restore dpm_mode at system halt */ dpm_modeswitch(&armv7a->dpm, ARM_MODE_ANY); /* called it now before restoring context because it uses cpu @@ -1030,7 +1030,7 @@ static int cortex_a8_internal_restore(struct target *target, int current, target->state = TARGET_RUNNING; /* registers are now invalid */ - register_cache_invalidate(armv4_5->core_cache); + register_cache_invalidate(arm->core_cache); #if 0 /* the front-end may request us not to handle breakpoints */ @@ -1053,8 +1053,8 @@ static int cortex_a8_internal_restore(struct target *target, int current, static int cortex_a8_internal_restart(struct target *target) { struct armv7a_common *armv7a = target_to_armv7a(target); - struct arm *armv4_5 = &armv7a->armv4_5_common; - struct adiv5_dap *swjdp = armv4_5->dap; + struct arm *arm = &armv7a->arm; + struct adiv5_dap *swjdp = arm->dap; int retval; uint32_t dscr; /* @@ -1104,7 +1104,7 @@ static int cortex_a8_internal_restart(struct target *target) target->state = TARGET_RUNNING; /* registers are now invalid */ - register_cache_invalidate(armv4_5->core_cache); + register_cache_invalidate(arm->core_cache); return ERROR_OK; } @@ -1179,8 +1179,8 @@ static int cortex_a8_debug_entry(struct target *target) struct working_area *regfile_working_area = NULL; struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target); struct armv7a_common *armv7a = target_to_armv7a(target); - struct arm *armv4_5 = &armv7a->armv4_5_common; - struct adiv5_dap *swjdp = armv7a->armv4_5_common.dap; + struct arm *arm = &armv7a->arm; + struct adiv5_dap *swjdp = armv7a->arm.dap; struct reg *reg; LOG_DEBUG("dscr = 0x%08" PRIx32, cortex_a8->cpudbg_dscr); @@ -1248,12 +1248,12 @@ static int cortex_a8_debug_entry(struct target *target) LOG_DEBUG("cpsr: %8.8" PRIx32, cpsr); - arm_set_cpsr(armv4_5, cpsr); + arm_set_cpsr(arm, cpsr); /* update cache */ for (i = 0; i <= ARM_PC; i++) { - reg = arm_reg_current(armv4_5, i); + reg = arm_reg_current(arm, i); buf_set_u32(reg->value, 0, 32, regfile[i]); reg->valid = 1; @@ -1272,7 +1272,7 @@ static int cortex_a8_debug_entry(struct target *target) regfile[ARM_PC] -= 8; } - reg = armv4_5->pc; + reg = arm->pc; buf_set_u32(reg->value, 0, 32, regfile[ARM_PC]); reg->dirty = reg->valid; } @@ -1309,7 +1309,7 @@ static int cortex_a8_post_debug_entry(struct target *target) int retval; /* MRC p15,0,