X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Fcortex_a.c;h=862fd554f87db89938a07d61c8e520e630191b30;hb=c527882121e3cc3d7cba5360c20928317c19a5cf;hp=c04804f85397039f118e6e8b8affd054c7dea5aa;hpb=2615bf4398f393ee1e387128064093dcd44749c8;p=openocd.git
diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c
old mode 100644
new mode 100755
index c04804f853..862fd554f8
--- a/src/target/cortex_a.c
+++ b/src/target/cortex_a.c
@@ -14,6 +14,9 @@
* Copyright (C) 2010 Ãyvind Harboe *
* oyvind.harboe@zylin.com *
* *
+ * Copyright (C) ST-Ericsson SA 2011 *
+ * michel.jaouen@stericsson.com : smp minimum support *
+ * *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
@@ -50,6 +53,10 @@ static int cortex_a8_debug_entry(struct target *target);
static int cortex_a8_restore_context(struct target *target, bool bpwp);
static int cortex_a8_set_breakpoint(struct target *target,
struct breakpoint *breakpoint, uint8_t matchmode);
+static int cortex_a8_set_context_breakpoint(struct target *target,
+ struct breakpoint *breakpoint, uint8_t matchmode);
+static int cortex_a8_set_hybrid_breakpoint(struct target *target,
+ struct breakpoint *breakpoint);
static int cortex_a8_unset_breakpoint(struct target *target,
struct breakpoint *breakpoint);
static int cortex_a8_dap_read_coreregister_u32(struct target *target,
@@ -59,12 +66,6 @@ static int cortex_a8_dap_write_coreregister_u32(struct target *target,
static int cortex_a8_mmu(struct target *target, int *enabled);
static int cortex_a8_virt2phys(struct target *target,
uint32_t virt, uint32_t *phys);
-static int cortex_a8_disable_mmu_caches(struct target *target, int mmu,
- int d_u_cache, int i_cache);
-static int cortex_a8_enable_mmu_caches(struct target *target, int mmu,
- int d_u_cache, int i_cache);
-static int cortex_a8_get_ttb(struct target *target, uint32_t *result);
-
/*
* FIXME do topology discovery using the ROM; don't
@@ -75,13 +76,106 @@ static int cortex_a8_get_ttb(struct target *target, uint32_t *result);
#define swjdp_memoryap 0
#define swjdp_debugap 1
+/* restore cp15_control_reg at resume */
+static int cortex_a8_restore_cp15_control_reg(struct target* target)
+{
+ int retval = ERROR_OK;
+ struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
+ struct armv7a_common *armv7a = target_to_armv7a(target);
+
+ if (cortex_a8->cp15_control_reg !=cortex_a8->cp15_control_reg_curr)
+ {
+ cortex_a8->cp15_control_reg_curr = cortex_a8->cp15_control_reg;
+ //LOG_INFO("cp15_control_reg: %8.8" PRIx32, cortex_a8->cp15_control_reg);
+ retval = armv7a->arm.mcr(target, 15,
+ 0, 0, /* op1, op2 */
+ 1, 0, /* CRn, CRm */
+ cortex_a8->cp15_control_reg);
+ }
+ return retval;
+}
+
+/* check address before cortex_a8_apb read write access with mmu on
+ * remove apb predictible data abort */
+static int cortex_a8_check_address(struct target *target, uint32_t address)
+{
+ struct armv7a_common *armv7a = target_to_armv7a(target);
+ struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
+ uint32_t os_border = armv7a->armv7a_mmu.os_border;
+ if ((address < os_border) &&
+ (armv7a->arm.core_mode == ARM_MODE_SVC)) {
+ LOG_ERROR("%x access in userspace and target in supervisor",address);
+ return ERROR_FAIL;
+ }
+ if ((address >= os_border) &&
+ (cortex_a8->curr_mode != ARM_MODE_SVC)) {
+ dpm_modeswitch(&armv7a->dpm, ARM_MODE_SVC);
+ cortex_a8->curr_mode = ARM_MODE_SVC;
+ LOG_INFO("%x access in kernel space and target not in supervisor",
+ address);
+ return ERROR_OK;
+ }
+ if ((address < os_border) &&
+ (cortex_a8->curr_mode == ARM_MODE_SVC)) {
+ dpm_modeswitch(&armv7a->dpm, ARM_MODE_ANY);
+ cortex_a8->curr_mode = ARM_MODE_ANY;
+ }
+ return ERROR_OK;
+}
+/* modify cp15_control_reg in order to enable or disable mmu for :
+ * - virt2phys address conversion
+ * - read or write memory in phys or virt address */
+static int cortex_a8_mmu_modify(struct target *target, int enable)
+{
+ struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
+ struct armv7a_common *armv7a = target_to_armv7a(target);
+ int retval = ERROR_OK;
+ if (enable)
+ {
+ /* if mmu enabled at target stop and mmu not enable */
+ if (!(cortex_a8->cp15_control_reg & 0x1U))
+ {
+ LOG_ERROR("trying to enable mmu on target stopped with mmu disable");
+ return ERROR_FAIL;
+ }
+ if (!(cortex_a8->cp15_control_reg_curr & 0x1U))
+ {
+ cortex_a8->cp15_control_reg_curr |= 0x1U;
+ retval = armv7a->arm.mcr(target, 15,
+ 0, 0, /* op1, op2 */
+ 1, 0, /* CRn, CRm */
+ cortex_a8->cp15_control_reg_curr);
+ }
+ }
+ else
+ {
+ if (cortex_a8->cp15_control_reg_curr & 0x4U)
+ {
+ /* data cache is active */
+ cortex_a8->cp15_control_reg_curr &= ~0x4U;
+ /* flush data cache armv7 function to be called */
+ if (armv7a->armv7a_mmu.armv7a_cache.flush_all_data_cache)
+ armv7a->armv7a_mmu.armv7a_cache.flush_all_data_cache(target);
+ }
+ if ( (cortex_a8->cp15_control_reg_curr & 0x1U))
+ {
+ cortex_a8->cp15_control_reg_curr &= ~0x1U;
+ retval = armv7a->arm.mcr(target, 15,
+ 0, 0, /* op1, op2 */
+ 1, 0, /* CRn, CRm */
+ cortex_a8->cp15_control_reg_curr);
+ }
+ }
+ return retval;
+}
+
/*
* Cortex-A8 Basic debug access, very low level assumes state is saved
*/
static int cortex_a8_init_debug_access(struct target *target)
{
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct adiv5_dap *swjdp = &armv7a->dap;
+ struct adiv5_dap *swjdp = armv7a->arm.dap;
int retval;
uint32_t dummy;
@@ -129,7 +223,7 @@ static int cortex_a8_exec_opcode(struct target *target,
uint32_t dscr;
int retval;
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct adiv5_dap *swjdp = &armv7a->dap;
+ struct adiv5_dap *swjdp = armv7a->arm.dap;
dscr = dscr_p ? *dscr_p : 0;
@@ -191,7 +285,7 @@ static int cortex_a8_read_regs_through_mem(struct target *target, uint32_t addre
{
int retval = ERROR_OK;
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct adiv5_dap *swjdp = &armv7a->dap;
+ struct adiv5_dap *swjdp = armv7a->arm.dap;
retval = cortex_a8_dap_read_coreregister_u32(target, regfile, 0);
if (retval != ERROR_OK)
@@ -216,7 +310,7 @@ static int cortex_a8_dap_read_coreregister_u32(struct target *target,
uint8_t reg = regnum&0xFF;
uint32_t dscr = 0;
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct adiv5_dap *swjdp = &armv7a->dap;
+ struct adiv5_dap *swjdp = armv7a->arm.dap;
if (reg > 17)
return retval;
@@ -286,7 +380,7 @@ static int cortex_a8_dap_write_coreregister_u32(struct target *target,
uint8_t Rd = regnum&0xFF;
uint32_t dscr;
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct adiv5_dap *swjdp = &armv7a->dap;
+ struct adiv5_dap *swjdp = armv7a->arm.dap;
LOG_DEBUG("register %i, value 0x%08" PRIx32, regnum, value);
@@ -320,6 +414,7 @@ static int cortex_a8_dap_write_coreregister_u32(struct target *target,
/* DCCRX to Rn, "MRC p14, 0, Rn, c0, c5, 0", 0xEE10nE15 */
retval = cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, Rd, 0, 5, 0),
&dscr);
+
if (retval != ERROR_OK)
return retval;
}
@@ -369,7 +464,7 @@ static int cortex_a8_dap_write_memap_register_u32(struct target *target, uint32_
{
int retval;
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct adiv5_dap *swjdp = &armv7a->dap;
+ struct adiv5_dap *swjdp = armv7a->arm.dap;
retval = mem_ap_sel_write_atomic_u32(swjdp, swjdp_debugap, address, value);
@@ -395,14 +490,14 @@ static inline struct cortex_a8_common *dpm_to_a8(struct arm_dpm *dpm)
static int cortex_a8_write_dcc(struct cortex_a8_common *a8, uint32_t data)
{
LOG_DEBUG("write DCC 0x%08" PRIx32, data);
- return mem_ap_sel_write_u32(&a8->armv7a_common.dap, swjdp_debugap,
- a8->armv7a_common.debug_base + CPUDBG_DTRRX, data);
+ return mem_ap_sel_write_u32(a8->armv7a_common.arm.dap,
+ swjdp_debugap,a8->armv7a_common.debug_base + CPUDBG_DTRRX, data);
}
static int cortex_a8_read_dcc(struct cortex_a8_common *a8, uint32_t *data,
uint32_t *dscr_p)
{
- struct adiv5_dap *swjdp = &a8->armv7a_common.dap;
+ struct adiv5_dap *swjdp = a8->armv7a_common.arm.dap;
uint32_t dscr = DSCR_INSTR_COMP;
int retval;
@@ -439,7 +534,7 @@ static int cortex_a8_read_dcc(struct cortex_a8_common *a8, uint32_t *data,
static int cortex_a8_dpm_prepare(struct arm_dpm *dpm)
{
struct cortex_a8_common *a8 = dpm_to_a8(dpm);
- struct adiv5_dap *swjdp = &a8->armv7a_common.dap;
+ struct adiv5_dap *swjdp = a8->armv7a_common.arm.dap;
uint32_t dscr;
int retval;
@@ -466,7 +561,7 @@ static int cortex_a8_dpm_prepare(struct arm_dpm *dpm)
LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32, dscr);
/* Clear DCCRX */
retval = cortex_a8_exec_opcode(
- a8->armv7a_common.armv4_5_common.target,
+ a8->armv7a_common.arm.target,
ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
&dscr);
if (retval != ERROR_OK)
@@ -494,7 +589,7 @@ static int cortex_a8_instr_write_data_dcc(struct arm_dpm *dpm,
return retval;
return cortex_a8_exec_opcode(
- a8->armv7a_common.armv4_5_common.target,
+ a8->armv7a_common.arm.target,
opcode,
&dscr);
}
@@ -512,7 +607,7 @@ static int cortex_a8_instr_write_data_r0(struct arm_dpm *dpm,
/* DCCRX to R0, "MCR p14, 0, R0, c0, c5, 0", 0xEE000E15 */
retval = cortex_a8_exec_opcode(
- a8->armv7a_common.armv4_5_common.target,
+ a8->armv7a_common.arm.target,
ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
&dscr);
if (retval != ERROR_OK)
@@ -520,7 +615,7 @@ static int cortex_a8_instr_write_data_r0(struct arm_dpm *dpm,
/* then the opcode, taking data from R0 */
retval = cortex_a8_exec_opcode(
- a8->armv7a_common.armv4_5_common.target,
+ a8->armv7a_common.arm.target,
opcode,
&dscr);
@@ -547,7 +642,7 @@ static int cortex_a8_instr_read_data_dcc(struct arm_dpm *dpm,
/* the opcode, writing data to DCC */
retval = cortex_a8_exec_opcode(
- a8->armv7a_common.armv4_5_common.target,
+ a8->armv7a_common.arm.target,
opcode,
&dscr);
if (retval != ERROR_OK)
@@ -566,7 +661,7 @@ static int cortex_a8_instr_read_data_r0(struct arm_dpm *dpm,
/* the opcode, writing data to R0 */
retval = cortex_a8_exec_opcode(
- a8->armv7a_common.armv4_5_common.target,
+ a8->armv7a_common.arm.target,
opcode,
&dscr);
if (retval != ERROR_OK)
@@ -574,7 +669,7 @@ static int cortex_a8_instr_read_data_r0(struct arm_dpm *dpm,
/* write R0 to DCC */
retval = cortex_a8_exec_opcode(
- a8->armv7a_common.armv4_5_common.target,
+ a8->armv7a_common.arm.target,
ARMV4_5_MCR(14, 0, 0, 0, 5, 0),
&dscr);
if (retval != ERROR_OK)
@@ -648,7 +743,7 @@ static int cortex_a8_dpm_setup(struct cortex_a8_common *a8, uint32_t didr)
struct arm_dpm *dpm = &a8->armv7a_common.dpm;
int retval;
- dpm->arm = &a8->armv7a_common.armv4_5_common;
+ dpm->arm = &a8->armv7a_common.arm;
dpm->didr = didr;
dpm->prepare = cortex_a8_dpm_prepare;
@@ -670,7 +765,54 @@ static int cortex_a8_dpm_setup(struct cortex_a8_common *a8, uint32_t didr)
return retval;
}
+static struct target *get_cortex_a8(struct target *target, int32_t coreid)
+{
+struct target_list *head;
+struct target *curr;
+
+ head = target->head;
+ while(head != (struct target_list*)NULL)
+ {
+ curr = head->target;
+ if ((curr->coreid == coreid) && (curr->state == TARGET_HALTED))
+ {
+ return curr;
+ }
+ head = head->next;
+ }
+ return target;
+}
+static int cortex_a8_halt(struct target *target);
+
+static int cortex_a8_halt_smp(struct target *target)
+{
+ int retval = 0;
+ struct target_list *head;
+ struct target *curr;
+ head = target->head;
+ while(head != (struct target_list*)NULL)
+ {
+ curr = head->target;
+ if ((curr != target) && (curr->state!= TARGET_HALTED))
+ {
+ retval += cortex_a8_halt(curr);
+ }
+ head = head->next;
+ }
+ return retval;
+}
+static int update_halt_gdb(struct target *target)
+{
+ int retval = 0;
+ if (target->gdb_service->core[0]==-1)
+ {
+ target->gdb_service->target = target;
+ target->gdb_service->core[0] = target->coreid;
+ retval += cortex_a8_halt_smp(target);
+ }
+ return retval;
+}
/*
* Cortex-A8 Run control
@@ -682,9 +824,22 @@ static int cortex_a8_poll(struct target *target)
uint32_t dscr;
struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
- struct adiv5_dap *swjdp = &armv7a->dap;
+ struct adiv5_dap *swjdp = armv7a->arm.dap;
enum target_state prev_target_state = target->state;
-
+ // toggle to another core is done by gdb as follow
+ // maint packet J core_id
+ // continue
+ // the next polling trigger an halt event sent to gdb
+ if ((target->state == TARGET_HALTED) && (target->smp) &&
+ (target->gdb_service) &&
+ (target->gdb_service->target==NULL) )
+ {
+ target->gdb_service->target =
+ get_cortex_a8(target, target->gdb_service->core[1]);
+ target_call_event_callbacks(target,
+ TARGET_EVENT_HALTED);
+ return retval;
+ }
retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
if (retval != ERROR_OK)
@@ -706,7 +861,12 @@ static int cortex_a8_poll(struct target *target)
retval = cortex_a8_debug_entry(target);
if (retval != ERROR_OK)
return retval;
-
+ if (target->smp)
+ {
+ retval = update_halt_gdb(target);
+ if (retval != ERROR_OK)
+ return retval;
+ }
target_call_event_callbacks(target,
TARGET_EVENT_HALTED);
}
@@ -717,6 +877,12 @@ static int cortex_a8_poll(struct target *target)
retval = cortex_a8_debug_entry(target);
if (retval != ERROR_OK)
return retval;
+ if (target->smp)
+ {
+ retval = update_halt_gdb(target);
+ if (retval != ERROR_OK)
+ return retval;
+ }
target_call_event_callbacks(target,
TARGET_EVENT_DEBUG_HALTED);
@@ -741,7 +907,7 @@ static int cortex_a8_halt(struct target *target)
int retval = ERROR_OK;
uint32_t dscr;
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct adiv5_dap *swjdp = &armv7a->dap;
+ struct adiv5_dap *swjdp = armv7a->arm.dap;
/*
* Tell the core to be halted by writing DRCR with 0x1
@@ -788,16 +954,13 @@ static int cortex_a8_halt(struct target *target)
return ERROR_OK;
}
-static int cortex_a8_resume(struct target *target, int current,
- uint32_t address, int handle_breakpoints, int debug_execution)
+static int cortex_a8_internal_restore(struct target *target, int current,
+ uint32_t *address, int handle_breakpoints, int debug_execution)
{
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct arm *armv4_5 = &armv7a->armv4_5_common;
- struct adiv5_dap *swjdp = &armv7a->dap;
+ struct arm *arm = &armv7a->arm;
int retval;
-
-// struct breakpoint *breakpoint = NULL;
- uint32_t resume_pc, dscr;
+ uint32_t resume_pc;
if (!debug_execution)
target_free_all_working_areas(target);
@@ -824,14 +987,16 @@ static int cortex_a8_resume(struct target *target, int current,
#endif
/* current = 1: continue on current pc, otherwise continue at
*/
- resume_pc = buf_get_u32(armv4_5->pc->value, 0, 32);
+ resume_pc = buf_get_u32(arm->pc->value, 0, 32);
if (!current)
- resume_pc = address;
+ resume_pc = *address;
+ else
+ *address = resume_pc;
/* Make sure that the Armv7 gdb thumb fixups does not
* kill the return address
*/
- switch (armv4_5->core_state)
+ switch (arm->core_state)
{
case ARM_STATE_ARM:
resume_pc &= 0xFFFFFFFC;
@@ -848,13 +1013,24 @@ static int cortex_a8_resume(struct target *target, int current,
return ERROR_FAIL;
}
LOG_DEBUG("resume pc = 0x%08" PRIx32, resume_pc);
- buf_set_u32(armv4_5->pc->value, 0, 32, resume_pc);
- armv4_5->pc->dirty = 1;
- armv4_5->pc->valid = 1;
-
+ buf_set_u32(arm->pc->value, 0, 32, resume_pc);
+ arm->pc->dirty = 1;
+ arm->pc->valid = 1;
+ /* restore dpm_mode at system halt */
+ dpm_modeswitch(&armv7a->dpm, ARM_MODE_ANY);
+ /* called it now before restoring context because it uses cpu
+ * register r0 for restoring cp15 control register */
+ retval = cortex_a8_restore_cp15_control_reg(target);
+ if (retval != ERROR_OK)
+ return retval;
retval = cortex_a8_restore_context(target, handle_breakpoints);
if (retval != ERROR_OK)
return retval;
+ target->debug_reason = DBG_REASON_NOTHALTED;
+ target->state = TARGET_RUNNING;
+
+ /* registers are now invalid */
+ register_cache_invalidate(arm->core_cache);
#if 0
/* the front-end may request us not to handle breakpoints */
@@ -871,8 +1047,17 @@ static int cortex_a8_resume(struct target *target, int current,
}
#endif
+ return retval;
+}
- /*
+static int cortex_a8_internal_restart(struct target *target)
+{
+ struct armv7a_common *armv7a = target_to_armv7a(target);
+ struct arm *arm = &armv7a->arm;
+ struct adiv5_dap *swjdp = arm->dap;
+ int retval;
+ uint32_t dscr;
+/*
* Restart core and wait for it to be started. Clear ITRen and sticky
* exception flags: see ARMv7 ARM, C5.9.
*
@@ -894,7 +1079,8 @@ static int cortex_a8_resume(struct target *target, int current,
return retval;
retval = mem_ap_sel_write_atomic_u32(swjdp, swjdp_debugap,
- armv7a->debug_base + CPUDBG_DRCR, DRCR_RESTART | DRCR_CLEAR_EXCEPTIONS);
+ armv7a->debug_base + CPUDBG_DRCR, DRCR_RESTART |
+ DRCR_CLEAR_EXCEPTIONS);
if (retval != ERROR_OK)
return retval;
@@ -918,19 +1104,68 @@ static int cortex_a8_resume(struct target *target, int current,
target->state = TARGET_RUNNING;
/* registers are now invalid */
- register_cache_invalidate(armv4_5->core_cache);
+ register_cache_invalidate(arm->core_cache);
+
+ return ERROR_OK;
+}
+
+static int cortex_a8_restore_smp(struct target *target,int handle_breakpoints)
+{
+ int retval = 0;
+ struct target_list *head;
+ struct target *curr;
+ uint32_t address;
+ head = target->head;
+ while(head != (struct target_list*)NULL)
+ {
+ curr = head->target;
+ if ((curr != target) && (curr->state != TARGET_RUNNING))
+ {
+ /* resume current address , not in step mode */
+ retval += cortex_a8_internal_restore(curr, 1, &address,
+ handle_breakpoints, 0);
+ retval += cortex_a8_internal_restart(curr);
+ }
+ head = head->next;
+
+ }
+ return retval;
+}
+
+static int cortex_a8_resume(struct target *target, int current,
+ uint32_t address, int handle_breakpoints, int debug_execution)
+{
+ int retval = 0;
+ /* dummy resume for smp toggle in order to reduce gdb impact */
+ if ((target->smp) && (target->gdb_service->core[1]!=-1))
+ {
+ /* simulate a start and halt of target */
+ target->gdb_service->target = NULL;
+ target->gdb_service->core[0] = target->gdb_service->core[1];
+ /* fake resume at next poll we play the target core[1], see poll*/
+ target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
+ return 0;
+ }
+ cortex_a8_internal_restore(target, current, &address, handle_breakpoints, debug_execution);
+ if (target->smp)
+ { target->gdb_service->core[0] = -1;
+ retval = cortex_a8_restore_smp(target, handle_breakpoints);
+ if (retval != ERROR_OK)
+ return retval;
+ }
+ cortex_a8_internal_restart(target);
if (!debug_execution)
{
target->state = TARGET_RUNNING;
target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
- LOG_DEBUG("target resumed at 0x%" PRIx32, resume_pc);
+ LOG_DEBUG("target resumed at 0x%" PRIx32, address);
}
else
{
target->state = TARGET_DEBUG_RUNNING;
target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
- LOG_DEBUG("target debug resumed at 0x%" PRIx32, resume_pc);
+ LOG_DEBUG("target debug resumed at 0x%" PRIx32, address);
}
return ERROR_OK;
@@ -944,8 +1179,8 @@ static int cortex_a8_debug_entry(struct target *target)
struct working_area *regfile_working_area = NULL;
struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct arm *armv4_5 = &armv7a->armv4_5_common;
- struct adiv5_dap *swjdp = &armv7a->dap;
+ struct arm *arm = &armv7a->arm;
+ struct adiv5_dap *swjdp = armv7a->arm.dap;
struct reg *reg;
LOG_DEBUG("dscr = 0x%08" PRIx32, cortex_a8->cpudbg_dscr);
@@ -1007,17 +1242,18 @@ static int cortex_a8_debug_entry(struct target *target)
/* read Current PSR */
retval = cortex_a8_dap_read_coreregister_u32(target, &cpsr, 16);
+ /* store current cpsr */
if (retval != ERROR_OK)
return retval;
LOG_DEBUG("cpsr: %8.8" PRIx32, cpsr);
- arm_set_cpsr(armv4_5, cpsr);
+ arm_set_cpsr(arm, cpsr);
/* update cache */
for (i = 0; i <= ARM_PC; i++)
{
- reg = arm_reg_current(armv4_5, i);
+ reg = arm_reg_current(arm, i);
buf_set_u32(reg->value, 0, 32, regfile[i]);
reg->valid = 1;
@@ -1036,7 +1272,7 @@ static int cortex_a8_debug_entry(struct target *target)
regfile[ARM_PC] -= 8;
}
- reg = armv4_5->pc;
+ reg = arm->pc;
buf_set_u32(reg->value, 0, 32, regfile[ARM_PC]);
reg->dirty = reg->valid;
}
@@ -1073,38 +1309,27 @@ static int cortex_a8_post_debug_entry(struct target *target)
int retval;
/* MRC p15,0,