X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Fcortex_a.h;h=685621c6b1d03c92d18032c05bc32752c772de4f;hb=4f371e8eed5c4e479d326cf09f7827884c23b947;hp=ebf79b88c745fba4d244d025ca9d365e58d65431;hpb=6e32887f917b8e5a870e2d485139820ee5161b4f;p=openocd.git

diff --git a/src/target/cortex_a.h b/src/target/cortex_a.h
index ebf79b88c7..685621c6b1 100644
--- a/src/target/cortex_a.h
+++ b/src/target/cortex_a.h
@@ -22,13 +22,11 @@
  *   GNU General Public License for more details.                          *
  *                                                                         *
  *   You should have received a copy of the GNU General Public License     *
- *   along with this program; if not, write to the                         *
- *   Free Software Foundation, Inc.,                                       *
- *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
+ *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  ***************************************************************************/
 
-#ifndef CORTEX_A_H
-#define CORTEX_A_H
+#ifndef OPENOCD_TARGET_CORTEX_A_H
+#define OPENOCD_TARGET_CORTEX_A_H
 
 #include "armv7a.h"
 
@@ -55,17 +53,33 @@
 
 #define CORTEX_A_PADDRDBG_CPU_SHIFT 13
 
+enum cortex_a_isrmasking_mode {
+	CORTEX_A_ISRMASK_OFF,
+	CORTEX_A_ISRMASK_ON,
+};
+
+enum cortex_a_dacrfixup_mode {
+	CORTEX_A_DACRFIXUP_OFF,
+	CORTEX_A_DACRFIXUP_ON
+};
+
 struct cortex_a_brp {
-	int used;
+	bool used;
 	int type;
 	uint32_t value;
 	uint32_t control;
-	uint8_t BRPn;
+	uint8_t brpn;
+};
+
+struct cortex_a_wrp {
+	bool used;
+	uint32_t value;
+	uint32_t control;
+	uint8_t wrpn;
 };
 
 struct cortex_a_common {
 	int common_magic;
-	struct arm_jtag jtag_info;
 
 	/* Context information */
 	uint32_t cpudbg_dscr;
@@ -74,23 +88,27 @@ struct cortex_a_common {
 	uint32_t cp15_control_reg;
 	/* latest cp15 register value written and cpsr processor mode */
 	uint32_t cp15_control_reg_curr;
+	/* auxiliary control reg */
+	uint32_t cp15_aux_control_reg;
+	/* DACR */
+	uint32_t cp15_dacr_reg;
 	enum arm_mode curr_mode;
 
-
 	/* Breakpoint register pairs */
 	int brp_num_context;
 	int brp_num;
 	int brp_num_available;
 	struct cortex_a_brp *brp_list;
-
-	/* Use cortex_a_read_regs_through_mem for fast register reads */
-	int fast_reg_read;
+	int wrp_num;
+	int wrp_num_available;
+	struct cortex_a_wrp *wrp_list;
 
 	uint32_t cpuid;
-	uint32_t ctypr;
-	uint32_t ttypr;
 	uint32_t didr;
 
+	enum cortex_a_isrmasking_mode isrmasking_mode;
+	enum cortex_a_dacrfixup_mode dacrfixup_mode;
+
 	struct armv7a_common armv7a_common;
 
 };
@@ -101,4 +119,4 @@ target_to_cortex_a(struct target *target)
 	return container_of(target->arch_info, struct cortex_a_common, armv7a_common.arm);
 }
 
-#endif /* CORTEX_A_H */
+#endif /* OPENOCD_TARGET_CORTEX_A_H */